Re: [PATCH] MAINTAINERS: update radeon/amdgpu/amdkfd git trees

2021-01-08 Thread Abramov, Slava 
[AMD Official Use Only - Internal Distribution Only]

Why not just https://gitlab.freedesktop.org/agd5f/linux ?

From: amd-gfx  on behalf of Alex Deucher 

Sent: Friday, January 8, 2021 2:30 PM
To: amd-gfx list ; Maling list - DRI developers 
; Dave Airlie ; Daniel 
Vetter 
Cc: Deucher, Alexander 
Subject: Re: [PATCH] MAINTAINERS: update radeon/amdgpu/amdkfd git trees

On Tue, Jan 5, 2021 at 3:15 PM Alex Deucher  wrote:
>
> FDO is out of space, so move to gitlab.
>
> Signed-off-by: Alex Deucher 

Ping?  Any objections?

Alex

> ---
>  MAINTAINERS | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index eb18459c1d16..e2877be6b10d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -907,7 +907,7 @@ AMD KFD
>  M: Felix Kuehling 
>  L: amd-gfx@lists.freedesktop.org
>  S: Supported
> -T: git git://people.freedesktop.org/~agd5f/linux
> +T: git 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fagd5f%2Flinux.gitdata=04%7C01%7Cslava.abramov%40amd.com%7Cb4e8adc5393c4b052d6908d8b40bd5db%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637457310677496846%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=xK4Oo8juN%2FoF1jVnLclPtt9MKLzRQ3GPiercdH9ogFE%3Dreserved=0
>  F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd*.[ch]
>  F: drivers/gpu/drm/amd/amdkfd/
>  F: drivers/gpu/drm/amd/include/cik_structs.h
> @@ -14596,7 +14596,7 @@ M:  Alex Deucher 
>  M: Christian König 
>  L: amd-gfx@lists.freedesktop.org
>  S: Supported
> -T: git git://people.freedesktop.org/~agd5f/linux
> +T: git 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fagd5f%2Flinux.gitdata=04%7C01%7Cslava.abramov%40amd.com%7Cb4e8adc5393c4b052d6908d8b40bd5db%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637457310677506842%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=ANez%2BLHaergD6Lae8arcJDyibaf5yPgRyrBfzBpd3vY%3Dreserved=0
>  F: drivers/gpu/drm/amd/
>  F: drivers/gpu/drm/radeon/
>  F: include/uapi/drm/amdgpu_drm.h
> --
> 2.29.2
>
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Re: [PATCH] drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.c

2020-10-27 Thread Abramov, Slava 
[AMD Official Use Only - Internal Distribution Only]

Looks sane to me.

Acked-by: Slava Abramov 

From: amd-gfx  on behalf of Alex Deucher 

Sent: Tuesday, October 27, 2020 11:20 AM
To: amd-gfx list 
Cc: Deucher, Alexander 
Subject: Re: [PATCH] drm/amdgpu/display: re-add surface size calculation in 
dcn30_hwseq.c

Ping?

On Mon, Oct 26, 2020 at 12:14 PM Alex Deucher  wrote:
>
> This is required for MALL.  Was accidently removed in PRS update.
>
> Fixes: 48e48e598478 ("drm/amd/display: Disable idle optimization when PSR is 
> enabled")
> Fixes: 52f2e83e2fe5 ("drm/amdgpu/display: add MALL support (v2)")
> Signed-off-by: Alex Deucher 
> ---
>  .../gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c| 15 +++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index f3ae208850b0..cc2eca8c9a62 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -715,6 +715,21 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, 
> bool enable)
> break;
> }
>
> +   if (dc->current_state->stream_count == 1 // single 
> display only
> +   && 
> dc->current_state->stream_status[0].plane_count == 1 // single surface only
> +   && 
> dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part
>  == 0 // no VM
> +   // Only 8 and 16 bit formats
> +   && 
> dc->current_state->stream_status[0].plane_states[0]->format <= 
> SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
> +   && 
> dc->current_state->stream_status[0].plane_states[0]->format >= 
> SURFACE_PIXEL_FORMAT_GRPH_ARGB) {
> +   surface_size = 
> dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch 
> *
> +   
> dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height
>  *
> +   
> (dc->current_state->stream_status[0].plane_states[0]->format >= 
> SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?
> +8 : 4);
> +   } else {
> +   // TODO: remove hard code size
> +   surface_size = 128 * 1024 * 1024;
> +   }
> +
> // TODO: remove hard code size
> if (surface_size < 128 * 1024 * 1024) {
> refresh_hz = div_u64((unsigned long long) 
> dc->current_state->streams[0]->timing.pix_clk_100hz *
> --
> 2.25.4
>
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Re: [PATCH 1/2] drm/amdgpu/display: fix abm shift and mask lists for DCN3.01/3.02

2020-10-26 Thread Abramov, Slava 
[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Slava Abramov 

From: amd-gfx  on behalf of Alex Deucher 

Sent: Monday, October 26, 2020 11:57 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander 
Subject: [PATCH 1/2] drm/amdgpu/display: fix abm shift and mask lists for 
DCN3.01/3.02

Updating these were missed.

Fixes: 2c8193fc72b1c5 ("drm/amd/display: Refactor ABM_MASK_SH_LIST_DCN301 
naming")
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 4 ++--
 drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index fe46a0b911fc..5a47b4106b7b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -363,11 +363,11 @@ static const struct dce_abm_registers abm_regs[] = {
 };

 static const struct dce_abm_shift abm_shift = {
-   ABM_MASK_SH_LIST_DCN301(__SHIFT)
+   ABM_MASK_SH_LIST_DCN30(__SHIFT)
 };

 static const struct dce_abm_mask abm_mask = {
-   ABM_MASK_SH_LIST_DCN301(_MASK)
+   ABM_MASK_SH_LIST_DCN30(_MASK)
 };

 #define audio_regs(id)\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index 38e807f22060..c4ffed95d35e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -1276,11 +1276,11 @@ static const struct dce_abm_registers abm_regs[] = {
 };

 static const struct dce_abm_shift abm_shift = {
-   ABM_MASK_SH_LIST_DCN301(__SHIFT)
+   ABM_MASK_SH_LIST_DCN30(__SHIFT)
 };

 static const struct dce_abm_mask abm_mask = {
-   ABM_MASK_SH_LIST_DCN301(_MASK)
+   ABM_MASK_SH_LIST_DCN30(_MASK)
 };

 static bool dcn302_resource_construct(
--
2.25.4

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Re: [PATCH 2/2] drm/amdgpu/display: drop disconnect_pipes callback for DCN3.01

2020-10-26 Thread Abramov, Slava 
[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Slava Abramov 

From: amd-gfx  on behalf of Alex Deucher 

Sent: Monday, October 26, 2020 11:57 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander 
Subject: [PATCH 2/2] drm/amdgpu/display: drop disconnect_pipes callback for 
DCN3.01

Was missed in a later update.

Fixes: 4d269c40066e ("drm/amd/display: Update GSL state if leaving immediate 
flip")
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c 
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
index d4bebb3a52e4..6d9587c39efd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
@@ -37,7 +37,6 @@ static const struct hw_sequencer_funcs dcn301_funcs = {
 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 .apply_ctx_for_surface = NULL,
 .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
-   .disconnect_pipes = dcn10_disconnect_pipes,
 .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
 .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
 .update_plane_addr = dcn20_update_plane_addr,
--
2.25.4

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Re: [PATCH] drm/amdgpu: No sysfs, not an error condition

2020-09-16 Thread Abramov, Slava 
[AMD Official Use Only - Internal Distribution Only]

​Acked-by: Slava Abramov 


From: amd-gfx  on behalf of Luben Tuikov 

Sent: Wednesday, September 16, 2020 1:08 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Tuikov, Luben 

Subject: [PATCH] drm/amdgpu: No sysfs, not an error condition

Not being able to create amdgpu sysfs attributes
is not a fatal error warranting not to continue
to try to bring up the display. Thus, if we get
an error trying to create amdgpu sysfs attrs,
report it and continue on to try to bring up
a display.

Signed-off-by: Luben Tuikov 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5d702f6e77de..62174f5e8311 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3400,10 +3400,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 flush_delayed_work(>delayed_init_work);

 r = sysfs_create_files(>dev->kobj, amdgpu_dev_attributes);
-   if (r) {
+   if (r)
 dev_err(adev->dev, "Could not create amdgpu device attr\n");
-   return r;
-   }

 if (IS_ENABLED(CONFIG_PERF_EVENTS))
 r = amdgpu_pmu_init(adev);
--
2.28.0.394.ge197136389

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Re: [PATCH] drm/amd/display: avoid 64-bit division

2019-07-09 Thread Abramov, Slava 
Hi Arnd!


Thanks for bisecting this issue.


I wonder whether you are going to commit your patch or planning to update it 
and it's still in your work queue.  We have one of our 32-bit builds failing 
because of this issue, so that I would like either to fix it or wait to your 
fix if it has chances to go upstream today.


Sincerely,



Slava Abramov


From: amd-gfx  on behalf of Arnd 
Bergmann 
Sent: Monday, July 8, 2019 9:52:08 AM
To: Wentland, Harry; Li, Sun peng (Leo); Deucher, Alexander; Koenig, Christian; 
Zhou, David(ChunMing); David Airlie; Daniel Vetter
Cc: Liu, Charlene; Park, Chris; Arnd Bergmann; Cheng, Tony; Francis, David; 
linux-ker...@vger.kernel.org; amd-gfx@lists.freedesktop.org; Cornij, Nikola; 
Laktyushkin, Dmytro; dri-de...@lists.freedesktop.org; Lei, Jun; Lakha, 
Bhawanpreet; Koo, Anthony
Subject: [PATCH] drm/amd/display: avoid 64-bit division

On 32-bit architectures, dividing a 64-bit integer in the kernel
leads to a link error:

ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!

Change the two recently introduced instances to a multiply+shift
operation that is also much cheaper on 32-bit architectures.
We can do that here, since both of them are really 32-bit numbers
that change a few percent.

Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to dc_link")
Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for 
NV")
Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c17db5c144aa..8dbf759eba45 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3072,8 +3072,8 @@ uint32_t dc_link_bandwidth_kbps(
  * but the difference is minimal and is in a safe direction,
  * which all works well around potential ambiguity of DP 1.4a 
spec.
  */
-   long long fec_link_bw_kbps = link_bw_kbps * 970LL;
-   link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL);
+   link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
+  link_bw_kbps, 32);
 }
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index b35327bafbc5..70ac8a95d2db 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2657,7 +2657,7 @@ static void update_bounding_box(struct dc *dc, struct 
_vcs_dpi_soc_bounding_box_
 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 
1000;

 // FCLK:UCLK ratio is 1.08
-   min_fclk_required_by_uclk = ((unsigned long 
long)uclk_states[i]) * 1080 / 100;
+   min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 
/ 100, uclk_states[i], 32);

 calculated_states[i].fabricclk_mhz = 
(min_fclk_required_by_uclk < min_dcfclk) ?
 min_dcfclk : min_fclk_required_by_uclk;
--
2.20.0

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Re: [PATCH] drm/amd/display: avoid 64-bit division

2019-07-08 Thread Abramov, Slava 
Acked-by: Slava Abramov 

Tested-by: Slava Abramov 


From: amd-gfx  on behalf of Arnd 
Bergmann 
Sent: Monday, July 8, 2019 9:52:08 AM
To: Wentland, Harry; Li, Sun peng (Leo); Deucher, Alexander; Koenig, Christian; 
Zhou, David(ChunMing); David Airlie; Daniel Vetter
Cc: Liu, Charlene; Park, Chris; Arnd Bergmann; Cheng, Tony; Francis, David; 
linux-ker...@vger.kernel.org; amd-gfx@lists.freedesktop.org; Cornij, Nikola; 
Laktyushkin, Dmytro; dri-de...@lists.freedesktop.org; Lei, Jun; Lakha, 
Bhawanpreet; Koo, Anthony
Subject: [PATCH] drm/amd/display: avoid 64-bit division

On 32-bit architectures, dividing a 64-bit integer in the kernel
leads to a link error:

ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!

Change the two recently introduced instances to a multiply+shift
operation that is also much cheaper on 32-bit architectures.
We can do that here, since both of them are really 32-bit numbers
that change a few percent.

Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to dc_link")
Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for 
NV")
Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c17db5c144aa..8dbf759eba45 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3072,8 +3072,8 @@ uint32_t dc_link_bandwidth_kbps(
  * but the difference is minimal and is in a safe direction,
  * which all works well around potential ambiguity of DP 1.4a 
spec.
  */
-   long long fec_link_bw_kbps = link_bw_kbps * 970LL;
-   link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL);
+   link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
+  link_bw_kbps, 32);
 }
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index b35327bafbc5..70ac8a95d2db 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2657,7 +2657,7 @@ static void update_bounding_box(struct dc *dc, struct 
_vcs_dpi_soc_bounding_box_
 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 
1000;

 // FCLK:UCLK ratio is 1.08
-   min_fclk_required_by_uclk = ((unsigned long 
long)uclk_states[i]) * 1080 / 100;
+   min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 
/ 100, uclk_states[i], 32);

 calculated_states[i].fabricclk_mhz = 
(min_fclk_required_by_uclk < min_dcfclk) ?
 min_dcfclk : min_fclk_required_by_uclk;
--
2.20.0

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Re: [PATCH][next] drm/amdgpu/mes10.1: fix duplicated assignment to adev->mes.ucode_fw_version

2019-06-28 Thread Abramov, Slava 
Acked-by: Slava Abramov 


From: amd-gfx  on behalf of Colin King 

Sent: Friday, June 28, 2019 11:05:39 AM
To: Deucher, Alexander; Koenig, Christian; Zhou, David(ChunMing); David Airlie; 
Daniel Vetter; Xiao, Jack; Zhang, Hawking; amd-gfx@lists.freedesktop.org; 
dri-de...@lists.freedesktop.org
Cc: kernel-janit...@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: [PATCH][next] drm/amdgpu/mes10.1: fix duplicated assignment to 
adev->mes.ucode_fw_version

From: Colin Ian King 

Currently adev->mes.ucode_fw_version is being assigned twice with
different values. This looks like a cut-n-paste error and instead
the second assignment should be adev->mes.data_fw_version. Fix
this.

Addresses-Coverity: ("Unused value")
Fixes: 298d05460cc4 ("drm/amdgpu/mes10.1: load mes firmware file to CPU buffer")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 
b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 29fab7984855..2a27f0b30bb5 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -91,7 +91,7 @@ static int mes_v10_1_init_microcode(struct amdgpu_device 
*adev)

 mes_hdr = (const struct mes_firmware_header_v1_0 *)adev->mes.fw->data;
 adev->mes.ucode_fw_version = le32_to_cpu(mes_hdr->mes_ucode_version);
-   adev->mes.ucode_fw_version =
+   adev->mes.data_fw_version =
 le32_to_cpu(mes_hdr->mes_ucode_data_version);
 adev->mes.uc_start_addr =
 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) |
--
2.20.1

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Re: [PATCH][next] drm/amd/powerplay: fix out of memory check on od8_settings

2019-06-28 Thread Abramov, Slava 
Acked-by: Slava Abramov 


From: amd-gfx  on behalf of Colin King 

Sent: Friday, June 28, 2019 11:13:54 AM
To: Wang, Kevin(Yang); Rex Zhu; Quan, Evan; Deucher, Alexander; Koenig, 
Christian; Zhou, David(ChunMing); David Airlie; Daniel Vetter; 
amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: kernel-janit...@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: [PATCH][next] drm/amd/powerplay: fix out of memory check on 
od8_settings

From: Colin Ian King 

The null pointer check on od8_settings is currently the opposite of what
it is intended to do. Fix this by adding in the missing ! operator.

Addressed-Coverity: ("Resource leak")
Fixes: 0c83d32c565c ("drm/amd/powerplay: simplified od_settings for each asic")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c 
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 0f14fe14ecd8..eb9e6b3a5265 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1501,8 +1501,7 @@ static int vega20_set_default_od8_setttings(struct 
smu_context *smu)
 return -EINVAL;

 od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
-
-   if (od8_settings)
+   if (!od8_settings)
 return -ENOMEM;

 smu->od_settings = (void *)od8_settings;
--
2.20.1

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Re: [PATCH] drm/amd/powerplay: fix incorrect assignments to mclk_mask and soc_mask

2019-06-28 Thread Abramov, Slava 
Acked-by: Slava Abramov 


From: amd-gfx  on behalf of Colin King 

Sent: Friday, June 28, 2019 10:45:17 AM
To: Wang, Kevin(Yang); Rex Zhu; Quan, Evan; Deucher, Alexander; Koenig, 
Christian; Zhou, David(ChunMing); David Airlie; Daniel Vetter; 
amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: kernel-janit...@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: [PATCH] drm/amd/powerplay: fix incorrect assignments to mclk_mask and 
soc_mask

From: Colin Ian King 

There are null pointer checks on mlck_mask and soc_mask however the
sclk_mask is being used in assignments in what looks to be a cut-n-paste
coding error. Fix this by using the correct pointers in the assignments.

Addresses-Coverity: ("Dereference after null check")
Fixes: 2d9fb9b06643 ("drm/amd/powerplay: add function get_profiling_clk_mask 
for navi10")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 27e5c80..ac151da 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1134,14 +1134,14 @@ static int navi10_get_profiling_clk_mask(struct 
smu_context *smu,
 ret = smu_get_dpm_level_count(smu, SMU_MCLK, 
_count);
 if (ret)
 return ret;
-   *sclk_mask = level_count - 1;
+   *mclk_mask = level_count - 1;
 }

 if(soc_mask) {
 ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, 
_count);
 if (ret)
 return ret;
-   *sclk_mask = level_count - 1;
+   *soc_mask = level_count - 1;
 }
 }

--
2.7.4

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Re: [PATCH] drm/amd/powerplay: fix off-by-one array bounds check

2019-06-28 Thread Abramov, Slava 
Acked-by: Slava Abramov 


From: amd-gfx  on behalf of Colin King 

Sent: Friday, June 28, 2019 10:24:02 AM
To: Rex Zhu; Quan, Evan; Deucher, Alexander; Koenig, Christian; Zhou, 
David(ChunMing); David Airlie; Daniel Vetter; amd-gfx@lists.freedesktop.org; 
dri-de...@lists.freedesktop.org
Cc: kernel-janit...@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: [PATCH] drm/amd/powerplay: fix off-by-one array bounds check

From: Colin Ian King 

The array bounds check for index is currently off-by-one and should
be using >= rather than > on the upper bound. Fix this.

Addresses-Coverity: ("Out-of-bounds read")
Fixes: b3490673f905 ("drm/amd/powerplay: introduce the navi10 pptable 
implementation")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 27e5c80..f678700 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -210,7 +210,7 @@ static int navi10_workload_map[] = {
 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 {
 int val;
-   if (index > SMU_MSG_MAX_COUNT)
+   if (index >= SMU_MSG_MAX_COUNT)
 return -EINVAL;

 val = navi10_message_map[index];
--
2.7.4

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Re: [PATCH][next] drm/amdkfd: fix a missing break in a switch statement

2019-06-28 Thread Abramov, Slava 
Acked-by: Slava Abramov 


From: amd-gfx  on behalf of Colin King 

Sent: Friday, June 28, 2019 10:54:43 AM
To: Cox, Philip; Oded Gabbay; Deucher, Alexander; Koenig, Christian; Zhou, 
David(ChunMing); David Airlie; Daniel Vetter; dri-de...@lists.freedesktop.org; 
amd-gfx@lists.freedesktop.org
Cc: kernel-janit...@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: [PATCH][next] drm/amdkfd: fix a missing break in a switch statement

From: Colin Ian King 

Currently for the CHIP_RAVEN case there is a missing break
causing the code to fall through to the new CHIP_NAVI10 case.
Fix this by adding in the missing break statement.

Fixes: 14328aa58ce5 ("drm/amdkfd: Add navi10 support to amdkfd. (v3)")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 792371442195..4e3fc284f6ac 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -668,6 +668,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
 case CHIP_RAVEN:
 pcache_info = raven_cache_info;
 num_of_cache_types = ARRAY_SIZE(raven_cache_info);
+   break;
 case CHIP_NAVI10:
 pcache_info = navi10_cache_info;
 num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
--
2.20.1

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Re: [PATCH][next] drm/amdgpu: fix off-by-one comparison on a WARN_ON message

2019-06-28 Thread Abramov, Slava 
Acked-by: Slava Abramov 


From: amd-gfx  on behalf of Colin King 

Sent: Friday, June 28, 2019 10:08:01 AM
To: Zhang, Hawking; Deucher, Alexander; Koenig, Christian; Zhou, 
David(ChunMing); David Airlie; Daniel Vetter; amd-gfx@lists.freedesktop.org; 
dri-de...@lists.freedesktop.org
Cc: kernel-janit...@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: [PATCH][next] drm/amdgpu: fix off-by-one comparison on a WARN_ON 
message

From: Colin Ian King 

The WARN_ON is currently throwing a warning when i is 65 or higher which
is off by one. It should be 64 or higher (64 queues from 0..63 inclusive),
so fix this off-by-one comparison.

Fixes: 849aca9f9c03 ("drm/amdgpu: Move common code to amdgpu_gfx.c")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 74066e1466f7..c8d106c59e27 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -501,7 +501,7 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
 /* This situation may be hit in the future if a new HW
  * generation exposes more than 64 queues. If so, the
  * definition of queue_mask needs updating */
-   if (WARN_ON(i > (sizeof(queue_mask)*8))) {
+   if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
 break;
 }
--
2.20.1

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Re: [PATCH] drm/amdgpu: fix a missing break in a switch statement

2019-06-28 Thread Abramov, Slava 
Acked-by: Slava Abramov 


From: amd-gfx  on behalf of Colin King 

Sent: Friday, June 28, 2019 10:33:20 AM
To: Zhang, Hawking; Deucher, Alexander; Koenig, Christian; Zhou, 
David(ChunMing); David Airlie; Daniel Vetter; amd-gfx@lists.freedesktop.org; 
dri-de...@lists.freedesktop.org
Cc: kernel-janit...@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: [PATCH] drm/amdgpu: fix a missing break in a switch statement

From: Colin Ian King 

Currently for the AMDGPU_IRQ_STATE_DISABLE there is a missing break
causing the code to fall through to the AMDGPU_IRQ_STATE_ENABLE case.
Fix this by adding in the missing break statement.

Addresses-Coverity: ("Missing break in switch")
Fixes: a644d85a5cd4 ("drm/amdgpu: add gfx v10 implementation (v10)")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 2932ade7dbd0..c165200361b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4608,6 +4608,7 @@ gfx_v10_0_set_gfx_eop_interrupt_state(struct 
amdgpu_device *adev,
 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
 TIME_STAMP_INT_ENABLE, 0);
 WREG32(cp_int_cntl_reg, cp_int_cntl);
+   break;
 case AMDGPU_IRQ_STATE_ENABLE:
 cp_int_cntl = RREG32(cp_int_cntl_reg);
 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
--
2.20.1

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Re: [PATCH] drm/amd/powerplay: use hardware fan control if no powerplay fan table

2019-06-28 Thread Abramov, Slava 
Tested-by: Slava Abramov 

Acked-by: Slava Abramov 


From: amd-gfx  on behalf of Evan Quan 

Sent: Thursday, June 27, 2019 11:15:29 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amd/powerplay: use hardware fan control if no powerplay 
fan table

Use SMC default fan table if no external powerplay fan table.

Change-Id: Icd7467a7fc5287a92945ba0fcc19699192b1683a
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c | 4 +++-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h   | 1 +
 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 4 
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
index ae64ff7153d6..1cd5a8b5cdc1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
@@ -916,8 +916,10 @@ static int init_thermal_controller(
 PHM_PlatformCaps_ThermalController
   );

-   if (0 == powerplay_table->usFanTableOffset)
+   if (0 == powerplay_table->usFanTableOffset) {
+   hwmgr->thermal_controller.use_hw_fan_control = 1;
 return 0;
+   }

 fan_table = (const PPTable_Generic_SubTable_Header *)
 (((unsigned long)powerplay_table) +
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 2f186fcbdfc5..ec53bf24396e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -697,6 +697,7 @@ struct pp_thermal_controller_info {
 uint8_t ucType;
 uint8_t ucI2cLine;
 uint8_t ucI2cAddress;
+   uint8_t use_hw_fan_control;
 struct pp_fan_info fanInfo;
 struct pp_advance_fan_control_parameters advanceFanControlParameters;
 };
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index fbac2d3326b5..a1a9f6196009 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -2092,6 +2092,10 @@ static int polaris10_thermal_setup_fan_table(struct 
pp_hwmgr *hwmgr)
 return 0;
 }

+   /* use hardware fan control */
+   if (hwmgr->thermal_controller.use_hw_fan_control)
+   return 0;
+
 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
 usPWMMin * duty100;
 do_div(tmp64, 1);
--
2.21.0

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Re: [PATCH] drm/amd/doc: add rough outline of tracepoint documentation

2019-05-30 Thread Abramov, Slava 
Comments inline (marked with [slava a]).


General comment - word capitalisation in the lists is inconsistent



From: amd-gfx  on behalf of StDenis, Tom 

Sent: Thursday, May 30, 2019 10:56 AM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: [PATCH] drm/amd/doc: add rough outline of tracepoint documentation

Signed-off-by: Tom St Denis 
---
 Documentation/gpu/amdgpu.rst  |  10 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 221 ++
 2 files changed, 231 insertions(+)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 86138798128f..3564765110e5 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -89,6 +89,16 @@ AMDGPU RAS debugfs control interface
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
:internal:

+AMDGPU Tracing Support
+==
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+   :doc: AMDGPU Tracing Support
+
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+   :internal:
+

 GPU Power/Thermal Controls and Monitoring
 =
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index d3ca2424b5fe..71febb90d3e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -37,6 +37,227 @@
 #define AMDGPU_JOB_GET_TIMELINE_NAME(job) \
  
job->base.s_fence->finished.ops->get_timeline_name(>base.s_fence->finished)

+/**
+ * DOC: AMDGPU Tracing Support
+ *
+ * The AMDGPU driver provides numerous trace points that can aid
+ * in debugging.  They are globally enabled by the file:
+ *
+ * /sys/kernel/debug/tracing/events/amdgpu/enable
+ *
+ * or individually by the enable files in the sub-directories
+ * of that directory.
+ *
+ * amdgpu_mm_rreg, amdgpu_mm_wreg
+ * --
+ *
+ * These trace points track reads and writes to MMIO registers by
+ * the kernel driver (activity inside ring/indirect buffers are not
+ * traced) which can be used to diagnose IP block activity and
+ * responses.

[slava a] Either 'activities are not traced' or 'activity is not traced'
[slava a] Double usage of word 'activity' sounds weird.

[snap]
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Re: [PATCH 1/2] drm/amd/doc: Add XGMI sysfs documentation

2019-05-24 Thread Abramov, Slava 
Acked-by: Slava Abramov 


From: amd-gfx  on behalf of StDenis, Tom 

Sent: Friday, May 24, 2019 9:23:49 AM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: [PATCH 1/2] drm/amd/doc: Add XGMI sysfs documentation

[CAUTION: External Email]

Signed-off-by: Tom St Denis 
---
 Documentation/gpu/amdgpu.rst |  9 
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 28 
 2 files changed, 37 insertions(+)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index a740e491dfcc..cacfcfad2356 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -70,6 +70,15 @@ Interrupt Handling
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
:internal:

+AMDGPU XGMI Support
+===
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+   :doc: AMDGPU XGMI Support
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+   :internal:
+
 GPU Power/Thermal Controls and Monitoring
 =

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index e48e9394f1e4..d11eba09eadd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -40,6 +40,34 @@ void *amdgpu_xgmi_hive_try_lock(struct amdgpu_hive_info 
*hive)
return >device_list;
 }

+/**
+ * DOC: AMDGPU XGMI Support
+ *
+ * XGMI is a high speed interconnect that joins multiple GPU cards
+ * into a homogeneous memory space that is organized by a collective
+ * hive ID and individual node IDs, both of which are 64-bit numbers.
+ *
+ * The file xgmi_device_id contains the unique per GPU device ID and
+ * is stored in the /sys/class/drm/card${cardno}/device/ directory.
+ *
+ * Inside the device directory a sub-directory 'xgmi_hive_info' is
+ * created which contains the hive ID and the list of nodes.
+ *
+ * The hive ID is stored in:
+ *   /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id
+ *
+ * The node information is stored in numbered directories:
+ *   
/sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id
+ *
+ * Each device has their own xgmi_hive_info direction with a mirror
+ * set of node sub-directories.
+ *
+ * The XGMI memory space is built by contiguously adding the power of
+ * two padded VRAM space from each node to each other.
+ *
+ */
+
+
 static ssize_t amdgpu_xgmi_show_hive_id(struct device *dev,
struct device_attribute *attr, char *buf)
 {
--
2.21.0

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Re: [PATCH 2/2] drm/amd/doc: Add RAS documentation to guide

2019-05-24 Thread Abramov, Slava 
Acked-by: Slava Abramov 


From: amd-gfx  on behalf of StDenis, Tom 

Sent: Friday, May 24, 2019 9:23:50 AM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: [PATCH 2/2] drm/amd/doc: Add RAS documentation to guide

[CAUTION: External Email]

Signed-off-by: Tom St Denis 
---
 Documentation/gpu/amdgpu.rst| 11 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c |  4 ++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index cacfcfad2356..86138798128f 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -79,6 +79,17 @@ AMDGPU XGMI Support
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
:internal:

+AMDGPU RAS debugfs control interface
+
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+   :doc: AMDGPU RAS debugfs control interface
+
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+   :internal:
+
+
 GPU Power/Thermal Controls and Monitoring
 =

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index d5719b0fb82c..7c8a4aedf07c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -244,8 +244,8 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file 
*f,

return 0;
 }
-/*
- * DOC: ras debugfs control interface
+/**
+ * DOC: AMDGPU RAS debugfs control interface
  *
  * It accepts struct ras_debug_if who has two members.
  *
--
2.21.0

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[PATCH] drm/amdgpu: use div64_ul for 32-bit compatibility v1

2019-05-17 Thread Abramov, Slava 
v1: replace casting to unsigned long with div64_ul

Change-Id: Ia48671ed0756bb73c7b4760a800bcb6f600cbef2
Signed-off-by: Slava Abramov 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index da1dc40b9b14..d5719b0fb82c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -764,8 +764,8 @@ static ssize_t amdgpu_ras_sysfs_badpages_read(struct file 
*f,
  struct amdgpu_device *adev = con->adev;
  const unsigned int element_size =
  sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
- unsigned int start = (ppos + element_size - 1) / element_size;
- unsigned int end = (ppos + count - 1) / element_size;
+ unsigned int start = div64_ul(ppos + element_size - 1, element_size);
+ unsigned int end = div64_ul(ppos + count - 1, element_size);
  ssize_t s = 0;
  struct ras_badpage *bps = NULL;
  unsigned int bps_count = 0;
--
2.17.1


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[PATCH] drm/amdgpu: cast to unsigned int for 32-bit portability

2019-05-16 Thread Abramov, Slava 
Without casting, 64-bit division is used implicitly causing DEPMOD
failure when building 32-bit kernel.

Signed-off-by: Slava Abramov 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index da1dc40b9b14..0499620ec972 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -764,8 +764,9 @@ static ssize_t amdgpu_ras_sysfs_badpages_read(struct file 
*f,
  struct amdgpu_device *adev = con->adev;
  const unsigned int element_size =
  sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
- unsigned int start = (ppos + element_size - 1) / element_size;
- unsigned int end = (ppos + count - 1) / element_size;
+ unsigned int start =
+ (unsigned int) (ppos + element_size - 1) / element_size;
+ unsigned int end = (unsigned int) (ppos + count - 1) / element_size;
  ssize_t s = 0;
  struct ras_badpage *bps = NULL;
  unsigned int bps_count = 0;
--
2.17.1


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Re: Same bridge number?

2018-11-07 Thread Abramov, Slava 
1-877-336-1283 8051546


From: amd-gfx  on behalf of Panariti, 
David 
Sent: Wednesday, November 7, 2018 9:59:42 AM
To: amd-gfx@lists.freedesktop.org
Subject: Same bridge number?



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Re: [PATCH xf86-video-amdgpu] Use strcpy for RandR output property names

2018-07-23 Thread Abramov, Slava 
Reviewed-by: Slava Abramov 


From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Monday, July 23, 2018 12:45:11 PM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH xf86-video-amdgpu] Use strcpy for RandR output property names

From: Michel Dänzer 

Instead of strncpy with the string length. Avoids new warnings with GCC
8:

../../src/drmmode_display.c: In function ‘drmmode_output_create_resources’:
../../src/drmmode_display.c:2240:2: warning: ‘strncpy’ output truncated before 
terminating nul copying 8 bytes from a string of the same length 
[-Wstringop-truncation]
  strncpy(tearfree_prop->name, "TearFree", 8);
  ^~~
../../src/drmmode_display.c:2244:2: warning: ‘strncpy’ output truncated before 
terminating nul copying 3 bytes from a string of the same length 
[-Wstringop-truncation]
  strncpy(tearfree_prop->enums[0].name, "off", 3);
  ^~~
../../src/drmmode_display.c:2245:2: warning: ‘strncpy’ output truncated before 
terminating nul copying 2 bytes from a string of the same length 
[-Wstringop-truncation]
  strncpy(tearfree_prop->enums[1].name, "on", 2);
  ^~
../../src/drmmode_display.c:2247:2: warning: ‘strncpy’ output truncated before 
terminating nul copying 4 bytes from a string of the same length 
[-Wstringop-truncation]
  strncpy(tearfree_prop->enums[2].name, "auto", 4);
  ^~~~

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index b3e754005..92f58c157 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -2211,14 +2211,14 @@ static void 
drmmode_output_create_resources(xf86OutputPtr output)
 /* Userspace-only property for TearFree */
 tearfree_prop = calloc(1, sizeof(*tearfree_prop));
 tearfree_prop->flags = DRM_MODE_PROP_ENUM;
-   strncpy(tearfree_prop->name, "TearFree", 8);
+   strcpy(tearfree_prop->name, "TearFree");
 tearfree_prop->count_enums = 3;
 tearfree_prop->enums = calloc(tearfree_prop->count_enums,
   sizeof(*tearfree_prop->enums));
-   strncpy(tearfree_prop->enums[0].name, "off", 3);
-   strncpy(tearfree_prop->enums[1].name, "on", 2);
+   strcpy(tearfree_prop->enums[0].name, "off");
+   strcpy(tearfree_prop->enums[1].name, "on");
 tearfree_prop->enums[1].value = 1;
-   strncpy(tearfree_prop->enums[2].name, "auto", 4);
+   strcpy(tearfree_prop->enums[2].name, "auto");
 tearfree_prop->enums[2].value = 2;
 drmmode_output->props[j].mode_prop = tearfree_prop;
 drmmode_output->props[j].value = info->tear_free;
--
2.18.0

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Re: [PATCH xf86-video-amdgpu 1/2] Remove #if 0'd code

2018-06-28 Thread Abramov, Slava 
Michel,

My review is only for the first patch.


Slava

From: Michel Dänzer 
Sent: Thursday, June 28, 2018 4:26:28 AM
To: Abramov, Slava
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH xf86-video-amdgpu 1/2] Remove #if 0'd code

On 2018-06-27 08:29 PM, Abramov, Slava wrote:
> I wonder how '#if 0' made its way upstream, but besides this

It was inherited from xf86-video-ati, where it's been in
drmmode_display.c since that file was first added (in 2009).


> Reviewed-by: Slava Abramov 

Thanks Slava (and Alex)! Is that only for this patch, or also for patch
2 of the series?


--
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: [PATCH xf86-video-amdgpu 1/2] Remove #if 0'd code

2018-06-27 Thread Abramov, Slava 
I wonder how '#if 0' made its way upstream, but besides this


Reviewed-by: Slava Abramov 


From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Wednesday, June 27, 2018 12:39:40 PM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH xf86-video-amdgpu 1/2] Remove #if 0'd code

From: Michel Dänzer 

This has always been disabled, no need to keep it.

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c | 12 
 1 file changed, 12 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 1563417a7..5fe49b607 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -2459,15 +2459,6 @@ static const xf86OutputFuncsRec drmmode_output_funcs = {
 .create_resources = drmmode_output_create_resources,
 .set_property = drmmode_output_set_property,
 .get_property = drmmode_output_get_property,
-#if 0
-
-   .save = drmmode_crt_save,
-   .restore = drmmode_crt_restore,
-   .mode_fixup = drmmode_crt_mode_fixup,
-   .prepare = drmmode_output_prepare,
-   .mode_set = drmmode_crt_mode_set,
-   .commit = drmmode_output_commit,
-#endif
 .detect = drmmode_output_detect,
 .mode_valid = drmmode_output_mode_valid,

@@ -3470,9 +3461,6 @@ Bool drmmode_setup_colormap(ScreenPtr pScreen, 
ScrnInfoPtr pScrn)
 !xf86HandleColormaps(pScreen, 256, 10,
  NULL, NULL,
  CMAP_PALETTED_TRUECOLOR
-#if 0  /* This option messes up text mode! 
(e...@suse.de) */
-| CMAP_LOAD_EVEN_IF_OFFSCREEN
-#endif
  | CMAP_RELOAD_ON_MODE_SWITCH))
 return FALSE;
 }
--
2.18.0

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Re: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs (v2)

2018-06-20 Thread Abramov, Slava 
Acked-by: Slava Abramov 


From: amd-gfx  on behalf of Tom St Denis 

Sent: Wednesday, June 20, 2018 12:48:52 PM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs (v2)

This adds what should be a stable interface to read GPU
load from userspace.

(v2): Fix comments and name of file per recommendations.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 47 ++
 1 file changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 113edffb5960..49138ac2be24 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -918,6 +918,43 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct 
device *dev,
 return -EINVAL;
 }

+/**
+ * DOC: busy_percent
+ *
+ * The firmware computes a percentage of load based on the activity
+ * level in the IP cores.
+ */
+static ssize_t amdgpu_get_busy_percent(struct device *dev,
+   struct device_attribute *attr,
+   char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+   int r, value, size = sizeof(value);
+
+   /* sanity check PP is enabled */
+   if (!(adev->powerplay.pp_funcs &&
+ adev->powerplay.pp_funcs->read_sensor))
+   return -EINVAL;
+
+   /* read the IP busy sensor */
+   r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
+  (void *), );
+   if (r)
+   return r;
+
+   return snprintf(buf, PAGE_SIZE, "%d\n", value);
+}
+
+static ssize_t amdgpu_set_busy_percent(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf,
+   size_t count)
+{
+   return -EINVAL;
+}
+
+
 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, 
amdgpu_set_dpm_state);
 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
amdgpu_get_dpm_forced_performance_level,
@@ -951,6 +988,8 @@ static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
 amdgpu_get_pp_od_clk_voltage,
 amdgpu_set_pp_od_clk_voltage);
+static DEVICE_ATTR(gpu_busy_percent, S_IRUGO | S_IWUSR,
+   amdgpu_get_busy_percent, amdgpu_set_busy_percent);

 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
   struct device_attribute *attr,
@@ -1854,6 +1893,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 "pp_od_clk_voltage\n");
 return ret;
 }
+   ret = device_create_file(adev->dev,
+   _attr_gpu_busy_percent);
+   if (ret) {
+   DRM_ERROR("failed to create device file "
+   "gpu_busy_level\n");
+   return ret;
+   }
 ret = amdgpu_debugfs_pm_init(adev);
 if (ret) {
 DRM_ERROR("Failed to register debugfs file for dpm!\n");
@@ -1889,6 +1935,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 _attr_pp_power_profile_mode);
 device_remove_file(adev->dev,
 _attr_pp_od_clk_voltage);
+   device_remove_file(adev->dev, _attr_gpu_busy_percent);
 }

 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
--
2.14.4

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Re: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs

2018-06-20 Thread Abramov, Slava 
Should the comment then say 'get the load' instead of 'get the temperature'?


From: StDenis, Tom
Sent: Wednesday, June 20, 2018 10:39:25 AM
To: Abramov, Slava; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs



On 06/20/2018 10:37 AM, Abramov, Slava wrote:
> I see some functions in amdgpu_pm.c have function level documentation,
> so that it would be good to have this for newly added functions.

Sure I can add some comments/docs.

> Another comment is inline.
>
>
>>From: amd-gfx  on behalf of Tom St 
>>Denis 
>
>  >Sent: Wednesday, June 20, 2018 8:31 AM
>  >To: amd-gfx@lists.freedesktop.org
>  >Cc: StDenis, Tom
>  >Subject: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs
>  >
>  >This adds what should be a stable interface to read GPU
>  >load from userspace.
>  >
>  >Signed-off-by: Tom St Denis 
>  >---
>  > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 41
> ++
>  > 1 file changed, 41 insertions(+)
>  >
>  >diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>  >index 113edffb5960..d57b414ac228 100644
>  >--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>  >+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>  >@@ -918,6 +918,37 @@ static ssize_t
> amdgpu_set_pp_power_profile_mode(struct device *dev,
>  > return -EINVAL;
>  > }
>  >
>  >+static ssize_t amdgpu_get_busy_level(struct device *dev,
>  >+   struct device_attribute *attr,
>  >+   char *buf)
>  >+{
>  >+   struct drm_device *ddev = dev_get_drvdata(dev);
>  >+   struct amdgpu_device *adev = ddev->dev_private;
>  >+   int r, value, size = sizeof(value);
>  >+
>  >+   /* sanity check PP is enabled */
>  >+   if (!(adev->powerplay.pp_funcs &&
>  >+ adev->powerplay.pp_funcs->read_sensor))
>  >+   return -EINVAL;
>  >+
>  >+   /* get the temperature */
>
> Is load is the same thing as temperature?


Nope, there is a separate sensor for that but it is included in hwmon
and Alex would rather not duplicate it.

GPU_LOAD is a value returned by firmware based on the RLC busy status (I
think...).

Tom
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Re: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs

2018-06-20 Thread Abramov, Slava 
I see some functions in amdgpu_pm.c have function level documentation, so that 
it would be good to have this for newly added functions.


Another comment is inline.


>From: amd-gfx  on behalf of Tom St 
>Denis 

>Sent: Wednesday, June 20, 2018 8:31 AM
>To: amd-gfx@lists.freedesktop.org
>Cc: StDenis, Tom
>Subject: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs
>
>This adds what should be a stable interface to read GPU
>load from userspace.
>
>Signed-off-by: Tom St Denis 
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 41 ++
> 1 file changed, 41 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>index 113edffb5960..d57b414ac228 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>@@ -918,6 +918,37 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct 
>device *dev,
> return -EINVAL;
> }
>
>+static ssize_t amdgpu_get_busy_level(struct device *dev,
>+   struct device_attribute *attr,
>+   char *buf)
>+{
>+   struct drm_device *ddev = dev_get_drvdata(dev);
>+   struct amdgpu_device *adev = ddev->dev_private;
>+   int r, value, size = sizeof(value);
>+
>+   /* sanity check PP is enabled */
>+   if (!(adev->powerplay.pp_funcs &&
>+ adev->powerplay.pp_funcs->read_sensor))
>+   return -EINVAL;
>+
>+   /* get the temperature */

Is load is the same thing as temperature?

[snap]


Slava A
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Re: GPU hang trying to run OpenCL kernels on x86_64

2018-05-04 Thread Abramov, Slava 
Luis,


Can you please provide more details on your system environment and steps on 
configuring the software and reproducing the issue?



Slava A


From: amd-gfx  on behalf of Luís Mendes 

Sent: Friday, May 4, 2018 12:27:47 PM
To: amd-gfx list; Koenig, Christian; Michel Dänzer
Subject: GPU hang trying to run OpenCL kernels on x86_64

Hi,

I am a collaborator with Syncleus/aparapi project on github and I've
been testing OpenCL on AMD and NVIDIA cards.

Currently I have a set of kernels that hang the GPU (AMD RX 460 and
AMD RX 550) across all compute units on x86_64 running vanilla kernel
4.16.7 on Ubuntu 18.04, also on Ubuntu 16.04.4 with AMDGPU PRO 17.50
and 18.10 show the same problems, in fact, AMDGPU-PRO 18.10 is even
worse.

However the same set of kernels run happily on armhf with vanilla
Linux 4.16.7 and mesa 18.0 (mesa-opencl-icd and libclc for amdgcn),
Ubuntu 17.10, on an AMD RX460 and an AMD RX 550.

Luís Mendes
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Re: [PATCH xf86-video-amdgpu 04/10] Create drmmode_crtc_wait_pending_event helper macro

2017-08-22 Thread Abramov, Slava 

From: Michel Dänzer <mic...@daenzer.net>
Sent: Tuesday, August 22, 2017 1:52 AM
To: Abramov, Slava
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH xf86-video-amdgpu 04/10] Create 
drmmode_crtc_wait_pending_event helper macro

On 18/08/17 11:51 PM, Abramov, Slava wrote:
> *From:* amd-gfx <amd-gfx-boun...@lists.freedesktop.org> on behalf of
>
>> diff --git a/src/drmmode_display.c b/src/drmmode_display.c
>> index 1a805b82d..bdd3866b8 100644
>> --- a/src/drmmode_display.c
>> +++ b/src/drmmode_display.c
>> @@ -96,6 +96,14 @@ AMDGPUZaphodStringMatches(ScrnInfoPtr pScrn, const
>> char *s, char *output_name)
>>  return FALSE;
>>  }
>>
>> +
>> +/* Wait for the boolean condition to be FALSE */
>> +#define drmmode_crtc_wait_pending_event(drmmode_crtc, fd, condition) \
>> +   do {} while ((condition) && \
>> +drmHandleEvent(fd,
>> _crtc->drmmode->event_context) \
>> +> 0);
>> +
>> +
>
> [slava] The comment seems a little misleading to me.  The loop condition
> has actually two parts, and it's unclear what we're actually waiting
> for.  A side question: is it expected that the variable 'condition' will
> change while we're waiting?

Yes, that's the whole point. :) While (condition) evaluates to non-0, we
call drmHandleEvent(), which blocks until at least one DRM event
arrives, and triggers processing of arrived DRM events.

Maybe something like this would be better?

/* If condition evaluates to TRUE, process DRM events until condition
 * evaluates to FALSE.
 */

[slava] Yes, I like that :)


Anyway, this patch just ports the same change from xf86-video-ati, so
I'm not going to modify the comment in this patch. Do you want to send a
patch modifying the comment in either driver?

[slava] I will try to do this, as a military exercise, to get use to the 
process 


Slava
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