[PATCH] drm/amdgpu: Use signed arithmetic for overdrive clock calculations
Signed-off-by: Donny Yang <w...@kota.moe>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 70 +++-
1 file changed, 21 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index a74f60a5..f6c01e19 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3349,7 +3349,8 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
struct smu7_dpm_table *dpm_table = >dpm_table;
struct smu7_dpm_table *golden_dpm_table = >golden_dpm_table;
- uint32_t dpm_count, clock_percent;
+ uint32_t dpm_count;
+ int32_t clock_percent;
uint32_t i;
if (0 == data->need_update_smu7_dpm_table)
@@ -3371,32 +3372,16 @@ static int
smu7_populate_and_upload_sclk_mclk_dpm_levels(
return -EINVAL);
dpm_count = dpm_table->sclk_table.count < 2 ? 0 :
dpm_table->sclk_table.count - 2;
+ clock_percent =
+ ((sclk
+ -
golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
+ ) * 100)
+ /
golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
for (i = dpm_count; i > 1; i--) {
- if (sclk >
golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value)
{
- clock_percent =
- ((sclk
- -
golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
- ) * 100)
- /
golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-
-
dpm_table->sclk_table.dpm_levels[i].value =
-
golden_dpm_table->sclk_table.dpm_levels[i].value +
-
(golden_dpm_table->sclk_table.dpm_levels[i].value *
-
clock_percent)/100;
-
- } else if
(golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value >
sclk) {
- clock_percent =
-
((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count -
1].value
- - sclk) * 100)
- /
golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-
-
dpm_table->sclk_table.dpm_levels[i].value =
-
golden_dpm_table->sclk_table.dpm_levels[i].value -
-
(golden_dpm_table->sclk_table.dpm_levels[i].value *
-
clock_percent) / 100;
- } else
-
dpm_table->sclk_table.dpm_levels[i].value =
-
golden_dpm_table->sclk_table.dpm_levels[i].value;
+ dpm_table->sclk_table.dpm_levels[i].value =
+
golden_dpm_table->sclk_table.dpm_levels[i].value +
+
(golden_dpm_table->sclk_table.dpm_levels[i].value *
+ clock_percent)
/ 100;
}
}
}
@@ -3414,30 +3399,17 @@ static int
smu7_populate_and_upload_sclk_mclk_dpm_levels(
"Divide by 0!",
return -EINVAL);
dpm_count = dpm_table->mclk_table.count < 2 ? 0 :
dpm_table->mclk_table.count - 2;
+
+ clock_percent =
+ ((mclk
+ -
golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value
+ ) * 100)
+ /
golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
for (i = dpm_count; i > 1; i--) {
- if
(golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_
[PATCH 0/2] Report VDDC and MVDD over pp_dpm{sclk,mclk}
Tested on a RX480.
I'm not sure whether to report VDDCI or MVDD for memory. MVDD felt "more"
correct, so that's what I've done.
Donny Yang (2):
drm/amdgpu: Populate DPMv1 voltage tables
drm/amdgpu: Report VDDC and MVDD over pp_dpm{sclk,mclk}
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 54 +---
1 file changed, 39 insertions(+), 15 deletions(-)
--
2.11.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amdgpu: Report VDDC and MVDD over pp_dpm{sclk,mclk}
Signed-off-by: Donny Yang <w...@kota.moe> --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 103e1330..4dd27c28 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -4065,6 +4065,8 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); + struct smu7_single_dpm_table *vddc_table = &(data->dpm_table.vddc_table); + struct smu7_single_dpm_table *mvdd_table = &(data->dpm_table.mvdd_table); int i, now, size = 0; uint32_t clock, pcie_speed; @@ -4081,8 +4083,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, now = i; for (i = 0; i < sclk_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", + size += sprintf(buf + size, "%d: %uMhz %umV %s\n", i, sclk_table->dpm_levels[i].value / 100, + vddc_table->dpm_levels[i].value, (i == now) ? "*" : ""); break; case PP_MCLK: @@ -4097,8 +4100,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, now = i; for (i = 0; i < mclk_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", + size += sprintf(buf + size, "%d: %uMhz %umV %s\n", i, mclk_table->dpm_levels[i].value / 100, + mvdd_table->dpm_levels[i].value, (i == now) ? "*" : ""); break; case PP_PCIE: -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amdgpu: Populate DPMv1 voltage tables
Signed-off-by: Donny Yang <w...@kota.moe>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 46 +---
1 file changed, 33 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index f6c01e19..103e1330 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -705,7 +705,7 @@ static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
/* Initialize Vddc DPM table based on allow Vddc values. And populate
corresponding std values. */
for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
- data->dpm_table.vddc_table.dpm_levels[i].value =
allowed_vdd_mclk_table->entries[i].v;
+ data->dpm_table.vddc_table.dpm_levels[i].value =
allowed_vdd_sclk_table->entries[i].v;
data->dpm_table.vddc_table.dpm_levels[i].param1 =
std_voltage_table->entries[i].Leakage;
/* param1 is for corresponding std voltage */
data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
@@ -749,12 +749,19 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr
*hwmgr)
struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
+ struct smu7_single_dpm_table *sclk_table, *mclk_table,
+ *vddc_table, *mvdd_table, *vddci_table;
if (table_info == NULL)
return -EINVAL;
dep_sclk_table = table_info->vdd_dep_on_sclk;
dep_mclk_table = table_info->vdd_dep_on_mclk;
+ sclk_table = >dpm_table.sclk_table;
+ mclk_table = >dpm_table.mclk_table;
+ vddc_table = >dpm_table.vddc_table;
+ mvdd_table = >dpm_table.mvdd_table;
+ vddci_table = >dpm_table.vddci_table;
PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
"SCLK dependency table is missing.",
@@ -770,32 +777,45 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr
*hwmgr)
"MCLK dependency table count is 0",
return -EINVAL);
- /* Initialize Sclk DPM table based on allow Sclk values */
+ /* Initialize Sclk and VDDC DPM table based on allow Sclk values */
data->dpm_table.sclk_table.count = 0;
+ data->dpm_table.vddc_table.count = 0;
for (i = 0; i < dep_sclk_table->count; i++) {
if (i == 0 ||
data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count -
1].value !=
dep_sclk_table->entries[i].clk)
{
+ phm_ppt_v1_clock_voltage_dependency_record *entry =
_sclk_table->entries[i];
-
data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
- dep_sclk_table->entries[i].clk;
+ sclk_table->dpm_levels[sclk_table->count].value =
entry->clk;
+ sclk_table->dpm_levels[sclk_table->count].enabled = i
== 0;
+ sclk_table->count++;
-
data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled
=
- (i == 0) ? true : false;
- data->dpm_table.sclk_table.count++;
+ vddc_table->dpm_levels[vddc_table->count].value =
entry->vddc;
+ vddc_table->dpm_levels[vddc_table->count].enabled = i
== 0;
+ vddc_table->count++;
}
}
- /* Initialize Mclk DPM table based on allow Mclk values */
+ /* Initialize Mclk, VDDCI and MVDD DPM table based on allow Mclk values
*/
data->dpm_table.mclk_table.count = 0;
+ data->dpm_table.mvdd_table.count = 0;
+ data->dpm_table.vddci_table.count = 0;
for (i = 0; i < dep_mclk_table->count; i++) {
if (i == 0 || data->dpm_table.mclk_table.dpm_levels
[data->dpm_table.mclk_table.count - 1].value !=
dep_mclk_table->entries[i].clk)
{
-
data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
-
dep_mclk_table->entries[i].clk;
-
data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled
=
- (i == 0) ? true : false;
- data->dpm_table.mclk_table.count++;
+ phm_ppt_v1_clock_voltage_dependency_record *entry =
_mclk_table->entries[i];
+
+
