[PATCH libdrm] amdgpu: Use the canonical form in branch predicate

[Edward O'Callaghan]

Suggested-by: Emil Velikov <emil.l.veli...@gmail.com>
Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 amdgpu/amdgpu_cs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 0993a6d..868eb7b 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -559,7 +559,7 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
if (ring >= AMDGPU_CS_MAX_RINGS)
return -EINVAL;
/* must signal first */
-   if (NULL == sem->signal_fence.context)
+   if (!sem->signal_fence.context)
return -EINVAL;
 
pthread_mutex_lock(>sequence_mutex);
-- 
2.9.3

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Re: [PATCH] drm/amd/powerplay: add error message to remind user updating firmware

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 04/20/2017 05:33 PM, Huang Rui wrote:
> Signed-off-by: Huang Rui <ray.hu...@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
> index 2685f02..b3f3af2 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
> @@ -378,8 +378,11 @@ static int vega10_verify_smc_interface(struct pp_smumgr 
> *smumgr)
>   "Attempt to read SMC IF Version Number Failed!",
>   return -1);
>  
> - if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION)
> - return -1;
> + if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) {
> + pr_err("Your firmware(0x%x) doesn't match 
> SMU9_DRIVER_IF_VERSION(0x%x). Please update your firmware!\n",
> +smc_driver_if_version, SMU9_DRIVER_IF_VERSION);
> + return -EINVAL;
> + }
>  
>   return 0;
>  }
> 



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Re: [PATCH libdrm 1/2] amdgpu: add the interface of waiting multiple fences

[Edward O'Callaghan]

On 04/19/2017 04:28 AM, Nicolai Hähnle wrote:
> On 18.04.2017 17:47, Edward O'Callaghan wrote:
>> On 04/14/2017 12:47 AM, Nicolai Hähnle wrote:
>>> From: Nicolai Hähnle <nicolai.haeh...@amd.com>
>>>
>>> Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
>>> [v2: allow returning the first signaled fence index]
>>> Signed-off-by: monk.liu <monk@amd.com>
>>> [v3:
>>>  - cleanup *status setting
>>>  - fix amdgpu symbols check]
>>> Signed-off-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
>>> Reviewed-by: Christian König <christian.koe...@amd.com> (v1)
>>> Reviewed-by: Jammy Zhou <jammy.z...@amd.com> (v1)
>>> ---
>>>  amdgpu/amdgpu-symbol-check |  1 +
>>>  amdgpu/amdgpu.h| 23 ++
>>>  amdgpu/amdgpu_cs.c | 74
>>> ++
>>>  3 files changed, 98 insertions(+)
>>>
> [snip]
>>> +static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences,
>>> +uint32_t fence_count,
>>> +bool wait_all,
>>> +uint64_t timeout_ns,
>>> +uint32_t *status,
>>> +uint32_t *first)
>>> +{
>>> +struct drm_amdgpu_fence *drm_fences;
>>> +amdgpu_device_handle dev = fences[0].context->dev;
>>> +union drm_amdgpu_wait_fences args;
>>> +int r;
>>> +uint32_t i;
>>> +
>>> +drm_fences = alloca(sizeof(struct drm_amdgpu_fence) * fence_count);
>>> +for (i = 0; i < fence_count; i++) {
>>> +drm_fences[i].ctx_id = fences[i].context->id;
>>> +drm_fences[i].ip_type = fences[i].ip_type;
>>> +drm_fences[i].ip_instance = fences[i].ip_instance;
>>> +drm_fences[i].ring = fences[i].ring;
>>> +drm_fences[i].seq_no = fences[i].fence;
>>> +}
>>> +
>>> +memset(, 0, sizeof(args));
>>> +args.in.fences = (uint64_t)(uintptr_t)drm_fences;
>>> +args.in.fence_count = fence_count;
>>> +args.in.wait_all = wait_all;
>>> +args.in.timeout_ns = amdgpu_cs_calculate_timeout(timeout_ns);
>>> +
>>> +r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_FENCES, );
>>> +if (r)
>>> +return -errno;
>>
>> Hi Nicolai,
>>
>> you will leak drm_fences here on the error branch.
> 
> It's an alloca, so it's automatically freed when the function returns.
> 
> 
>>> +
>>> +*status = args.out.status;
>>> +
>>> +if (first)
>>> +*first = args.out.first_signaled;
>>> +
>>> +return 0;
>>> +}
>>> +
>>> +int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
>>> +  uint32_t fence_count,
>>> +  bool wait_all,
>>> +  uint64_t timeout_ns,
>>> +  uint32_t *status,
>>> +  uint32_t *first)
>>> +{
>>> +uint32_t i;
>>> +int r;
>>
>> no need for a intermediate ret, just return amdgpu_ioctl_wait_fences()
>> directly?
> 
> Good point, I'll change that before I push.
> 
> 
>>> +
>>> +/* Sanity check */
>>> +if (NULL == fences)
>>> +return -EINVAL;
>>> +if (NULL == status)
>>> +return -EINVAL;
>>> +if (fence_count <= 0)
>>> +return -EINVAL;
>>
>> may as well combine these branches?
>>
>> if (!fences || !status || !fence_count)
>> return -EINVAL;
>>
>> as fence_count is unsigned.
> 
> Yeah, that makes some sense, but I decided to keep the separate
> if-statements because other functions are written like this as well.

Its not completely consistent actually, I sent in a patch last night to
fix the rest.

Cheers,
Edward.

> 
> Thanks,
> Nicolai
> 
> 
> 
>>
>> Kind Regards,
>> Edward.
>>
>>> +for (i = 0; i < fence_count; i++) {
>>> +if (NULL == fences[i].context)
>>> +return -EINVAL;
>>> +if (fences[i].ip_type >= AMDGPU_HW_IP_NUM)
>>> +return -EINVAL;
>>> +if (fences[i].ring >= AMDGPU_CS_MAX_RINGS)
>>> +return -EINVAL;
>>> +}
>>> +
>>> +*status = 0;
>>> +
>>> +r = amdgpu_ioctl_wait_fences(fences, fence_count, wait_all,
>>> timeout_ns,
>>> + status, first);
>>> +
>>> +return r;
>>> +}
>>> +
>>>  int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem)
>>>  {
>>>  struct amdgpu_semaphore *gpu_semaphore;
>>>
>>>  if (NULL == sem)
>>>  return -EINVAL;
>>>
>>>  gpu_semaphore = calloc(1, sizeof(struct amdgpu_semaphore));
>>>  if (NULL == gpu_semaphore)
>>>  return -ENOMEM;
>>>
>>
> 
> 



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[libdrm] amdgpu/: concisely && consistently check null ptrs in canonical form

[Edward O'Callaghan]

Be consistent and use the canonical form while sanity checking
null pointers, also combine a few branches for brevity.

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 amdgpu/amdgpu_bo.c   |  2 +-
 amdgpu/amdgpu_cs.c   | 36 +++-
 amdgpu/amdgpu_gpu_info.c |  5 +++--
 3 files changed, 15 insertions(+), 28 deletions(-)

diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index 9adfffa..5ac456b 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -652,7 +652,7 @@ int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
return -EINVAL;
 
list = malloc(number_of_resources * sizeof(struct 
drm_amdgpu_bo_list_entry));
-   if (list == NULL)
+   if (!list)
return -ENOMEM;
 
args.in.operation = AMDGPU_BO_LIST_OP_UPDATE;
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index fb5b3a8..7fbba96 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -59,13 +59,11 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
int i, j, k;
int r;
 
-   if (NULL == dev)
-   return -EINVAL;
-   if (NULL == context)
+   if (!dev || !context)
return -EINVAL;
 
gpu_context = calloc(1, sizeof(struct amdgpu_context));
-   if (NULL == gpu_context)
+   if (!gpu_context)
return -ENOMEM;
 
gpu_context->dev = dev;
@@ -110,7 +108,7 @@ int amdgpu_cs_ctx_free(amdgpu_context_handle context)
int i, j, k;
int r;
 
-   if (NULL == context)
+   if (!context)
return -EINVAL;
 
pthread_mutex_destroy(>sequence_mutex);
@@ -330,9 +328,7 @@ int amdgpu_cs_submit(amdgpu_context_handle context,
uint32_t i;
int r;
 
-   if (NULL == context)
-   return -EINVAL;
-   if (NULL == ibs_request)
+   if (!context || !ibs_request)
return -EINVAL;
 
r = 0;
@@ -416,11 +412,7 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence 
*fence,
bool busy = true;
int r;
 
-   if (NULL == fence)
-   return -EINVAL;
-   if (NULL == expired)
-   return -EINVAL;
-   if (NULL == fence->context)
+   if (!fence || !expired || !fence->context)
return -EINVAL;
if (fence->ip_type >= AMDGPU_HW_IP_NUM)
return -EINVAL;
@@ -447,11 +439,11 @@ int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle 
*sem)
 {
struct amdgpu_semaphore *gpu_semaphore;
 
-   if (NULL == sem)
+   if (!sem)
return -EINVAL;
 
gpu_semaphore = calloc(1, sizeof(struct amdgpu_semaphore));
-   if (NULL == gpu_semaphore)
+   if (!gpu_semaphore)
return -ENOMEM;
 
atomic_set(_semaphore->refcount, 1);
@@ -466,14 +458,12 @@ int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
   uint32_t ring,
   amdgpu_semaphore_handle sem)
 {
-   if (NULL == ctx)
+   if (!ctx || !sem)
return -EINVAL;
if (ip_type >= AMDGPU_HW_IP_NUM)
return -EINVAL;
if (ring >= AMDGPU_CS_MAX_RINGS)
return -EINVAL;
-   if (NULL == sem)
-   return -EINVAL;
/* sem has been signaled */
if (sem->signal_fence.context)
return -EINVAL;
@@ -494,14 +484,12 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
 uint32_t ring,
 amdgpu_semaphore_handle sem)
 {
-   if (NULL == ctx)
+   if (!ctx || !sem)
return -EINVAL;
if (ip_type >= AMDGPU_HW_IP_NUM)
return -EINVAL;
if (ring >= AMDGPU_CS_MAX_RINGS)
return -EINVAL;
-   if (NULL == sem)
-   return -EINVAL;
/* must signal first */
if (NULL == sem->signal_fence.context)
return -EINVAL;
@@ -514,9 +502,7 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
 
 static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem)
 {
-   if (NULL == sem)
-   return -EINVAL;
-   if (NULL == sem->signal_fence.context)
+   if (!sem || !sem->signal_fence.context)
return -EINVAL;
 
sem->signal_fence.context = NULL;;
@@ -530,7 +516,7 @@ static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem)
 
 static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem)
 {
-   if (NULL == sem)
+   if (!sem)
return -EINVAL;
 
if (update_references(>refcount, NULL))
diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c
index f4b94c9..1efffc6 100644
--- a/amdgpu/amdgpu_gpu_info.c
+++ b/amdgpu/amdgpu_gpu_info.c
@@ -234,8 +234,9 @@ drm_private int 
amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
 int amdgpu_query_gpu_info(amdgpu_device_handle 

Re: [PATCH libdrm 1/2] amdgpu: add the interface of waiting multiple fences

[Edward O'Callaghan]

On 04/14/2017 12:47 AM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle 
> 
> Signed-off-by: Junwei Zhang 
> [v2: allow returning the first signaled fence index]
> Signed-off-by: monk.liu 
> [v3:
>  - cleanup *status setting
>  - fix amdgpu symbols check]
> Signed-off-by: Nicolai Hähnle 
> Reviewed-by: Christian König  (v1)
> Reviewed-by: Jammy Zhou  (v1)
> ---
>  amdgpu/amdgpu-symbol-check |  1 +
>  amdgpu/amdgpu.h| 23 ++
>  amdgpu/amdgpu_cs.c | 74 
> ++
>  3 files changed, 98 insertions(+)
> 
> diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
> index 4d1ae65..81ef9b4 100755
> --- a/amdgpu/amdgpu-symbol-check
> +++ b/amdgpu/amdgpu-symbol-check
> @@ -26,20 +26,21 @@ amdgpu_bo_va_op_raw
>  amdgpu_bo_wait_for_idle
>  amdgpu_create_bo_from_user_mem
>  amdgpu_cs_create_semaphore
>  amdgpu_cs_ctx_create
>  amdgpu_cs_ctx_free
>  amdgpu_cs_destroy_semaphore
>  amdgpu_cs_query_fence_status
>  amdgpu_cs_query_reset_state
>  amdgpu_cs_signal_semaphore
>  amdgpu_cs_submit
> +amdgpu_cs_wait_fences
>  amdgpu_cs_wait_semaphore
>  amdgpu_device_deinitialize
>  amdgpu_device_initialize
>  amdgpu_get_marketing_name
>  amdgpu_query_buffer_size_alignment
>  amdgpu_query_crtc_from_id
>  amdgpu_query_firmware_version
>  amdgpu_query_gds_info
>  amdgpu_query_gpu_info
>  amdgpu_query_heap_info
> diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
> index 55884b2..fdea905 100644
> --- a/amdgpu/amdgpu.h
> +++ b/amdgpu/amdgpu.h
> @@ -900,20 +900,43 @@ int amdgpu_cs_submit(amdgpu_context_handle context,
>   *returned in the case if submission was completed or timeout error
>   *code.
>   *
>   * \sa amdgpu_cs_submit()
>  */
>  int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
>uint64_t timeout_ns,
>uint64_t flags,
>uint32_t *expired);
>  
> +/**
> + *  Wait for multiple fences
> + *
> + * \param   fences  - \c [in] The fence array to wait
> + * \param   fence_count - \c [in] The fence count
> + * \param   wait_all- \c [in] If true, wait all fences to be signaled,
> + *otherwise, wait at least one fence
> + * \param   timeout_ns  - \c [in] The timeout to wait, in nanoseconds
> + * \param   status  - \c [out] '1' for signaled, '0' for timeout
> + * \param   first   - \c [out] the index of the first signaled fence 
> from @fences
> + *
> + * \return  0 on success
> + *  <0 - Negative POSIX Error code
> + *
> + * \noteCurrently it supports only one amdgpu_device. All fences come 
> from
> + *  the same amdgpu_device with the same fd.
> +*/
> +int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
> +   uint32_t fence_count,
> +   bool wait_all,
> +   uint64_t timeout_ns,
> +   uint32_t *status, uint32_t *first);
> +
>  /*
>   * Query / Info API
>   *
>  */
>  
>  /**
>   * Query allocation size alignments
>   *
>   * UMD should query information about GPU VM MC size alignments requirements
>   * to be able correctly choose required allocation size and implement
> diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
> index fb5b3a8..707e6d1 100644
> --- a/amdgpu/amdgpu_cs.c
> +++ b/amdgpu/amdgpu_cs.c
> @@ -436,20 +436,94 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence 
> *fence,
>   r = amdgpu_ioctl_wait_cs(fence->context, fence->ip_type,
>   fence->ip_instance, fence->ring,
>   fence->fence, timeout_ns, flags, );
>  
>   if (!r && !busy)
>   *expired = true;
>  
>   return r;
>  }
>  
> +static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences,
> + uint32_t fence_count,
> + bool wait_all,
> + uint64_t timeout_ns,
> + uint32_t *status,
> + uint32_t *first)
> +{
> + struct drm_amdgpu_fence *drm_fences;
> + amdgpu_device_handle dev = fences[0].context->dev;
> + union drm_amdgpu_wait_fences args;
> + int r;
> + uint32_t i;
> +
> + drm_fences = alloca(sizeof(struct drm_amdgpu_fence) * fence_count);
> + for (i = 0; i < fence_count; i++) {
> + drm_fences[i].ctx_id = fences[i].context->id;
> + drm_fences[i].ip_type = fences[i].ip_type;
> + drm_fences[i].ip_instance = fences[i].ip_instance;
> + drm_fences[i].ring = fences[i].ring;
> + drm_fences[i].seq_no = fences[i].fence;
> + }
> +
> + memset(, 0, sizeof(args));
> + args.in.fences = (uint64_t)(uintptr_t)drm_fences;
> + args.in.fence_count = 

Re: [PATCH umr] Add new AI+ field to RELEASE_MEM decoding

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 04/17/2017 10:43 PM, Tom St Denis wrote:
> As well as add EVENT type decoding to human readable
> string.
> 
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
> ---
>  src/lib/ring_decode.c | 66 
> ---
>  1 file changed, 63 insertions(+), 3 deletions(-)
> 
> diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
> index ab1cb9d46411..372bb43595b8 100644
> --- a/src/lib/ring_decode.c
> +++ b/src/lib/ring_decode.c
> @@ -284,6 +284,60 @@ static const char *pm4_pkt3_opcode_names[] = {
>   "UNK", // ff
>  };
>  
> +static const struct {
> + char *name;
> + unsigned event_no;
> +} vgt_event_tags[] = {
> + { "SAMPLE_STREAMOUTSTATS1", 1 },
> + { "SAMPLE_STREAMOUTSTATS2", 2 },
> + { "SAMPLE_STREAMOUTSTATS3", 3 },
> + { "CACHE_FLUSH_TS", 4 },
> + { "CACHE_FLUSH", 6 },
> + { "CS_PARTIAL_FLUSH", 7 },
> + { "VGT_STREAMOUT_RESET", 10 },
> + { "END_OF_PIPE_INCR_DE", 11 },
> + { "END_OF_PIPE_IB_END", 12 },
> + { "RST_PIX_CNT", 13 },
> + { "VS_PARTIAL_FLUSH", 15 },
> + { "PS_PARTIAL_FLUSH", 16 },
> + { "CACHE_FLUSH_AND_INV_TS_EVENT", 20 },
> + { "ZPASS_DONE", 21 },
> + { "CACHE_FLUSH_AND_INV_EVENT", 22 },
> + { "PERFCOUNTER_START", 23 },
> + { "PERFCOUNTER_STOP", 24 },
> + { "PIPELINESTAT_START", 25 },
> + { "PIPELINESTAT_STOP", 26 },
> + { "PERFCOUNTER_SAMPLE", 27 },
> + { "SAMPLE_PIPELINESTAT", 30 },
> + { "SAMPLE_STREAMOUTSTATS", 32 },
> + { "RESET_VTX_CNT", 33 },
> + { "VGT_FLUSH", 36 },
> + { "BOTTOM_OF_PIPE_TS", 40 },
> + { "DB_CACHE_FLUSH_AND_INV", 42 },
> + { "FLUSH_AND_INV_DB_DATA_TS", 43 },
> + { "FLUSH_AND_INV_DB_META", 44 },
> + { "FLUSH_AND_INV_CB_DATA_TS", 45 },
> + { "FLUSH_AND_INV_CB_META", 46 },
> + { "CS_DONE", 47 },
> + { "PS_DONE", 48 },
> + { "FLUSH_AND_INV_CB_PIXEL_DATA", 49 },
> + { "THREAD_TRACE_START", 51 },
> + { "THREAD_TRACE_STOP", 52 },
> + { "THREAD_TRACE_FLUSH", 54 },
> + { "THREAD_TRACE_FINISH", 55 },
> + { NULL, 0 },
> +};
> +
> +static char *vgt_event_decode(unsigned tag)
> +{
> + unsigned x;
> + for (x = 0; vgt_event_tags[x].name; x++) {
> + if (vgt_event_tags[x].event_no == tag)
> + return vgt_event_tags[x].name;
> + }
> + return "";
> +}
> +
>  #define BITS(x, a, b) (unsigned long)((x >> a) & ((1ULL << (b-a))-1))
>  
>  void add_ib(struct umr_ring_decoder *decoder)
> @@ -454,12 +508,11 @@ static void print_decode_pm4_pkt3(struct umr_asic 
> *asic, struct umr_ring_decoder
>   break;
>   case 0x49: // RELEASE_MEM
>   switch(decoder->pm4.cur_word) {
> - case 0: printf("EOP_TCL1_ACTION: %lu, 
> EOP_TC_ACTION: %lu, EOP_TC_WB_ACTION: %lu, EVENT_TYPE: %lu, EVENT_INDEX: %lu",
> - BITS(ib, 16, 17), BITS(ib, 17, 18), BITS(ib, 
> 15, 16), BITS(ib, 0, 7), BITS(ib, 8, 15));
> + case 0: printf("EOP_TCL1_ACTION: %lu, 
> EOP_TC_ACTION: %lu, EOP_TC_WB_ACTION: %lu, EVENT_TYPE: %lu[%s], EVENT_INDEX: 
> %lu",
> + BITS(ib, 16, 17), BITS(ib, 17, 18), BITS(ib, 
> 15, 16), BITS(ib, 0, 7), vgt_event_decode(BITS(ib, 0, 7)), BITS(ib, 8, 15));
>   break;
>   case 1:
>   printf("DATA_SEL+INT_SEL: 0x%08lx", 
> (unsigned long)ib);
> -//DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)
>   break;
>   case 2: printf("ADDR_LO: 0x%08lx", (unsigned 
> long)ib);
>   break;
> @@ -469,6 +522,13 @@ static void print_decode_pm4_pkt3(struct umr_asic *asic, 
> struct umr_ring_decoder
>   break;
>   case 5: printf("SEQ_HI: 0x%08lx", (unsigned 
> long)ib);
>   break;
> + case 6:
> + if (asic->family >= FAMILY_AI) {
> + // decode additional words
> + printf("DATA: 0x%08lx", 
> (unsigned long)ib);
> + break;
> + }
> + // fall through to invalid
>   default: printf("Invalid word for opcode 
> 0x%02lx", (unsigned long)decoder->pm4.cur_opcode);
>   }
>   break;
> 



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Re: [PATCH umr] Prevent reading sensors far too quickly.

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 04/12/2017 11:10 PM, Tom St Denis wrote:
> On platforms without GPU_POWER sensors the thread reading sensors would 
> proceed
> far too quickly.  So it is now rate limited to 50Hz to be consistent.
> 
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
> ---
>  src/app/top.c | 12 +++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/src/app/top.c b/src/app/top.c
> index 96e33ff2e1da..364180eb70f6 100644
> --- a/src/app/top.c
> +++ b/src/app/top.c
> @@ -293,18 +293,24 @@ static volatile struct umr_bitfield *sensor_bits = NULL;
>  static void *gpu_sensor_thread(void *data)
>  {
>   struct umr_asic asic = *((struct umr_asic*)data);
> - int size, rem, off, x;
> + int size, rem, off, x, power;
>   char fname[128];
> + struct timespec ts;
> +
> + ts.tv_sec = 0;
> + ts.tv_nsec = 10UL / 50; // limit to 50Hz
>  
>   snprintf(fname, sizeof(fname)-1, 
> "/sys/kernel/debug/dri/%d/amdgpu_sensors", asic.instance);
>   asic.fd.sensors = open(fname, O_RDWR);
>   while (!sensor_thread_quit) {
>   rem = sizeof gpu_power_data;
>   off = 0;
> + power = 0;
>   for (x = 0; sensor_bits[x].regname; ) {
>   switch (sensor_bits[x].start) {
>   case AMDGPU_PP_SENSOR_GPU_POWER:
>   size = 16;
> + power = 1;
>   break;
>   default:
>   size = 4;
> @@ -316,6 +322,10 @@ static void *gpu_sensor_thread(void *data)
>   rem -= size;
>   x   += size / 4;
>   }
> +
> + // sleep for 20ms if no GPU power sensor to rate limit things a 
> bit
> + if (!power)
> + nanosleep(, NULL);
>   }
>   close(asic.fd.sensors);
>   return NULL;
> 



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Re: [PATCH umr] Add AI sensors to --top

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 04/07/2017 08:47 PM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
> ---
>  src/app/top.c | 14 +-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/src/app/top.c b/src/app/top.c
> index b8a91e317ba5..96e33ff2e1da 100644
> --- a/src/app/top.c
> +++ b/src/app/top.c
> @@ -252,6 +252,15 @@ static struct umr_bitfield stat_si_sensor_bits[] = {
>   { NULL, 0, 0, NULL },
>  };
>  
> +static struct umr_bitfield stat_ai_sensor_bits[] = {
> + { "GFX_SCLK", AMDGPU_PP_SENSOR_GFX_SCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
> _bitfield_default },
> + { "GFX_MCLK", AMDGPU_PP_SENSOR_GFX_MCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
> _bitfield_default },
> + { "GPU_LOAD", AMDGPU_PP_SENSOR_GPU_LOAD, SENSOR_PERCENT<<4, 
> _bitfield_default },
> + { "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), 
> _bitfield_default },
> + { NULL, 0, 0, NULL },
> +};
> +
> +
>  #define AMDGPU_INFO_NUM_BYTES_MOVED  0x0f
>  #define AMDGPU_INFO_VRAM_USAGE   0x10
>  #define AMDGPU_INFO_GTT_USAGE0x11
> @@ -794,7 +803,10 @@ static void top_build_vi_program(struct umr_asic *asic)
>   ENTRY(i++, "mmRLC_GPM_STAT", _rlc_gpm_bits[0], 
> _options.vi.gfxpwr, "GFX PWR");
>  
>   // sensors
> - if (asic->config.gfx.family == 135) {
> + if (asic->config.gfx.family == 141) {
> + // Arctic Island Family
> + ENTRY_SENSOR(i++, "GFX_SCLK", _ai_sensor_bits[0], 
> _options.vi.sensors, "Sensors");
> + } else if (asic->config.gfx.family == 135) {
>   // Carrizo/Stoney family
>   ENTRY_SENSOR(i++, "GFX_SCLK", _carrizo_sensor_bits[0], 
> _options.vi.sensors, "Sensors");
>   } else if (asic->config.gfx.family == 130) {
> 



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Re: [PATCH umr] Add family text for family 141

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 03/25/2017 01:08 AM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
> ---
>  src/app/print_config.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/app/print_config.c b/src/app/print_config.c
> index 6dbe0d42b8dc..e295302ab7a3 100644
> --- a/src/app/print_config.c
> +++ b/src/app/print_config.c
> @@ -91,6 +91,7 @@ static const struct {
>   { "Kaveri", 125 },
>   { "Volcanic Islands", 130 },
>   { "Carrizo", 135 },
> + { "Arctic Islands", 141 },
>   { NULL, 0 },
>  };
>  
> 



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Re: [PATCH] Fix a misspelling of 'acceleration' in amdgpu_kms.c

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 03/26/2017 12:38 AM, Nicholas Molloy wrote:
> ---
>  src/amdgpu_kms.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
> index 4821e93..c4ac90d 100644
> --- a/src/amdgpu_kms.c
> +++ b/src/amdgpu_kms.c
> @@ -1796,7 +1796,7 @@ Bool AMDGPUScreenInit_KMS(SCREEN_INIT_ARGS_DECL)
>   xf86DrvMsg(pScrn->scrnIndex, X_INFO, "3D acceleration 
> disabled\n");
>   xf86DrvMsg(pScrn->scrnIndex, X_INFO, "2D acceleration 
> disabled\n");
>   } else {
> - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "2D and 3D cceleration 
> disabled\n");
> + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "2D and 3D acceleration 
> disabled\n");
>   }
>  
>   /* Init DPMS */
> 



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Re: [PATCH umr] Add program memory dump to wave status.

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 03/22/2017 01:11 AM, Tom St Denis wrote:
> It will display the leading 4 words up to
> the current PC value and then 4 words after.
> 
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
> ---
>  src/app/print_waves.c | 44 +---
>  1 file changed, 33 insertions(+), 11 deletions(-)
> 
> diff --git a/src/app/print_waves.c b/src/app/print_waves.c
> index f0eeeba43a99..e3662983d8d1 100644
> --- a/src/app/print_waves.c
> +++ b/src/app/print_waves.c
> @@ -35,7 +35,8 @@
>  
>  void umr_print_waves(struct umr_asic *asic)
>  {
> - uint32_t x, se, sh, cu, simd, wave, sgprs[1024], shift;
> + uint32_t x, se, sh, cu, simd, wave, sgprs[1024], shift, opcodes[8];
> + uint64_t pgm_addr;
>   struct umr_wave_status ws;
>   int first = 1, col = 0;
>  
> @@ -74,17 +75,24 @@ void umr_print_waves(struct umr_asic *asic)
>  (unsigned long)ws.hw_id.value, (unsigned long)ws.gpr_alloc.value, (unsigned 
> long)ws.lds_alloc.value, (unsigned long)ws.trapsts.value, (unsigned 
> long)ws.ib_sts.value,
>  (unsigned long)ws.tba_hi, (unsigned long)ws.tba_lo, (unsigned 
> long)ws.tma_hi, (unsigned long)ws.tma_lo, (unsigned long)ws.ib_dbg0, 
> (unsigned long)ws.m0
>  );
> - for (x = 0; x < 
> ((ws.gpr_alloc.sgpr_size + 1) << shift); x += 4)
> - printf(">SGPRS[%u..%u] = { 
> %08lx, %08lx, %08lx, %08lx }\n",
> - 
> (unsigned)((ws.gpr_alloc.sgpr_base << shift) + x),
> - 
> (unsigned)((ws.gpr_alloc.sgpr_base << shift) + x + 3),
> - (unsigned long)sgprs[x],
> - (unsigned 
> long)sgprs[x+1],
> - (unsigned 
> long)sgprs[x+2],
> - (unsigned 
> long)sgprs[x+3]);
> - }
> + for (x = 0; x < 
> ((ws.gpr_alloc.sgpr_size + 1) << shift); x += 4)
> + printf(">SGPRS[%u..%u] 
> = { %08lx, %08lx, %08lx, %08lx }\n",
> + 
> (unsigned)((ws.gpr_alloc.sgpr_base << shift) + x),
> + 
> (unsigned)((ws.gpr_alloc.sgpr_base << shift) + x + 3),
> + (unsigned 
> long)sgprs[x],
> + (unsigned 
> long)sgprs[x+1],
> + (unsigned 
> long)sgprs[x+2],
> + (unsigned 
> long)sgprs[x+3]);
>  
> - if (options.bitfields) {
> + pgm_addr = (((uint64_t)ws.pc_hi 
> << 32) | ws.pc_lo) - (sizeof(opcodes)/2);
> + umr_read_vram(asic, 
> ws.hw_id.vm_id, pgm_addr, sizeof(opcodes), opcodes);
> + for (x = 0; x < 
> sizeof(opcodes)/4; x++) {
> + printf(">pgm[%lu@%llx] 
> = %08lx\n",
> + (unsigned 
> long)ws.hw_id.vm_id,
> + (unsigned long 
> long)(pgm_addr + 4 * x),
> + (unsigned 
> long)opcodes[x]);
> + }
> + } else {
>   first = 0;
>   
> printf("\n--\nse%u.sh%u.cu%u.simd%u.wave%u\n",
>   (unsigned)se, (unsigned)sh, 
> (unsigned)cu, (unsigned)ws.hw_id.simd_id, (unsigned)ws.hw_id.wave_id);
> @@ -156,6 +164,20 @@ void umr_print_waves(struct umr_asic *asic)
>   (unsigned 
> long)sgprs[x+2],
>   (unsigned 
> long)sgprs[x+3]);
>  
> + printf("\n\nPGM_MEM:\n");
> +

Re: [PATCH 0/6] drm/amdgpu: add get clockgating functions for new asic

[Edward O'Callaghan]

This series is,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 03/24/2017 04:47 PM, Huang Rui wrote:
> Hi all,
> 
> This patch set adds get_clockgating functions, after that, we can use
> debugfs pm to check the dynamic clockgating status.
> 
> Thanks,
> Rui
> 
> Huang Rui (6):
>   drm/amdgpu: add get_clockgating callback for gfx v9
>   drm/amdgpu: add get_clockgating callback for nbio v6.1
>   drm/amdgpu: add get_clockgating callback for soc15
>   drm/amdgpu: add get_clockgating for sdma v4
>   drm/amdgpu: add get_clockgating callback for mmhub v1
>   drm/amdgpu: fix to remove HDP MGCG on soc15
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c  |  6 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 43 
> +
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 17 +
>  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c  | 15 
>  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h  |  1 +
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  | 17 +
>  drivers/gpu/drm/amd/amdgpu/soc15.c  | 35 ++-
>  7 files changed, 133 insertions(+), 1 deletion(-)
> 



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Re: [PATCH 000/100] Add Vega10 Support

[Edward O'Callaghan]

On 03/21/2017 05:36 PM, Christian König wrote:
> Am 21.03.2017 um 00:38 schrieb Tom St Denis:
>> On 03/20/2017 06:34 PM, Jan Ziak wrote:
>>> On Mon, Mar 20, 2017 at 10:41 PM, Alex Deucher >> > wrote:
>>>
>>> On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak <0xe2.0x9a.0...@gmail.com
>>> > wrote:
>>> > Hi
>>> >
>>> >
>>> https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9=9555ef0ba926df25d9a637d0ea21bc0d231c21d2
>>>
>>> 
>>>
>>> >
>>> > The file nbio_6_1_sh_mask.h is uncompressed. It consists from
>>> 133884 lines.
>>> > Only generated C/C++ code will be able to utilize the content
>>> of such a file
>>> > efficiently. All hand-written codes combined will be able to
>>> utilize about
>>> > 1% of the file.
>>> >
>>> > Is there a reason why nbio_6_1_sh_mask.h is huge?
>>>
>>> That IP block contains a lot of registers.  The idea is to open
>>> source
>>> as much IP as possible to facilitate debugging, new features, etc.
>>>
>>> Alex
>>>
>>>
>>> [This email contains long/wide lines and should be viewed on a
>>> sufficiently wide screen]
>>>
>>> For example if I open the file in vim and go to line 66952:
>>>
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>>
>>> Then abstracting away some of the digits used in the defined identifier
>>> and using egrep:
>>>
>>> $ egrep
>>> "\"
>>>
>>> nbio_6_1_sh_mask.h
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>>0x9
>>>
>>> The egrep command produced 20 lines.
>>>
>>> Instead of the many #define directives, it is a possibility to define
>>> functions such as:
>>>
>>> int
>>> DWC_E12MP_PHY_Xa_NS_Xb_c_LANEd_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_e__DTB_SEL__SHIFT(int
>>>
>>> a, int b, int c, int d, int e) __attribute__((pure));
>>>
>>> I suppose the file nbio_6_1_sh_mask.h is the output of a tool (it is a
>>> generated file). It is an option to modify the tool to output C
>>> functions with proper input guards instead of #define directives.
>>
>> The 

Re: [PATCH umr] sync up registers/bits with staging tree

[Edward O'Callaghan]

On 03/21/2017 02:31 AM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
> ---
>  scripts/parse_bits.sh| 4 +++-
>  src/lib/ip/dce60_bits.i  | 1 +
>  src/lib/ip/smu712_regs.i | 1 +
>  src/lib/ip/smu713_regs.i | 1 +
>  4 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/scripts/parse_bits.sh b/scripts/parse_bits.sh
> index ebaa6aefb1fa..14df5e831b01 100755
> --- a/scripts/parse_bits.sh
> +++ b/scripts/parse_bits.sh
> @@ -4,7 +4,9 @@
>  # ASICs
>  
>  #this is the path to the tree (not necessarily the one running on your host)
> -pk=/nas/work/repos/linux/drivers/gpu/drm/amd/include/asic_reg/
> +if [ "$pk" == "" ]; then
> + pk=/nas/work/repos/linux/drivers/gpu/drm/amd/include/asic_reg/
> +fi
>  
Hmm, perhaps this hunk should not be conflated in with the rest.

The rest of this patch is,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

>  # parse_bits /path/to/asic_reg/foo/block /path/to/umr/file
>  parse_bits() {
> diff --git a/src/lib/ip/dce60_bits.i b/src/lib/ip/dce60_bits.i
> index 50ae01e400d5..7ced97afed5d 100644
> --- a/src/lib/ip/dce60_bits.i
> +++ b/src/lib/ip/dce60_bits.i
> @@ -2488,6 +2488,7 @@ static struct umr_bitfield mmCC_DC_PIPE_DIS[] = {
>  };
>  static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
>{ "AZALIA_ENDPOINT_REG_INDEX", 0, 7, _bitfield_default },
> +  { "AZALIA_ENDPOINT_REG_WRITE_EN", 8, 8, _bitfield_default },
>  };
>  static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_DATA[] = {
>{ "AZALIA_ENDPOINT_REG_DATA", 0, 31, _bitfield_default },
> diff --git a/src/lib/ip/smu712_regs.i b/src/lib/ip/smu712_regs.i
> index eb030979eaec..f718b000b84b 100644
> --- a/src/lib/ip/smu712_regs.i
> +++ b/src/lib/ip/smu712_regs.i
> @@ -1222,6 +1222,7 @@
>   { "ixCG_THERMAL_INT_ENA", REG_SMC, 0xc2100024, 
> _THERMAL_INT_ENA[0], 
> sizeof(ixCG_THERMAL_INT_ENA)/sizeof(ixCG_THERMAL_INT_ENA[0]), 0, 0 },
>   { "ixCG_THERMAL_INT_CTRL", REG_SMC, 0xc2100028, 
> _THERMAL_INT_CTRL[0], 
> sizeof(ixCG_THERMAL_INT_CTRL)/sizeof(ixCG_THERMAL_INT_CTRL[0]), 0, 0 },
>   { "ixCG_THERMAL_INT_STATUS", REG_SMC, 0xc210002c, 
> _THERMAL_INT_STATUS[0], 
> sizeof(ixCG_THERMAL_INT_STATUS)/sizeof(ixCG_THERMAL_INT_STATUS[0]), 0, 0 },
> + { "ixCURRENT_PG_STATUS_APU", REG_SMC, 0xd020029c, NULL, 0, 0, 0 },
>   { "ixSMU_MAIN_PLL_OP_FREQ", REG_SMC, 0xe0003020, 
> _MAIN_PLL_OP_FREQ[0], 
> sizeof(ixSMU_MAIN_PLL_OP_FREQ)/sizeof(ixSMU_MAIN_PLL_OP_FREQ[0]), 0, 0 },
>   { "ixSMU_STATUS", REG_SMC, 0xe0003088, _STATUS[0], 
> sizeof(ixSMU_STATUS)/sizeof(ixSMU_STATUS[0]), 0, 0 },
>   { "ixSMU_FIRMWARE", REG_SMC, 0xe00030a4, _FIRMWARE[0], 
> sizeof(ixSMU_FIRMWARE)/sizeof(ixSMU_FIRMWARE[0]), 0, 0 },
> diff --git a/src/lib/ip/smu713_regs.i b/src/lib/ip/smu713_regs.i
> index 0f1d79aa2b9f..8a632b41624e 100644
> --- a/src/lib/ip/smu713_regs.i
> +++ b/src/lib/ip/smu713_regs.i
> @@ -1192,6 +1192,7 @@
>   { "ixGC_CAC_ACC_CU13", REG_SMC, 0xc7, _CAC_ACC_CU13[0], 
> sizeof(ixGC_CAC_ACC_CU13)/sizeof(ixGC_CAC_ACC_CU13[0]), 0, 0 },
>   { "ixGC_CAC_ACC_CU14", REG_SMC, 0xc8, _CAC_ACC_CU14[0], 
> sizeof(ixGC_CAC_ACC_CU14)/sizeof(ixGC_CAC_ACC_CU14[0]), 0, 0 },
>   { "ixGC_CAC_ACC_CU15", REG_SMC, 0xc9, _CAC_ACC_CU15[0], 
> sizeof(ixGC_CAC_ACC_CU15)/sizeof(ixGC_CAC_ACC_CU15[0]), 0, 0 },
> + { "ixCURRENT_PG_STATUS_APU", REG_SMC, 0xd020029c, NULL, 0, 0, 0 },
>   { "ixSMU_MAIN_PLL_OP_FREQ", REG_SMC, 0xe0003020, 
> _MAIN_PLL_OP_FREQ[0], 
> sizeof(ixSMU_MAIN_PLL_OP_FREQ)/sizeof(ixSMU_MAIN_PLL_OP_FREQ[0]), 0, 0 },
>   { "ixSMU_STATUS", REG_SMC, 0xe0003088, _STATUS[0], 
> sizeof(ixSMU_STATUS)/sizeof(ixSMU_STATUS[0]), 0, 0 },
>   { "ixSMU_FIRMWARE", REG_SMC, 0xe00030a4, _FIRMWARE[0], 
> sizeof(ixSMU_FIRMWARE)/sizeof(ixSMU_FIRMWARE[0]), 0, 0 },
> 



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Re: [PATCH] drm/amdgpu: bump version for PRT support

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

Alex, as a matter of procedure could you perhaps have the actual version
bump as part of the final patch in a given series? This would mitigate
the issue of forgetting to bump the version for a given relevant changeset.

Kindly,
Edward.

On 03/17/2017 01:46 AM, Alex Deucher wrote:
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index c4dacd5..c75f48e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -62,9 +62,10 @@
>   * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
>   * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
>   * - 3.12.0 - Add query for double offchip LDS buffers
> + * - 3.13.0 - Add PRT support
>   */
>  #define KMS_DRIVER_MAJOR 3
> -#define KMS_DRIVER_MINOR 12
> +#define KMS_DRIVER_MINOR 13
>  #define KMS_DRIVER_PATCHLEVEL0
>  
>  int amdgpu_vram_limit = 0;
> 



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Re: [PATCH umr] PM4 packets list number of dwords not bytes

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 03/09/2017 07:03 AM, Tom St Denis wrote:
> When counting size of IBs count in dwords...
> 
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
> ---
>  src/lib/ring_decode.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
> index 401d6caaa088..a991f5ffa237 100644
> --- a/src/lib/ring_decode.c
> +++ b/src/lib/ring_decode.c
> @@ -334,7 +334,7 @@ static void print_decode_pm4_pkt3(struct umr_asic *asic, 
> struct umr_ring_decoder
>   decoder->pm4.next_ib_state.ib_addr_hi = 
> BITS(ib, 0, 16);
>   break;
>   case 2: printf("IB_SIZE:%lu, VMID: %lu", 
> BITS(ib, 0, 20), BITS(ib, 24, 32));
> - decoder->pm4.next_ib_state.ib_size = 
> BITS(ib, 0, 20);
> + decoder->pm4.next_ib_state.ib_size = 
> BITS(ib, 0, 20) * 4;
>   decoder->pm4.next_ib_state.ib_vmid = 
> BITS(ib, 24, 32);
>   add_ib(decoder);
>   break;
> 



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Re: [PATCH 2/2] drm/amdgpu: bump driver version for some new features

[Edward O'Callaghan]

On 03/09/2017 10:18 AM, Alex Deucher wrote:
> We added new gem ioctl flags and the new fences ioctl, but forgot
> to bump the version.
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

Form which commit Alex? perhaps CC stable?

> 
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 75fc376..f7adbac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -59,9 +59,10 @@
>   * - 3.7.0 - Add support for VCE clock list packet
>   * - 3.8.0 - Add support raster config init in the kernel
>   * - 3.9.0 - Add support for memory query info about VRAM and GTT.
> + * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
>   */
>  #define KMS_DRIVER_MAJOR 3
> -#define KMS_DRIVER_MINOR 9
> +#define KMS_DRIVER_MINOR 10
>  #define KMS_DRIVER_PATCHLEVEL0
>  
>  int amdgpu_vram_limit = 0;
> 



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Re: [PATCH umr] Fix ring offset to dword instead of bytes

[Edward O'Callaghan]

Acked-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 03/09/2017 03:31 AM, Tom St Denis wrote:
> This allows you to specify (say)
> 
> -R gfx[16:32] to read words 16 through 32 which is
> consistent with how the data is presented.
> 
> This patch also correctly enables the PM4 decoder
> when specifying a range of words.
> 
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
> ---
>  src/app/ring_read.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/src/app/ring_read.c b/src/app/ring_read.c
> index 970310b9bf52..d6b3df58be4d 100644
> --- a/src/app/ring_read.c
> +++ b/src/app/ring_read.c
> @@ -96,7 +96,10 @@ void umr_read_ring(struct umr_asic *asic, char *ringpath)
>   } else {
>   sscanf(from, "%"SCNu32, );
>   sscanf(to, "%"SCNu32, );
> + start *= 4;
> + end *= 4;
>   use_decoder = 1;
> + decoder.pm4.cur_opcode = 0x;
>   }
>   }
>   end %= ringsize;
> 



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Re: [PATCH] drm/amdgpu: fix coding style and printing in amdgpu_doorbell_init

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 03/07/2017 12:54 AM, Christian König wrote:
> From: Christian König <christian.koe...@amd.com>
> 
> Based on commit "drm/radeon: remove useless and potentially wrong message".
> 
> The size of the info printing is incorrect and the PCI subsystems prints
> the same info on boot anyway.
> 
> Signed-off-by: Christian König <christian.koe...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 -
>  1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index bf31aaf..fd03072 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -381,12 +381,11 @@ static int amdgpu_doorbell_init(struct amdgpu_device 
> *adev)
>   if (adev->doorbell.num_doorbells == 0)
>   return -EINVAL;
>  
> - adev->doorbell.ptr = ioremap(adev->doorbell.base, 
> adev->doorbell.num_doorbells * sizeof(u32));
> - if (adev->doorbell.ptr == NULL) {
> + adev->doorbell.ptr = ioremap(adev->doorbell.base,
> +  adev->doorbell.num_doorbells *
> +  sizeof(u32));
> + if (adev->doorbell.ptr == NULL)
>   return -ENOMEM;
> - }
> - DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
> - DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
>  
>   return 0;
>  }
> 



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Re: [PATCH] drm/amdgpu/powerplay: enable LEDs on Fiji boards

[Edward O'Callaghan]

Hi guys,

Shouldn't this hook into the "led framework" of the kernel?

https://www.kernel.org/doc/Documentation/leds/leds-class.txt

Kind Regards,
Edward.

On 02/24/2017 10:03 AM, Alex Deucher wrote:
> On Thu, Feb 23, 2017 at 5:50 PM, Alexandre Demers
>  wrote:
>> First, sorry for not replying directly as I should normally, but I'm not on
>> my usual computer, so I can't. That being said...
>>
>> I may have my eyes in the same socket right now, but I think
>> fiji_setup_dpm_led_config() always returns 0.
>>
>>> + if (mask)
>>> + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
>>> +PPSMC_MSG_LedConfig,
>>> +mask);
>>> + return 0;
>>> +}
>>
>> Even when "if (mask)" is true, whether smum_send_msg_to_smc_with_parameter()
>> succeeds or not, fiji_setup_dpm_led_config() spits a 0 at the end.
>>
>> Thus,
>>
>>> + result = fiji_setup_dpm_led_config(hwmgr);
>>> + PP_ASSERT_WITH_CODE(0 == result,
>>> +"Failed to setup dpm led config", return result);
>>
>> will always lead to "result" being set to 0... Am I missing something?
>>
> 
> Yes, that function can't fail.  I suppose we could just make it a void
> function, but I was following the same pattern of all the other
> functions in that file.
> 
> Alex
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Re: [PATCH] drm/amdgpu: trace amdgpu_job fence details

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 02/23/2017 10:47 AM, Andres Rodriguez wrote:
> This trace is intended to provide the required information to associate
> the completion of an amdgpu_job with its corresponding dma_fence_*
> tracepoints.
> 
> Signed-off-by: Andres Rodriguez <andre...@gmail.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   |  2 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 22 ++
>  2 files changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> index 86a1242..84a04e4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> @@ -177,6 +177,8 @@ static struct dma_fence *amdgpu_job_run(struct 
> amd_sched_job *sched_job)
>   /* if gpu reset, hw fence will be replaced here */
>   dma_fence_put(job->fence);
>   job->fence = dma_fence_get(fence);
> + trace_amdgpu_job_attach_fence(job);
> +
>   amdgpu_job_free_resources(job);
>   return fence;
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> index a18ae1e..0a61ed9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> @@ -147,6 +147,28 @@ TRACE_EVENT(amdgpu_sched_run_job,
> __entry->fence, __entry->ring_name, __entry->num_ibs)
>  );
>  
> +TRACE_EVENT(amdgpu_job_attach_fence,
> + TP_PROTO(struct amdgpu_job *job),
> + TP_ARGS(job),
> + TP_STRUCT__entry(
> +  __field(struct amdgpu_device *, adev)
> +  __field(struct amd_sched_job *, sched_job)
> +  __string(timeline, 
> job->fence->ops->get_timeline_name(job->fence))
> +  __field(unsigned int, context)
> +  __field(unsigned int, seqno)
> +  ),
> +
> + TP_fast_assign(
> +__entry->adev = job->adev;
> +__entry->sched_job = >base;
> +__assign_str(timeline, 
> job->fence->ops->get_timeline_name(job->fence))
> +__entry->context = job->fence->context;
> +__entry->seqno = job->fence->seqno;
> +),
> + TP_printk("adev=%p, sched_job=%p, timeline:%s, context:%u, 
> seqno:%u",
> +   __entry->adev, __entry->sched_job,
> +   __get_str(timeline), __entry->context, __entry->seqno)
> +);
>  
>  TRACE_EVENT(amdgpu_vm_grab_id,
>   TP_PROTO(struct amdgpu_vm *vm, int ring, struct amdgpu_job *job),
> 



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Re: [PATCH umr] Simplify --scan and --list-regs syntax

[Edward O'Callaghan]

On 02/23/2017 01:55 AM, Tom St Denis wrote:
> Now it supports the same syntax as --read/--write, you can specify any
> of:
> 
> *.ipname
> asicname.ipname
> ipname
> 
> When using --scan and --list-regs now.  e.g.,
> 
> umr --scan carrizo.uvd6
> or
> umr --scan uvd6
> 
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
> ---
>  src/app/main.c | 39 +++
>  1 file changed, 35 insertions(+), 4 deletions(-)
> 
> diff --git a/src/app/main.c b/src/app/main.c
> index 5b1694654352..a905ff0359cf 100644
> --- a/src/app/main.c
> +++ b/src/app/main.c
> @@ -47,6 +47,31 @@ static struct umr_asic *get_asic(void)
>   return asic;
>  }
>  
> +// returns blockname supports
> +// asicname.blockname
> +// *.blockname
> +// blockname
> +static char *get_block_name(struct umr_asic *asic, char *path)
> +{
> + static char asicname[256], block[256], *dot;
> +
> + memset(asicname, 0, sizeof asicname);
> + if ((dot = strstr(path, "."))) {
> + memset(block, 0, sizeof block);
perhaps move this block zero'ing memset outside the branch above.

with that,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

> + memcpy(asicname, path, (int)(dot - path));
> + strcpy(block, dot + 1);
> + } else {
> + strcpy(block, path);
> + }
> +
> + if (asicname[0] && asicname[0] != '*' && strcmp(asic->asicname, 
> asicname)) {
> + printf("[ERROR]: Invalid asicname <%s>\n", asicname);
> + return NULL;
> + }
> + return block;
> +}
> +
> +
>  static void parse_options(char *str)
>  {
>   char option[64], *p;
> @@ -96,7 +121,7 @@ int main(int argc, char **argv)
>  {
>   int i, j, k, l;
>   struct umr_asic *asic;
> - char *str, *str2, asicname[256], ipname[256], regname[256];
> + char *blockname, *str, *str2, asicname[256], ipname[256], regname[256];
>   struct timespec req;
>  
>   memset(, 0, sizeof options);
> @@ -162,8 +187,11 @@ int main(int argc, char **argv)
>   if (i + 1 < argc) {
>   if (!asic)
>   asic = get_asic();
> + blockname = get_block_name(asic, argv[i+1]);
> + if (!blockname)
> + return EXIT_FAILURE;
>   for (j = 0; j < asic->no_blocks; j++)
> - if (!strcmp(asic->blocks[j]->ipname, 
> argv[i+1]))
> + if (!strcmp(asic->blocks[j]->ipname, 
> blockname))
>   for (k = 0; k < 
> asic->blocks[j]->no_regs; k++) {
>   printf("\t%s.%s.%s => 
> 0x%05lx\n", asic->asicname, asic->blocks[j]->ipname, 
> asic->blocks[j]->regs[k].regname, (unsigned 
> long)asic->blocks[j]->regs[k].addr);
>   if (options.bitfields) {
> @@ -216,8 +244,11 @@ int main(int argc, char **argv)
>   if (i + 1 < argc) {
>   if (!asic)
>   asic = get_asic();
> - if (!umr_scan_asic(asic, "", argv[i+1], ""))
> - umr_print_asic(asic, argv[i+1]);
> + blockname = get_block_name(asic, argv[i+1]);
> + if (!blockname)
> + return EXIT_FAILURE;
> + if (!umr_scan_asic(asic, "", blockname, ""))
> + umr_print_asic(asic, blockname);
>   ++i;
>   options.need_scan = 0;
>   } else {
> 



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Re: [PATCH] drm/amdgpu: add HDMI audio support for si dce6

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 02/21/2017 09:39 PM, Xiaojie Yuan wrote:
> Signed-off-by: Xiaojie Yuan <xiaojie.y...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 130 
> +++---
>  1 file changed, 121 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index c940bec..1398db6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -1531,12 +1531,58 @@ static void dce_v6_0_audio_fini(struct amdgpu_device 
> *adev)
>   adev->mode_info.audio.enabled = false;
>  }
>  
> -/*
> -static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t 
> clock)
> +static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
>  {
> - DRM_INFO(": dce_v6_0_afmt_update_ACR---no imp!\n");
> + struct drm_device *dev = encoder->dev;
> + struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
> + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
> + u32 tmp;
> +
> + tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
> + WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
> +}
> +
> +static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder,
> +uint32_t clock, int bpc)
> +{
> + struct drm_device *dev = encoder->dev;
> + struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
> + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
> + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
> + u32 tmp;
> +
> + tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 
> 1);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
> + bpc > 8 ? 0 : 1);
> + WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
> + WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
> + WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, 
> acr.cts_44_1khz);
> + WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
> + WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
> +
> + tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
> + WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
> + tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
> + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
> + WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
>  }
> -*/
>  
>  static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
>  struct drm_display_mode *mode)
> @@ -1585,6 +1631,7 @@ static void dce_v6_0_audio_set_dto(struct drm_encoder 
> *encoder, u32 clock)
>   struct drm_device *dev = encoder->dev;
>   struct amdgpu_device *adev = dev->dev_private;
>   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
> + int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
>   u32 tmp;
>  
>   /*
> @@ -1596,10 +1643,21 @@ static void dce_v6_0_audio_set_dto(struct drm_encoder 
> *encoder, u32 clock)
>   tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
>   tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
>   DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id);
> - tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, 1);
> + if (em == ATOM_ENCODER_MODE_HDMI) {
> + tmp = REG_SET_FIELD(tmp

Re: [PATCH 17/35] drivers/gpu: Convert remaining uses of pr_warning to pr_warn

[Edward O'Callaghan]

On 02/18/2017 01:22 AM, Christian König wrote:
> Am 17.02.2017 um 08:11 schrieb Joe Perches:
>> To enable eventual removal of pr_warning
>>
>> This makes pr_warn use consistent for drivers/gpu
>>
>> Prior to this patch, there were 15 uses of pr_warning and
>> 20 uses of pr_warn in drivers/gpu
>>
>> Signed-off-by: Joe Perches <j...@perches.com>
> 
> Acked-by: Christian König <christian.koe...@amd.com>.

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

> 
>> ---
>>   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c |  2 +-
>>   drivers/gpu/drm/amd/powerplay/inc/pp_debug.h |  2 +-
>>   drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c  |  4 ++--
>>   drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c   | 14
>> +++---
>>   drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c |  4 ++--
>>   drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c |  4 ++--
>>   6 files changed, 15 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> index b1de9e8ccdbc..83266408634e 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> @@ -1535,7 +1535,7 @@ static int smu7_get_evv_voltages(struct pp_hwmgr
>> *hwmgr)
>>   if (vddc >= 2000 || vddc == 0)
>>   return -EINVAL;
>>   } else {
>> -pr_warning("failed to retrieving EVV voltage!\n");
>> +pr_warn("failed to retrieving EVV voltage!\n");
>>   continue;
>>   }
>>   diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
>> b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
>> index 072880130cfb..f3f9ebb631a5 100644
>> --- a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
>> +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
>> @@ -37,7 +37,7 @@
>>   #define PP_ASSERT_WITH_CODE(cond, msg, code)\
>>   do {\
>>   if (!(cond)) {\
>> -pr_warning("%s\n", msg);\
>> +pr_warn("%s\n", msg);\
>>   code;\
>>   }\
>>   } while (0)
>> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> index 0f7a77b7312e..5450f5ef8e89 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
>> @@ -2131,7 +2131,7 @@ uint32_t fiji_get_offsetof(uint32_t type,
>> uint32_t member)
>>   return offsetof(SMU73_Discrete_DpmTable,
>> LowSclkInterruptThreshold);
>>   }
>>   }
>> -pr_warning("can't get the offset of type %x member %x\n", type,
>> member);
>> +pr_warn("can't get the offset of type %x member %x\n", type,
>> member);
>>   return 0;
>>   }
>>   @@ -2156,7 +2156,7 @@ uint32_t fiji_get_mac_definition(uint32_t value)
>>   return SMU73_MAX_LEVELS_MVDD;
>>   }
>>   -pr_warning("can't get the mac of %x\n", value);
>> +pr_warn("can't get the mac of %x\n", value);
>>   return 0;
>>   }
>>   diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
>> b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
>> index ad82161df831..51adf04ab4b3 100644
>> --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
>> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
>> @@ -122,7 +122,7 @@ static void
>> iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
>>   break;
>>   default:
>>   smu_data->power_tune_defaults = _iceland;
>> -pr_warning("Unknown V.I. Device ID.\n");
>> +pr_warn("Unknown V.I. Device ID.\n");
>>   break;
>>   }
>>   return;
>> @@ -378,7 +378,7 @@ static int
>> iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
>>   return -EINVAL);
>> if (NULL == hwmgr->dyn_state.cac_leakage_table) {
>> -pr_warning("CAC Leakage Table does not exist, using vddc.\n");
>> +pr_warn("CAC Leakage Table does not exist, using vddc.\n");
>>   return 0;
>>   }
>>   @@ -394,7 +394,7 @@ static int
>> iceland_get_std_voltage_value_sidd(s

Re: [PATCH] amdgpu/powerplay: Fixup printk() usage in pp_debug.h

[Edward O'Callaghan]

disregard this, sorry for the noise.

On 02/16/2017 07:42 PM, Edward O'Callaghan wrote:
> We should properly prefix which kernel module this spewed
> from in dmesg for consistency to the user.
> 
> Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
> ---
>  drivers/gpu/drm/amd/powerplay/inc/pp_debug.h | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h 
> b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
> index bfdbec1..e4fad15 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
> @@ -28,12 +28,12 @@
>  #include 
>  #include 
>  
> -#define PP_ASSERT_WITH_CODE(cond, msg, code) \
> - do {\
> - if (!(cond)) {  \
> - printk("%s\n", msg);\
> - code;   \
> - }   \
> +#define PP_ASSERT_WITH_CODE(cond, msg, code) \
> + do {\
> + if (!(cond)) {  \
> + pr_error("amdgpu: %s\n", msg);  \
> + code;   \
> + }   \
>   } while (0)
>  
>  
> 
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Re: [PATCH umr] Add SENSOR for SI/CIK/KV systems.

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 02/18/2017 06:26 AM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
> ---
>  src/app/top.c | 30 ++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/src/app/top.c b/src/app/top.c
> index 92ab8ab854af..c97a0c9d93ab 100644
> --- a/src/app/top.c
> +++ b/src/app/top.c
> @@ -231,6 +231,27 @@ static struct umr_bitfield stat_vi_sensor_bits[] = {
>   { NULL, 0, 0, NULL },
>  };
>  
> +static struct umr_bitfield stat_cik_sensor_bits[] = {
> + { "GFX_SCLK", AMDGPU_PP_SENSOR_GFX_SCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
> _bitfield_default },
> + { "GFX_MCLK", AMDGPU_PP_SENSOR_GFX_MCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
> _bitfield_default },
> + { "GPU_LOAD", AMDGPU_PP_SENSOR_GPU_LOAD, SENSOR_PERCENT<<4, 
> _bitfield_default },
> + { "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), 
> _bitfield_default },
> + { NULL, 0, 0, NULL },
> +};
> +
> +static struct umr_bitfield stat_kaveri_sensor_bits[] = {
> + { "GFX_SCLK", AMDGPU_PP_SENSOR_GFX_SCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
> _bitfield_default },
> + { "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), 
> _bitfield_default },
> + { NULL, 0, 0, NULL },
> +};
> +
> +static struct umr_bitfield stat_si_sensor_bits[] = {
> + { "GFX_SCLK", AMDGPU_PP_SENSOR_GFX_SCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
> _bitfield_default },
> + { "GFX_MCLK", AMDGPU_PP_SENSOR_GFX_MCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
> _bitfield_default },
> + { "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), 
> _bitfield_default },
> + { NULL, 0, 0, NULL },
> +};
> +
>  #define AMDGPU_INFO_NUM_BYTES_MOVED  0x0f
>  #define AMDGPU_INFO_VRAM_USAGE   0x10
>  #define AMDGPU_INFO_GTT_USAGE0x11
> @@ -774,6 +795,15 @@ static void top_build_vi_program(struct umr_asic *asic)
>   } else if (asic->config.gfx.family == 130) {
>   // Volcanic Islands Family
>   ENTRY_SENSOR(i++, "GFX_SCLK", _vi_sensor_bits[0], 
> _options.vi.sensors, "Sensors");
> + } else if (asic->config.gfx.family == 125) {
> + // Fusion
> + ENTRY_SENSOR(i++, "GFX_SCLK", _kaveri_sensor_bits[0], 
> _options.vi.sensors, "Sensors");
> + } else if (asic->config.gfx.family == 120) {
> + // CIK
> + ENTRY_SENSOR(i++, "GFX_SCLK", _cik_sensor_bits[0], 
> _options.vi.sensors, "Sensors");
> + } else if (asic->config.gfx.family == 110) {
> + // SI
> + ENTRY_SENSOR(i++, "GFX_SCLK", _si_sensor_bits[0], 
> _options.vi.sensors, "Sensors");
>   }
>  
>   // More GFX bits
> 



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Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info

[Edward O'Callaghan]

On 02/16/2017 04:46 PM, Zhang, Jerry wrote:
> Hi Edward,
> 
>> Question, is this a bit premature to have a new function and struct for 
>> this, could
>> it just be put in amdgpu_gfx for now or are we expecting amdgpu_gfx_cap to
>> start growing quickly with far more cap state info?
> Yes, we will add more in the future.
> 
> Ideally we'd like to add a feature structure to export all supported by 
> current amdgpu_device.
> Now it's only one for gfx, so I insert a structure in amdgpu_gfx, which was 
> verified by vulkan carrizo. 
> Then I send it out for guys review whether to add in the amdgpu_device 
> directly
> or keep current style till we have other features besides gfx.

Hmmk, its nothing to stress about I was just more curious about it.

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

Kindly,
Edward.

> 
> Regards,
> Jerry (Junwei Zhang)
> 
> Linux Base Graphics
> SRDC Software Development
> _____
> 
> 
>> -Original Message-
>> From: Edward O'Callaghan [mailto:funfunc...@folklore1984.net]
>> Sent: Thursday, February 16, 2017 12:38
>> To: Zhang, Jerry; amd-gfx@lists.freedesktop.org
>> Subject: Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info
>>
>> Hi,
>>
>> Question, is this a bit premature to have a new function and struct for 
>> this, could
>> it just be put in amdgpu_gfx for now or are we expecting amdgpu_gfx_cap to
>> start growing quickly with far more cap state info?
>>
>> Kind Regards,
>> Edward.
>>
>> On 02/16/2017 01:53 PM, Junwei Zhang wrote:
>>> Change-Id: Ibf3e4dbb7deb83271adabc275c9b7a0e0652541a
>>> Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
>>> ---
>>>  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  6 ++
>>>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  2 ++
>>>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c   |  6 ++
>>>  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   |  6 ++
>>>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   | 14 ++
>>>  include/uapi/drm/amdgpu_drm.h   |  1 +
>>>  6 files changed, 35 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index 1ad3f08..cdc2b2a 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -869,6 +869,10 @@ struct amdgpu_gfx_funcs {
>>> void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
>>> uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);  };
>>>
>>> +struct amdgpu_gfx_cap {
>>> +   uint32_t gc_double_offchip_lds_buf;
>>> +};
>>> +
>>>  struct amdgpu_gfx {
>>> struct mutexgpu_clock_mutex;
>>> struct amdgpu_gca_configconfig;
>>> @@ -911,6 +915,8 @@ struct amdgpu_gfx {
>>> /* reset mask */
>>> uint32_tgrbm_soft_reset;
>>> uint32_tsrbm_soft_reset;
>>> +
>>> +   struct amdgpu_gfx_cap   cap;
>>>  };
>>>
>>>  int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> index 7f59608..e7aa382 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> @@ -618,6 +618,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
>> void *data, struct drm_file
>>> cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG;
>>> cap.direct_gma_size = amdgpu_direct_gma_size;
>>> }
>>> +   cap.gc_double_offchip_lds_buf =
>>> +   adev->gfx.cap.gc_double_offchip_lds_buf;
>>> return copy_to_user(out, ,
>>> min((size_t)size, sizeof(cap))) ? -EFAULT : 
>>> 0;
>>> }
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>>> index ce75d46..a1e221b 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>>> @@ -1534,6 +1534,11 @@ static void gfx_v6_0_setup_spi(struct
>> amdgpu_device *adev,
>>> mutex_unlock(>grbm_idx_mutex);
>>>  }
>>>
>>> +static void gfx_v6_0_cap_init(struct amdgpu_device *adev) {
>>> +   adev-

Re: Change queue/pipe split between amdkfd and amdgpu

[Edward O'Callaghan]

On 02/16/2017 03:00 PM, Bridgman, John wrote:
> Any objections to authorizing Oded to post the kfdtest binary he is using to 
> some public place (if not there already) so others (like Andres) can test 
> changes which touch on amdkfd ? 
> 
> We should check it for embarrassing symbols but otherwise it should be OK.

someone was up late for a dead line? lol

> 
> That said, since we are getting perilously close to actually sending dGPU 
> support changes upstream we will need (IMO) to maintain a sanitized source 
> repo for kfdtest as well... sharing the binary just gets us started.
> 

Hi John,

Yes, this is the sort of thing I've been referring to for some time now.
We definitely need some kind of centralized mechanism to test/validate
kfd stuff so if you can get this out that would be great! A binary would
be a start, I am sure we can made do and its certainly better than
nothing, however source much like what happened with UMR would be of
course ideal.

I suggest to you that it would perhaps be good if we could arrange some
kind of IRC meeting regarding kfd? Since it seems there is a bit of
fragmented effort here. I have my own ioctl()'s locally for pinning for
my own project which I am not sure are suitable to just upstream as AMD
has its own take so what should we do? I heard so much about dGPU
support for a couple of years now but only seen bits thrown over the
wall. Can we begin a more serious incremental approach happening ASAP?
I created #amdkfd on freenode some time ago which a couple of interested
academics and users hang.

Kind Regards,
Edward.

> Thanks,
> John
> 
>> -Original Message-
>> From: Oded Gabbay [mailto:oded.gab...@gmail.com]
>> Sent: Friday, February 10, 2017 12:57 PM
>> To: Andres Rodriguez
>> Cc: Kuehling, Felix; Bridgman, John; amd-gfx@lists.freedesktop.org;
>> Deucher, Alexander; Jay Cornwall
>> Subject: Re: Change queue/pipe split between amdkfd and amdgpu
>>
>> I don't have a repo, nor do I have the source code.
>> It is a tool that we developed inside AMD (when I was working there), and
>> after I left AMD I got permission to use the binary for regressions testing.
>>
>> Oded
>>
>> On Fri, Feb 10, 2017 at 6:33 PM, Andres Rodriguez 
>> wrote:
>>> Hey Oded,
>>>
>>> Where can I find a repo with kfdtest?
>>>
>>> I tried looking here bit couldn't find it:
>>>
>>> https://cgit.freedesktop.org/~gabbayo/
>>>
>>> -Andres
>>>
>>>
>>>
>>> On 2017-02-10 05:35 AM, Oded Gabbay wrote:

 So the warning in dmesg is gone of course, but the test (that I
 mentioned in previous email) still fails, and this time it caused the
 kernel to crash. In addition, now other tests fail as well, e.g.
 KFDEventTest.SignalEvent

 I honestly suggest to take some time to debug this patch-set on an
 actual Kaveri machine and then re-send the patches.

 Thanks,
 Oded

 log of crash from KFDQMTest.CreateMultipleCpQueues:

 [  160.900137] kfd: qcm fence wait loop timeout expired [
 160.900143] kfd: the cp might be in an unrecoverable state due to an
 unsuccessful queues preemption [  160.916765] show_signal_msg: 36
 callbacks suppressed [  160.916771] kfdtest[2498]: segfault at
 17f8a ip 7f8ae932ee5d sp 7ffc52219cd0 error 4 in
 libhsakmt-1.so.0.0.1[7f8ae932b000+8000]
 [  163.152229] kfd: qcm fence wait loop timeout expired [
 163.152250] BUG: unable to handle kernel NULL pointer dereference at
 005a [  163.152299] IP:
 kfd_get_process_device_data+0x6/0x30 [amdkfd] [  163.152323] PGD
 2333aa067 [  163.152323] PUD 230f64067 [  163.152335] PMD 0

 [  163.152364] Oops:  [#1] SMP
 [  163.152379] Modules linked in: joydev edac_mce_amd edac_core
 input_leds kvm_amd snd_hda_codec_realtek kvm irqbypass
 snd_hda_codec_generic snd_hda_codec_hdmi snd_hda_intel
>> snd_hda_codec
 crct10dif_pclmul crc32_pclmul ghash_clmulni_intel snd_hda_core
 snd_hwdep pcbc snd_pcm aesni_intel snd_seq_midi snd_seq_midi_event
 snd_rawmidi snd_seq aes_x86_64 crypto_simd snd_seq_device
>> glue_helper
 cryptd snd_timer snd fam15h_power k10temp soundcore i2c_piix4 shpchp
 tpm_infineon mac_hid parport_pc ppdev nfsd auth_rpcgss nfs_acl lockd
 lp grace sunrpc parport autofs4 hid_logitech_hidpp hid_logitech_dj
 hid_generic usbhid hid uas usb_storage amdkfd amd_iommu_v2 radeon
 i2c_algo_bit ttm drm_kms_helper syscopyarea ahci sysfillrect
 sysimgblt libahci fb_sys_fops drm r8169 mii fjes video [  163.152668]
 CPU: 3 PID: 2498 Comm: kfdtest Not tainted 4.10.0-rc5+ #3 [
 163.152695] Hardware name: Gigabyte Technology Co., Ltd. To be filled
 by O.E.M./F2A88XM-D3H, BIOS F5 01/09/2014 [  163.152735] task:
 995e73d16580 task.stack: b41144458000 [  163.152764] RIP:
 0010:kfd_get_process_device_data+0x6/0x30 [amdkfd] [  163.152790]
 RSP: 0018:b4114445bab0 EFLAGS: 00010246 [  163.152812] RAX:
 ffea 

Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info

[Edward O'Callaghan]

Hi,

Question, is this a bit premature to have a new function and struct for
this, could it just be put in amdgpu_gfx for now or are we expecting
amdgpu_gfx_cap to start growing quickly with far more cap state info?

Kind Regards,
Edward.

On 02/16/2017 01:53 PM, Junwei Zhang wrote:
> Change-Id: Ibf3e4dbb7deb83271adabc275c9b7a0e0652541a
> Signed-off-by: Junwei Zhang 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  6 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  2 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c   |  6 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   |  6 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   | 14 ++
>  include/uapi/drm/amdgpu_drm.h   |  1 +
>  6 files changed, 35 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 1ad3f08..cdc2b2a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -869,6 +869,10 @@ struct amdgpu_gfx_funcs {
>   void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 
> uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
>  };
>  
> +struct amdgpu_gfx_cap {
> + uint32_t gc_double_offchip_lds_buf;
> +};
> +
>  struct amdgpu_gfx {
>   struct mutexgpu_clock_mutex;
>   struct amdgpu_gca_configconfig;
> @@ -911,6 +915,8 @@ struct amdgpu_gfx {
>   /* reset mask */
>   uint32_tgrbm_soft_reset;
>   uint32_tsrbm_soft_reset;
> +
> + struct amdgpu_gfx_cap   cap;
>  };
>  
>  int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 7f59608..e7aa382 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -618,6 +618,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
> *data, struct drm_file
>   cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG;
>   cap.direct_gma_size = amdgpu_direct_gma_size;
>   }
> + cap.gc_double_offchip_lds_buf =
> + adev->gfx.cap.gc_double_offchip_lds_buf;
>   return copy_to_user(out, ,
>   min((size_t)size, sizeof(cap))) ? -EFAULT : 
> 0;
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index ce75d46..a1e221b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -1534,6 +1534,11 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device 
> *adev,
>   mutex_unlock(>grbm_idx_mutex);
>  }
>  
> +static void gfx_v6_0_cap_init(struct amdgpu_device *adev)
> +{
> + adev->gfx.cap.gc_double_offchip_lds_buf = 1;
> +}
> +
>  static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
>  {
>   u32 gb_addr_config = 0;
> @@ -1692,6 +1697,7 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device 
> *adev)
>adev->gfx.config.max_cu_per_sh);
>  
>   gfx_v6_0_get_cu_info(adev);
> + gfx_v6_0_cap_init(adev);
>  
>   WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << 
> CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
>  (0x2b << 
> CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index aaf66fe..e1e97ae 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct 
> amdgpu_device *adev)
>   mutex_unlock(>srbm_mutex);
>  }
>  
> +static void gfx_v7_0_cap_init(struct amdgpu_device *adev)
> +{
> + adev->gfx.cap.gc_double_offchip_lds_buf = 1;
> +}
> +
>  /**
>   * gfx_v7_0_gpu_init - setup the 3D engine
>   *
> @@ -1900,6 +1905,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device 
> *adev)
>  
>   gfx_v7_0_setup_rb(adev);
>   gfx_v7_0_get_cu_info(adev);
> + gfx_v7_0_cap_init(adev);
>  
>   /* set HW defaults for 3D engine */
>   WREG32(mmCP_MEQ_THRESHOLDS,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index ce05e38..934fc71 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -3826,6 +3826,19 @@ static void gfx_v8_0_init_compute_vmid(struct 
> amdgpu_device *adev)
>   mutex_unlock(>srbm_mutex);
>  }
>  
> +static void gfx_v8_0_cap_init(struct amdgpu_device *adev)
> +{
> + switch (adev->asic_type) {
> + default:
> + adev->gfx.cap.gc_double_offchip_lds_buf = 1;
> + break;
> + case CHIP_CARRIZO:
> + case CHIP_STONEY:
> + adev->gfx.cap.gc_double_offchip_lds_buf = 0;
> + break;
> + }
> +}
> +
>  static void 

Re: [PATCH] Add GPU_POWER sensors

[Edward O'Callaghan]

Hey Tom,

On 02/11/2017 05:10 AM, Tom St Denis wrote:
> Add the ability to sample GPU_POWER sensors.  Because
> the sensors have a high latency we read them from a background
> thread which means we've added the requirement for pthreads.
> 
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
> ---
>  CMakeLists.txt |  5 ++-
>  README |  6 ++--
>  src/app/top.c  | 88 
> +-
>  src/lib/CMakeLists.txt |  1 +
>  src/lib/read_sensor.c  | 37 +
>  src/umr.h  |  5 +++
>  6 files changed, 123 insertions(+), 19 deletions(-)
>  create mode 100644 src/lib/read_sensor.c
> 
> diff --git a/CMakeLists.txt b/CMakeLists.txt
> index ef78c97ad763..7b771d01919b 100644
> --- a/CMakeLists.txt
> +++ b/CMakeLists.txt
> @@ -19,6 +19,9 @@ add_definitions(-DUMR_BUILD_REV=\"${GIT_REV}\")
>  # Add local repository for FindXXX.cmake modules.
>  SET(CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake_modules/" 
> ${CMAKE_MODULE_PATH})
>  
> +find_package(Threads REQUIRED)
> +include_directories(${THREADS_INCLUDE_DIRS})
Do you need this include_directories() line?

> +
>  find_package(Curses REQUIRED)
>  include_directories(${CURSES_INCLUDE_DIRS})
>  
> @@ -37,7 +40,7 @@ set(REQUIRED_EXTERNAL_LIBS
>  set(CMAKE_POSITION_INDEPENDENT_CODE ON)
>  
>  # CFLAGS += -Wall -W -O2 -g3 -Isrc/ -DPIC -fPIC
> -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -W -O2 -g3")
> +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -pthread -Wall -W -O2 -g3")
You don't really want to have your linkage flags here, I think your
looking for ${CMAKE_THREAD_LIBS_INIT} to go into the
REQUIRED_EXTERNAL_LIBS list.

>  
>  add_subdirectory(src)
>  add_subdirectory(doc)
> diff --git a/README b/README
> index 13cdac663d20..8a8de8485ac7 100644
> --- a/README
> +++ b/README
> @@ -28,9 +28,9 @@ mailing list at:
>  Building
>  -
>  
> -To build umr you will need pciaccess, ncurses, and libdrm headers and
> -libraries.  Which are available in both Fedora and Ubuntu (as well as
> -other distributions).  To build umr:
> +To build umr you will need pciaccess, ncurses, libdrm, and pthread 
> +headers and libraries.  Which are available in both Fedora and Ubuntu 
> +(as well as other distributions).  To build umr:
>  
>  $ mkdir build && cd build/ && cmake ../
>  $ make
> diff --git a/src/app/top.c b/src/app/top.c
> index b081515a5b40..60f629d247f3 100644
> --- a/src/app/top.c
> +++ b/src/app/top.c
> @@ -54,6 +54,7 @@ enum sensor_maps {
>   SENSOR_IDENTITY=0, // x = x
>   SENSOR_D1000,// x = x/1000
>   SENSOR_D100,// x = x/100
> + SENSOR_WATT,
>  };
>  
>  enum sensor_print {
> @@ -61,6 +62,7 @@ enum sensor_print {
>   SENSOR_MHZ,
>   SENSOR_PERCENT,
>   SENSOR_TEMP,
> + SENSOR_POWER,
>  };
>  
>  enum drm_print {
> @@ -171,19 +173,14 @@ static struct umr_bitfield stat_uvd_pgfsm7_bits[] = {
>  static struct umr_bitfield stat_mc_hub_bits[] = {
>{ "OUTSTANDING_READ", 255, 255, _bitfield_default },
>{ "OUTSTANDING_WRITE", 255, 255, _bitfield_default },
> -//{ "OUTSTANDING_ATOMIC", 255, 255, _bitfield_default },
>{ "OUTSTANDING_HUB_RDREQ", 255, 255, _bitfield_default },
>{ "OUTSTANDING_HUB_RDRET", 255, 255, _bitfield_default },
>{ "OUTSTANDING_HUB_WRREQ", 255, 255, _bitfield_default },
>{ "OUTSTANDING_HUB_WRRET", 255, 255, _bitfield_default },
> -//{ "OUTSTANDING_HUB_ATOMIC_REQ", 255, 255, _bitfield_default },
> -//{ "OUTSTANDING_HUB_ATOMIC_RET", 255, 255, _bitfield_default },
>{ "OUTSTANDING_RPB_READ", 255, 255, _bitfield_default },
>{ "OUTSTANDING_RPB_WRITE", 255, 255, _bitfield_default },
> -//{ "OUTSTANDING_RPB_ATOMIC", 255, 255, _bitfield_default },
>{ "OUTSTANDING_MCD_READ", 255, 255, _bitfield_default },
>{ "OUTSTANDING_MCD_WRITE", 255, 255, _bitfield_default },
> -//{ "OUTSTANDING_MCD_ATOMIC", 255, 255, _bitfield_default },
>{ NULL, 0, 0, NULL },
>  };
this hulk seems unrelated to this patch?


With those fixes,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

>  
> @@ -227,6 +224,10 @@ static struct umr_bitfield stat_vi_sensor_bits[] = {
>   { "GFX_MCLK", AMDGPU_PP_SENSOR_GFX_MCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
> _bitfield_default },
>   { "GPU_LOAD", AMDGPU_PP_SENSOR_GPU_LOAD, SENSOR_PERCENT<<4, 
> _bitfield_default },
>   { "GPU_TEMP", AMDGPU_PP

Re: [PATCH] drm/amdgpu: clear framebuffer with GPU

[Edward O'Callaghan]

On 02/08/2017 12:24 PM, Pixel Ding wrote:
> CPU is not efficient to do this job. There's a failure caused by this
> is that handshaking gets timeout of SRIOV virtual function.
Can you fixup the commit message a little but otherwise,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

> 
> Signed-off-by: Pixel Ding <pixel.d...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> index 1e735c4..2867f55 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> @@ -148,7 +148,8 @@ static int amdgpufb_create_pinned_object(struct 
> amdgpu_fbdev *rfbdev,
>   ret = amdgpu_gem_object_create(adev, aligned_size, 0,
>  AMDGPU_GEM_DOMAIN_VRAM,
>  AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
> -AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
> +AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
> +AMDGPU_GEM_CREATE_VRAM_CLEARED,
>  true, );
>   if (ret) {
>   printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
> @@ -242,8 +243,6 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
>   /* setup helper */
>   rfbdev->helper.fb = fb;
>  
> - memset_io(abo->kptr, 0x0, amdgpu_bo_size(abo));
> -
>   strcpy(info->fix.id, "amdgpudrmfb");
>  
>   drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
> 



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Re: [RFC]: More robust build sys for UMR

[Edward O'Callaghan]

On 02/05/2017 10:42 PM, StDenis, Tom wrote:
> Hi Edward,

Hey Tom,

> 
> 
> Well the patches apply and work but I'm not really sure what problem
> it's meant to solve .  Building previously was actually simpler with

So the idea here was to implement something a little more robust and
extensible. For example with a couple of extra lines cmake can produce
rpm's, deb's and tar's too as build by-products. I can add this
functionality if you wish? Additionally another couple of lines a unit
tests could be hooked in if that is useful?

Fundamentally the idea was to have a "proper" build system that can
be extensible enough not to get in the way while the community
elaborates on UMR some more with additional features. I was thinking
about looking at unifying other peoples radeon debug/re tooling together
into UMR to be the one-stop tool as my Sunday afternoon weekend project
you see :) .

> "make" as opposed to "mkdir build && cd build && cmake .. && make".
>

I just added that step because its nice to build out of tree, you don't
have to.

> 
> On a BSD system (where this wouldn't really work without the
> corresponding debugfs entries) gmake could be used to build it provided
> ncurses/pciaccess were around.

Well in truth I didn't test on the BSD's yet, however it helps give some
a good foundation so they could port it should they wish. I am assuming
so since they seem to be updating their graphics stack these days.

> 
> 
> If this legitimately makes it more stable to build on Linux systems then
> I'm all for it.  Can anyone elaborate on where the simple make system
> would fail?

Well I hope so, that's why I RFC it. I expect this to work out the box
on all distributions right off the bat and I would be interested in
feedback for that.

> 
> (I'm not saying NAK I'm simply asking for my own edification).

Sure sure, this only took me a hour to put together because of _my_ itch
so don't stress.

> 
> Thanks,
> Tom

Kind Regards,
Edward.

> 
> 
> *From:* Edward O'Callaghan <funfunc...@folklore1984.net>
> *Sent:* Saturday, February 4, 2017 23:59
> *To:* amd-gfx@lists.freedesktop.org
> *Cc:* StDenis, Tom
> *Subject:* [RFC]: More robust build sys for UMR
>  
> Keeping with the tradition of changing the build system on initial
> release, here we go again.. This follow series introduces the cmake
> build system that is intended to be a little more robust across
> various distros and presumably the BSD's also. The installation
> prefix is configurable in the usual cmake way:
>  `cmake -DCMAKE_INSTALL_PREFIX:PATH=/usr ..`
> 
> Please kindly review,
> 
> Edward O'Callaghan (4):
>  [PATCH 1/4] cmake_modules: Add libpciaccess finder
>  [PATCH 2/4] cmake: Initial build system
>  [PATCH 3/4] README: minor update for cmake buildsys
>  [PATCH 4/4] drop orginal Makefile && stub bin/ directory



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[PATCH 3/4] README: minor update for cmake buildsys

[Edward O'Callaghan]

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 README | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README b/README
index 2700736..7d8b025 100644
--- a/README
+++ b/README
@@ -32,6 +32,7 @@ To build umr you will need pciaccess and ncurses headers and 
libraries.
 Which are available in both Fedora and Ubuntu (as well as other
 distributions).  To build simply invoke the make command
 
+$ mkdir build && cd build/ && cmake ../
 $ make
 
 and then
-- 
2.9.3

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[PATCH 2/4] cmake: Initial build system

[Edward O'Callaghan]

V.2: squash in,
  cmake: Add docs manpage build target
  cmake: Add install targets
  cmake: Misc fixes

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 CMakeLists.txt  | 40 
 doc/CMakeLists.txt  |  3 +++
 src/CMakeLists.txt  |  6 ++
 src/app/CMakeLists.txt  | 24 
 src/lib/CMakeLists.txt  | 28 
 src/lib/asic/CMakeLists.txt | 20 
 src/lib/ip/CMakeLists.txt   | 41 +
 7 files changed, 162 insertions(+)
 create mode 100644 CMakeLists.txt
 create mode 100644 doc/CMakeLists.txt
 create mode 100644 src/CMakeLists.txt
 create mode 100644 src/app/CMakeLists.txt
 create mode 100644 src/lib/CMakeLists.txt
 create mode 100644 src/lib/asic/CMakeLists.txt
 create mode 100644 src/lib/ip/CMakeLists.txt

diff --git a/CMakeLists.txt b/CMakeLists.txt
new file mode 100644
index 000..bef94fd
--- /dev/null
+++ b/CMakeLists.txt
@@ -0,0 +1,40 @@
+# Copyright 2017 Edward O'Callaghan <funfunc...@folklore1984.net>
+
+cmake_minimum_required(VERSION 3.0.1)
+
+project(umr)
+
+SET(MAJOR_VERSION 1)
+SET(MINOR_VERSION 0)
+
+SET(RELEASE_VERSION \"${MAJOR_VERSION}.${MINOR_VERSION}\")
+execute_process(COMMAND  git describe --abbrev=12 --always
+WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
+OUTPUT_STRIP_TRAILING_WHITESPACE
+OUTPUT_VARIABLE GIT_REV
+)
+add_definitions(-DUMR_BUILD_VER=${RELEASE_VERSION})
+add_definitions(-DUMR_BUILD_REV=\"${GIT_REV}\")
+
+# Add local repository for FindXXX.cmake modules.
+SET(CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake_modules/" 
${CMAKE_MODULE_PATH})
+
+find_package(Curses REQUIRED)
+include_directories(${CURSES_INCLUDE_DIRS})
+
+find_package(PCIAccess REQUIRED)
+include_directories(${PCIACCESS_INCLUDE_DIR})
+
+set(REQUIRED_EXTERNAL_LIBS
+  ${CURSES_LIBRARIES}
+  ${PCIACCESS_LIBRARIES}
+)
+
+# Global setting: build everything position independent
+set(CMAKE_POSITION_INDEPENDENT_CODE ON)
+
+# CFLAGS += -Wall -W -O2 -g3 -Isrc/ -DPIC -fPIC
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -W -O2 -g3")
+
+add_subdirectory(src)
+add_subdirectory(doc)
diff --git a/doc/CMakeLists.txt b/doc/CMakeLists.txt
new file mode 100644
index 000..112ad48
--- /dev/null
+++ b/doc/CMakeLists.txt
@@ -0,0 +1,3 @@
+# Copyright 2017 Edward O'Callaghan <funfunc...@folklore1984.net>
+
+install(FILES umr.1 DESTINATION ${CMAKE_INSTALL_PREFIX}/man/man1)
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
new file mode 100644
index 000..e9eaeeb
--- /dev/null
+++ b/src/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2017 Edward O'Callaghan <funfunc...@folklore1984.net>
+
+include_directories(${CMAKE_CURRENT_SOURCE_DIR}/)
+
+add_subdirectory(lib)
+add_subdirectory(app)
diff --git a/src/app/CMakeLists.txt b/src/app/CMakeLists.txt
new file mode 100644
index 000..117d3f1
--- /dev/null
+++ b/src/app/CMakeLists.txt
@@ -0,0 +1,24 @@
+# Copyright 2017 Edward O'Callaghan <funfunc...@folklore1984.net>
+
+project(umr)
+
+#application objects
+add_library(umrapp
+  print.c
+  print_config.c
+  ring_read.c
+  scan.c
+  scan_log.c
+  top.c
+  umr_lookup.c
+  set_bit.c
+  set_reg.c
+  print_waves.c
+  enum.c
+)
+
+add_executable(umr main.c)
+target_link_libraries(umr umrapp)
+target_link_libraries(umr umrcore)
+
+install(TARGETS umr DESTINATION bin)
diff --git a/src/lib/CMakeLists.txt b/src/lib/CMakeLists.txt
new file mode 100644
index 000..46c75d6
--- /dev/null
+++ b/src/lib/CMakeLists.txt
@@ -0,0 +1,28 @@
+# Copyright 2017 Edward O'Callaghan <funfunc...@folklore1984.net>
+
+add_subdirectory(asic)
+add_subdirectory(ip)
+
+add_library(umrcore STATIC
+  bitfield_print.c
+  close_asic.c
+  create_asic_helper.c
+  discover_by_did.c
+  discover_by_name.c
+  discover.c
+  dump_ib.c
+  find_reg.c
+  mmio.c
+  query_drm.c
+  read_sgpr.c
+  read_vram.c
+  ring_decode.c
+  scan_config.c
+  wave_status.c
+  create_mmio_accel.c
+  $ $
+)
+
+target_link_libraries(umrcore ${REQUIRED_EXTERNAL_LIBS})
+
+install(TARGETS umrcore DESTINATION lib)
diff --git a/src/lib/asic/CMakeLists.txt b/src/lib/asic/CMakeLists.txt
new file mode 100644
index 000..6cfec30
--- /dev/null
+++ b/src/lib/asic/CMakeLists.txt
@@ -0,0 +1,20 @@
+# Copyright 2017 Edward O'Callaghan <funfunc...@folklore1984.net>
+
+#library objects (ASICs blocks)
+add_library(asic OBJECT
+  bonaire.c
+  carrizo.c
+  fiji.c
+  hainan.c
+  kaveri.c
+  oland.c
+  pitcairn.c
+  polaris10.c
+  polaris11.c
+  polaris12.c
+  stoney.c
+  tahiti.c
+  tonga.c
+  topaz.c
+  verde.c
+)
diff --git a/src/lib/ip/CMakeLists.txt b/src/lib/ip/CMakeLists.txt
new file mode 100644
index 000..2c2fe68
--- /dev/null
+++ b/src/lib/ip/CMakeLists.txt
@@ -0,0 +1,41 @@
+# Copyright 2017 Edward O'Callaghan <funfunc...@folklore1984.net>
+
+add_library(ip OBJECT
+  bif30.c
+  bif41.c
+  bif50.c
+  bif51.c
+  dce100.c
+

[PATCH 4/4] drop orginal Makefile && stub bin/ directory

[Edward O'Callaghan]

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 Makefile  | 80 ---
 bin/.keep |  0
 2 files changed, 80 deletions(-)
 delete mode 100644 Makefile
 delete mode 100644 bin/.keep

diff --git a/Makefile b/Makefile
deleted file mode 100644
index 5c47832..000
--- a/Makefile
+++ /dev/null
@@ -1,80 +0,0 @@
-LIBNAME=bin/libumr.a
-BINNAME=bin/umr
-
-CFLAGS += -Wall -W -O2 -g3 -Isrc/ -DPIC -fPIC
-
-REV=$(shell git rev-parse HEAD | cut -b1-12)
-VER_MAJOR=1
-VER_MINOR=0
-CFLAGS+=-DUMR_BUILD_REV=\"${REV}\" 
-DUMR_BUILD_VER=\"${VER_MAJOR}.${VER_MINOR}\"
-
-
-PREFIX ?= /usr/local/
-
-#library objects (ASICs blocks)
-LIBOBJS=\
-src/lib/asic/bonaire.o src/lib/asic/carrizo.o src/lib/asic/fiji.o \
-src/lib/asic/hainan.o src/lib/asic/kaveri.o src/lib/asic/oland.o \
-src/lib/asic/pitcairn.o src/lib/asic/polaris10.o src/lib/asic/polaris11.o \
-src/lib/asic/polaris12.o src/lib/asic/stoney.o src/lib/asic/tahiti.o \
-src/lib/asic/tonga.o src/lib/asic/topaz.o src/lib/asic/verde.o \
-\
-src/lib/bitfield_print.o src/lib/close_asic.o src/lib/create_asic_helper.o \
-src/lib/discover_by_did.o src/lib/discover_by_name.o src/lib/discover.o 
src/lib/dump_ib.o \
-src/lib/find_reg.o src/lib/mmio.o src/lib/query_drm.o \
-src/lib/read_sgpr.o src/lib/read_vram.o src/lib/ring_decode.o 
src/lib/scan_config.o \
-src/lib/wave_status.o src/lib/create_mmio_accel.o \
-\
-src/lib/ip/bif30.o src/lib/ip/bif41.o src/lib/ip/bif50.o src/lib/ip/bif51.o \
-\
-src/lib/ip/dce100.o src/lib/ip/dce110.o src/lib/ip/dce112.o src/lib/ip/dce60.o 
\
-src/lib/ip/dce80.o \
-\
-src/lib/ip/gfx60.o src/lib/ip/gfx70.o src/lib/ip/gfx72.o src/lib/ip/gfx80.o \
-src/lib/ip/gfx81.o \
-\
-src/lib/ip/gmc60.o src/lib/ip/gmc70.o src/lib/ip/gmc71.o src/lib/ip/gmc81.o \
-src/lib/ip/gmc82.o \
-\
-src/lib/ip/oss10.o src/lib/ip/oss20.o src/lib/ip/oss30.o \
-\
-src/lib/ip/smu60.o src/lib/ip/smu700.o src/lib/ip/smu701.o src/lib/ip/smu710.o 
\
-src/lib/ip/smu711.o src/lib/ip/smu712.o src/lib/ip/smu713.o src/lib/ip/smu80.o 
\
-\
-src/lib/ip/uvd40.o src/lib/ip/uvd42.o src/lib/ip/uvd5.o src/lib/ip/uvd6.o \
-\
-src/lib/ip/vce1.o src/lib/ip/vce2.o src/lib/ip/vce3.o
-
-
-#application objects
-APPOBJS=src/app/main.o src/app/print.o src/app/print_config.o \
-src/app/ring_read.o src/app/scan.o src/app/scan_log.o \
-src/app/top.o src/app/umr_lookup.o src/app/set_bit.o src/app/set_reg.o 
src/app/print_waves.o \
-src/app/enum.o
-
-${BINNAME}: ${LIBNAME} ${APPOBJS}
-   ${CC} ${CFLAGS} ${APPOBJS} ${LIBNAME} -lpciaccess -lncurses -o $@
-
-${LIBOBJS}: src/umr.h
-${APPOBJS}: src/umr.h
-
-${LIBNAME}: ${LIBOBJS}
-   ${AR} ${ARFLAGS} $@ $^
-
-.PHONY: install
-install: bin/umr
-   mkdir -p ${PREFIX}/bin
-   mkdir -p ${PREFIX}/share/man/man1
-   install ${BINNAME} ${PREFIX}/bin/
-   install doc/umr.1 ${PREFIX}/share/man/man1/
-
-.PHONY: installlib
-installlib: ${LIBOBJS}
-   mkdir -p ${PREFIX}/include
-   mkdir -p ${PREFIX}/lib
-   install src/*.h ${PREFIX}/include/
-   install ${LIBNAME} ${PREFIX}/lib/
-
-.PHONY: clean
-clean:
-   rm -f bin/umr ${LIBNAME} ${LIBOBJS} ${APPOBJS}
diff --git a/bin/.keep b/bin/.keep
deleted file mode 100644
index e69de29..000
-- 
2.9.3

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[RFC]: More robust build sys for UMR

[Edward O'Callaghan]

Keeping with the tradition of changing the build system on initial
release, here we go again.. This follow series introduces the cmake
build system that is intended to be a little more robust across
various distros and presumably the BSD's also. The installation
prefix is configurable in the usual cmake way:
 `cmake -DCMAKE_INSTALL_PREFIX:PATH=/usr ..`

Please kindly review,

Edward O'Callaghan (4):
 [PATCH 1/4] cmake_modules: Add libpciaccess finder
 [PATCH 2/4] cmake: Initial build system
 [PATCH 3/4] README: minor update for cmake buildsys
 [PATCH 4/4] drop orginal Makefile && stub bin/ directory
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[PATCH 1/4] cmake_modules: Add libpciaccess finder

[Edward O'Callaghan]

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 cmake_modules/FindPCIAccess.cmake | 35 +++
 1 file changed, 35 insertions(+)
 create mode 100644 cmake_modules/FindPCIAccess.cmake

diff --git a/cmake_modules/FindPCIAccess.cmake 
b/cmake_modules/FindPCIAccess.cmake
new file mode 100644
index 000..09ddd51
--- /dev/null
+++ b/cmake_modules/FindPCIAccess.cmake
@@ -0,0 +1,35 @@
+# Try to find pciaccess
+#
+# Once done, this will define
+#
+# PCIACCESS_FOUND
+# PCIACCESS_INCLUDE_DIR
+# PCIACCESS_LIBRARIES
+
+find_package(PkgConfig)
+
+pkg_check_modules(PC_PCIACCESS QUIET pciaccess)
+
+find_path(PCIACCESS_INCLUDE_DIR NAMES pciaccess.h
+HINTS
+${PC_PCIACCESS_INCLUDEDIR}
+${PC_PCIACCESS_INCLUDE_DIRS}
+/usr/include
+)
+
+find_library(PCIACCESS_LIBRARY NAMES pciaccess
+HINTS
+${PC_PCIACCESS_LIBDIR}
+${PC_PCIACCESS_LIBRARY_DIRS}
+/usr/lib64
+/usr/lib
+)
+
+SET(PCIACCESS_LIBRARIES optimized ${PCIACCESS_LIBRARY})
+
+include(FindPackageHandleStandardArgs)
+find_package_handle_standard_args(PCIACCESS DEFAULT_MSG
+   PCIACCESS_LIBRARIES PCIACCESS_INCLUDE_DIR
+)
+
+mark_as_advanced(PCIACCESS_INCLUDE_DIR PCIACCESS_LIBRARIES)
-- 
2.9.3

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Re: [PATCH v5 0/3] Allow ASYNC flip with atomic helpers.

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 02/04/2017 04:46 AM, Alex Deucher wrote:
> On Thu, Feb 2, 2017 at 4:56 PM, Andrey Grodzovsky
> <andrey.grodzov...@amd.com> wrote:
>> This series is a folow-up on
>> https://patchwork.kernel.org/patch/9501787/
>>
>> The first patch makes changes to atomic helpers to allow for drives with 
>> ASYNC flip support to use them.
>> Patch 2 is to use this in AMDGPU/DC.
>> Patch 3 is possible cleanup in nouveau/kms who seems to have to duplicate 
>> the helper as we did to support ASYNC flips.
>>
>> v2:
>> Resend drm/atomic: Save flip flags in drm_plane_state since the original 
>> patch was incomplete.
>> Squash 2 AMD changes into one to not break compilation.
>>
>> v3:
>> Following Daniel's comments, save flip flags in crtc_state instead of 
>> plane_state.
>>
>> v4:
>> Lauren's comment, reset flp flags before using again.
>> Harry's comment, fix identation in amd/display.
>>
>> v5:
>> Rename the flag, fix typo in header.
> 
> Looks good.  The series is:
> Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> Unless there are any objections I'll push to drm-misc today.
> 
> Thanks!
> 
> Alex
> 
>>
>> Andrey Grodzovsky (3):
>>   drm/atomic: Save flip flags in drm_crtc_state
>>   drm/nouveau/kms/nv50: Switch to using atomic helper for flip.
>>   drm/amd/display: Switch to using atomic_helper for flip.
>>
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h   |   1 -
>>  .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 113 
>> +
>>  drivers/gpu/drm/drm_atomic_helper.c|  20 ++--
>>  drivers/gpu/drm/nouveau/nv50_display.c |  84 ++-
>>  include/drm/drm_crtc.h |   9 +-
>>  5 files changed, 48 insertions(+), 179 deletions(-)
>>
>> --
>> 1.9.1
>>
>> ___
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH libdrm 0/3] some -pro patches for integration

[Edward O'Callaghan]

This series is,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 01/29/2017 06:49 AM, Grazvydas Ignotas wrote:
> I've taken several patches from amdgpu-pro libdrm that look useful
> to me and I think can be applied already. The only things I did was
> rebasing, fixing some typos and dropping Change-Id.
> 
> Alex Xie (3):
>   amdgpu: Free/uninit vamgr_32 in theoretically correct order
>   amdgpu: vamgr can be a struct instead of a pointer
>   amdgpu: vamgr_32 can be a struct instead of a pointer
> 
>  amdgpu/amdgpu_device.c   | 24 +++-
>  amdgpu/amdgpu_internal.h |  4 ++--
>  amdgpu/amdgpu_vamgr.c|  6 +++---
>  3 files changed, 12 insertions(+), 22 deletions(-)
> 



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Re: [PATCH v2 0/3] Allow ASYNC flip with atomic helpers.

[Edward O'Callaghan]

This series is,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 01/17/2017 04:16 PM, Andrey Grodzovsky wrote:
> This series is a folow-up on
> https://patchwork.kernel.org/patch/9501787/
> 
> The first patch makes changes to atomic helpers to allow for 
> drives with ASYNC flip support to use them.
> Patch 2 is to use this in AMDGPU/DC.
> Patch 3 is possible cleanup in nouveau/kms who seems to have to duplicate 
> the helper as we did to support ASYNC flips. 
> 
> v2: 
> Resend drm/atomic: Save flip flags in drm_plane_state since
> the original patch was incomplete.
> Squash 2 AMD changes into one to not break compilation.
> 
> Andrey Grodzovsky (3):
>   drm/atomic: Save flip flags in drm_plane_state
>   drm/amd/display: Switch to using atomic_helper for flip.
>   drm/nouveau/kms/nv50: Switch to using atomic helper for flip.
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h   |  1 -
>  .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 92 
> ++
>  drivers/gpu/drm/drm_atomic_helper.c| 18 ++---
>  drivers/gpu/drm/nouveau/nv50_display.c | 77 ++
>  include/drm/drm_plane.h|  8 ++
>  5 files changed, 24 insertions(+), 172 deletions(-)
> 



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Re: More specific libdrm error message

[Edward O'Callaghan]

Hi Xie,

Perhaps you want to use `fprintf(stderr, "...")` over `printf("..")` and
lose the space before the start parenthesis. Also, line wrap
your commit message.

Side note, use git send-email so that the patch is inline and not a HTML
email for easy review and application of the patch.

Kind Regards,
Edward.

On 01/12/2017 08:49 AM, Xie, AlexBin wrote:
> Hi,
> 
> 
> v2: Use strerror instead of %m. %m is a GNU C Library extension.
> 
> Thanks,
> 
> Alex Bin Xie
> 
> 
> 
> *From:* Xie, AlexBin
> *Sent:* Wednesday, January 11, 2017 4:14 PM
> *To:* amd-gfx@lists.freedesktop.org
> *Subject:* More specific libdrm error message
>  
> Hi,
> 
> Provide more specific error message if non-privileged user runs amdgpu_test
> 
> Before this change, the error message is:" WARNING - Suite
> initialization failed..." People might think this is a driver problem.
> 
> 
> Tested with non-privileged user. Now the error message is like.
> 
> ...
> Error:Permission denied. Hint: Try to run this test program as root.
> WARNING - Suite initialization failed for 'Basic Tests'.
> 
> ...
> 
> 
> 
> Tested as root with no regression.
> 
> 
> 
> Please review.
> 
> 
> Thanks,
> 
> Alex Bin Xie
> 
> 
> 
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Re: [PATCH 0/2] drm/amd/amdgpu: locking fixes

[Edward O'Callaghan]

this series is,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 01/11/2017 06:31 PM, Nicolai Hähnle wrote:
> Hi all,
> 
> two fixes for locking issues that I noticed.
> 
> The first one is something that I actually encountered live; it probably
> only matters when lock debugging is enabled, but obviously needs to be fixed
> anyway.
> 
> The second one I only noticed upon reading the code -- I haven't seen it
> fail live yet, at least not with lock debugging enabled (who knows what its
> effects could be without lock debugging).
> 
> Please review!
> 
> I noticed two more locking-related problems, but since I'm not sure whether
> I'll get to those this week, I'm sending out these two patches already. The
> other two problems are (both of them probably mostly benign, but I did
> encounter them in live tests):
> 
> 1. amdgpu_bo_create_restricted(resv == NULL) --> ttm_bo_init will free a
>reservation object while it is locked. Fixing this soundly probably
>requires mild changes to the ttm_bo_init API (perhaps a separate
>ttm_bo_init_locked?).
> 
> 2. ttm_bo_pipeline_move will ttm_bo_unref(_obj) leading to
>mutex_destroy(_obj->wu_mutex) while that mutex "looks" locked (due
>to the dumb copy).
> 
> Thanks,
> Nicolai
> 
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Re: [PATCH] drm/amd/display: drop min/max wrappers

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 01/10/2017 09:35 AM, Dave Airlie wrote:
> From: Dave Airlie <airl...@redhat.com>
> 
> These aren't needed, and aren't really used in too many places.
> 
> Signed-off-by: Dave Airlie <airl...@redhat.com>
> ---
>  drivers/gpu/drm/amd/display/dc/core/dc.c| 2 +-
>  drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 4 ++--
>  drivers/gpu/drm/amd/display/dc/os_types.h   | 2 --
>  3 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index 69819d8..763d1e3 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -628,7 +628,7 @@ struct dc *dc_create(const struct dc_init_data 
> *init_params)
>   full_pipe_count = core_dc->res_pool->pipe_count;
>   if (core_dc->res_pool->underlay_pipe_index >= 0)
>   full_pipe_count--;
> - core_dc->public.caps.max_targets = dm_min(
> + core_dc->public.caps.max_targets = min(
>   full_pipe_count,
>   core_dc->res_pool->stream_enc_count);
>  
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c 
> b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
> index 2626120..dd922bd 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
> @@ -289,7 +289,7 @@ static void dce_set_clock(
>  
>   /* Make sure requested clock isn't lower than minimum threshold*/
>   if (requested_clk_khz > 0)
> - requested_clk_khz = dm_max(requested_clk_khz,
> + requested_clk_khz = max(requested_clk_khz,
>   clk_dce->dentist_vco_freq_khz / 64);
>  
>   /* Prepare to program display clock*/
> @@ -364,7 +364,7 @@ static void dce112_set_clock(
>  
>   /* Make sure requested clock isn't lower than minimum threshold*/
>   if (requested_clk_khz > 0)
> - requested_clk_khz = dm_max(requested_clk_khz,
> + requested_clk_khz = max(requested_clk_khz,
>   clk_dce->dentist_vco_freq_khz / 62);
>  
>   dce_clk_params.target_clock_frequency = requested_clk_khz;
> diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h 
> b/drivers/gpu/drm/amd/display/dc/os_types.h
> index 7f0c282..27ed2a6 100644
> --- a/drivers/gpu/drm/amd/display/dc/os_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/os_types.h
> @@ -52,8 +52,6 @@
>  
>  #define dm_vlog(fmt, args) vprintk(fmt, args)
>  
> -#define dm_min(x, y) min(x, y)
> -#define dm_max(x, y) max(x, y)
>  #endif
>  
>  
> 



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Re: [PATCH] drm/amd/display: start using linux hdmi header

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 01/10/2017 10:33 AM, Dave Airlie wrote:
> From: Dave Airlie <airl...@redhat.com>
> 
> DAL has defines for things, and it doesn't even use them itself.
> 
> Signed-off-by: Dave Airlie <airl...@redhat.com>
> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 18 --
>  .../gpu/drm/amd/display/include/set_mode_types.h   | 22 
> +-
>  2 files changed, 9 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index 2b08f5a..0f8bb6e 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -1333,13 +1333,12 @@ static void set_avi_info_frame(
>  
>   /* Initialize header */
>   info_frame.avi_info_packet.info_packet_hdmi.bits.header.
> - info_frame_type = INFO_FRAME_AVI;
> + info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
>   /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
>   * not be used in HDMI 2.0 (Section 10.1) */
> - info_frame.avi_info_packet.info_packet_hdmi.bits.header.version =
> - INFO_FRAME_VERSION_2;
> + info_frame.avi_info_packet.info_packet_hdmi.bits.header.version = 2;
>   info_frame.avi_info_packet.info_packet_hdmi.bits.header.length =
> - INFO_FRAME_SIZE_AVI;
> + HDMI_AVI_INFOFRAME_SIZE;
>  
>   /*
>* IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
> @@ -1472,10 +1471,9 @@ static void set_avi_info_frame(
>   check_sum =
>   _frame.
>   avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
> - *check_sum = INFO_FRAME_AVI + INFO_FRAME_SIZE_AVI
> - + INFO_FRAME_VERSION_2;
> + *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
>  
> - for (byte_index = 1; byte_index <= INFO_FRAME_SIZE_AVI; byte_index++)
> + for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; 
> byte_index++)
>   *check_sum += info_frame.avi_info_packet.info_packet_hdmi.
>   packet_raw_data.sb[byte_index];
>  
> @@ -1586,7 +1584,7 @@ static void set_vendor_info_packet(struct core_stream 
> *stream,
>   info_packet->sb[5] = stream->public.timing.hdmi_vic;
>  
>   /* Header */
> - info_packet->hb0 = 0x81; /* VSIF packet type. */
> + info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
>   info_packet->hb1 = 0x01; /* Version */
>  
>   /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
> @@ -1627,7 +1625,7 @@ static void set_spd_info_packet(struct core_stream 
> *stream,
>   /* HB0  = Packet Type = 0x83 (Source Product
>*Descriptor InfoFrame)
>*/
> - info_packet->hb0 = 0x83;
> + info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
>  
>   /* HB1  = Version = 0x01 */
>   info_packet->hb1 = 0x01;
> @@ -1649,7 +1647,7 @@ static void set_spd_info_packet(struct core_stream 
> *stream,
>   /* HB1  = Packet Type = 0x83 (Source Product
>*Descriptor InfoFrame)
>*/
> - info_packet->hb1 = 0x83;
> + info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
>  
>   /* HB2  = [Bits 7:0 = Least significant eight bits -
>*For INFOFRAME, the value must be 1Bh]
> diff --git a/drivers/gpu/drm/amd/display/include/set_mode_types.h 
> b/drivers/gpu/drm/amd/display/include/set_mode_types.h
> index d18210f..fee2b6f 100644
> --- a/drivers/gpu/drm/amd/display/include/set_mode_types.h
> +++ b/drivers/gpu/drm/amd/display/include/set_mode_types.h
> @@ -27,6 +27,7 @@
>  #define __DAL_SET_MODE_TYPES_H__
>  
>  #include "dc_types.h"
> +#include 
>  
>  /* Info frame packet status */
>  enum info_frame_flag {
> @@ -36,27 +37,6 @@ enum info_frame_flag {
>   INFO_PACKET_PACKET_UPDATE_SCAN_TYPE = 8
>  };
>  
> -/* Info frame types */
> -enum info_frame_type {
> - INFO_FRAME_GAMUT = 0x0A,
> - INFO_FRAME_VENDOR_INFO = 0x81,
> - INFO_FRAME_AVI = 0x82
> -};
> -
> -/* Info frame versions */
> -enum info_frame_version {
> - INFO_FRAME_VERSION_1 = 1,
> - INFO_FRAME_VERSION_2 = 2,
> - INFO_FRAME_VERSION_3 = 3
> -};
> -
> -/* Info frame size */
> -enum info_frame_size {
> - INFO_FRAME_SIZE_AVI = 13,
> - INFO_FRAME_SIZE_VENDOR = 25,
> - INFO_FRAME_SIZE_AUDIO = 10
> -};
> -
>  struct hdmi_info_frame_header {
>   uint8_t info_frame_type;
>   uint8_t version;
> 



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Re: [PATCH 01/10] drm/radeon/si: load special ucode for certain MC configs

[Edward O'Callaghan]

On 01/06/2017 05:10 AM, Alex Deucher wrote:
> Required for certain MC configs.
> 
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
>  drivers/gpu/drm/radeon/si.c | 11 ++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
> index ad4d7b8..bbc239e 100644
> --- a/drivers/gpu/drm/radeon/si.c
> +++ b/drivers/gpu/drm/radeon/si.c
> @@ -116,6 +116,8 @@ MODULE_FIRMWARE("radeon/hainan_rlc.bin");
>  MODULE_FIRMWARE("radeon/hainan_smc.bin");
>  MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
>  
> +MODULE_FIRMWARE("radeon/si58_mc.bin");
> +
>  static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 
> sh);
>  static void si_pcie_gen3_enable(struct radeon_device *rdev);
>  static void si_program_aspm(struct radeon_device *rdev);
> @@ -1651,6 +1653,7 @@ static int si_init_microcode(struct radeon_device *rdev)
>   int err;
>   int new_fw = 0;
>   bool new_smc = false;
> + bool si58_fw = false;
>  
>   DRM_DEBUG("\n");
>  
> @@ -1746,6 +1749,9 @@ static int si_init_microcode(struct radeon_device *rdev)
>   default: BUG();
>   }
>  

Hi Alex,

I suggest just a short one line comment above here and also in the
amdgpu patch too explaining what a 'si58_fw' actually means for a
non-AMD eng.

With that this series is,
Acked-by: Edward O'Callaghan <funfunc...@folklore1984.net>

> + if (((RREG32(MC_SEQ_MISC0) & 0xff00) >> 24) == 0x58)
> + si58_fw = true;
> +
>   DRM_INFO("Loading %s Microcode\n", new_chip_name);
>  
>   snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", new_chip_name);
> @@ -1849,7 +1855,10 @@ static int si_init_microcode(struct radeon_device 
> *rdev)
>   }
>   }
>  
> - snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", new_chip_name);
> + if (si58_fw)
> + snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
> + else
> + snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", 
> new_chip_name);
>   err = request_firmware(>mc_fw, fw_name, rdev->dev);
>   if (err) {
>   snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", 
> chip_name);
> 



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Re: [PATCH] drm/amd/amdgpu: fix spelling mistake: "comleted" -> "completed"

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 12/30/2016 12:39 PM, Zhou, David(ChunMing) wrote:
> +amd-gfx, patch is Reviewed-by: Chunming Zhou <david1.z...@amd.com>
> 
> -Original Message-
> From: Colin King [mailto:colin.k...@canonical.com] 
> Sent: Thursday, December 29, 2016 11:47 PM
> To: Deucher, Alexander <alexander.deuc...@amd.com>; Koenig, Christian 
> <christian.koe...@amd.com>; David Airlie <airl...@linux.ie>; Zhou, 
> David(ChunMing) <david1.z...@amd.com>; StDenis, Tom <tom.stde...@amd.com>; 
> Liu, Monk <monk@amd.com>; dri-de...@lists.freedesktop.org
> Cc: linux-ker...@vger.kernel.org
> Subject: [PATCH] drm/amd/amdgpu: fix spelling mistake: "comleted" -> 
> "completed"
> 
> From: Colin Ian King <colin.k...@canonical.com>
> 
> trivial fix to spelling mistake in WARN message
> 
> Signed-off-by: Colin Ian King <colin.k...@canonical.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 60bd4af..9ca3167 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2335,7 +2335,7 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
>   if (fence) {
>   r = dma_fence_wait(fence, false);
>   if (r) {
> - WARN(r, "recovery from shadow 
> isn't comleted\n");
> + WARN(r, "recovery from shadow 
> isn't completed\n");
>   break;
>   }
>   }
> @@ -2347,7 +2347,7 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
>   if (fence) {
>   r = dma_fence_wait(fence, false);
>   if (r)
> - WARN(r, "recovery from shadow isn't 
> comleted\n");
> + WARN(r, "recovery from shadow isn't 
> completed\n");
>   }
>   dma_fence_put(fence);
>   }
> 



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Re: [PATCH v2 0/6] drm/amd/powerplay: refine pr_* prints for powerplay

[Edward O'Callaghan]

Merry Christmas Huang Rui,

This set looks way better and a much more complete solution, good job
working though it all!

Patches 1-6 are,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

Kindest Regards,
Edward.

On 12/26/2016 06:56 PM, Huang Rui wrote:
> From: Huang Rui <ray.hu...@amd.com>
> 
> Hi all,
> 
> Merry Christmas! No one generate patches at this time except us :-).
> 
> The following patch set doesn't have any function change, just refine
> prints of powerplay. Powerplay will used pr_* instead of raw printk,
> and we can dynamic change the debug level with it.
> 
> The prefix is like below:
> 
> [  xxx.xx] amdgpu: [powerplay] ...
> 
> Best Wishes,
> Rui
> 
> Huang Rui (6):
>   drm/amd/powerplay: add prefix for all powerplay pr_* prints
>   drm/amd/powerplay: reshuffle headers to make pr_fmt macro before
> 
>   drm/amd/powerplay: refine print message for amd_powerplay
>   drm/amd/powerplay: update all printk to pr_* on eventmgr
>   drm/amd/powerplay: update all printk to pr_* on hwmgr
>   drm/amd/powerplay: update all printk to pr_* on smumgr
> 
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 50 
> +++---
>  drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 29 ++---
>  .../gpu/drm/amd/powerplay/hwmgr/functiontables.c   | 14 +++---
>  .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 11 ++---
>  drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c   |  8 ++--
>  .../amd/powerplay/hwmgr/process_pptables_v1_0.c|  6 +--
>  .../gpu/drm/amd/powerplay/hwmgr/processpptables.c  |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 28 ++--
>  .../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c   |  4 +-
>  drivers/gpu/drm/amd/powerplay/inc/pp_debug.h   | 10 -
>  drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c   | 28 ++--
>  drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c|  6 +--
>  drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 10 ++---
>  drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c | 10 ++---
>  .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c  |  4 +-
>  .../gpu/drm/amd/powerplay/smumgr/polaris10_smc.c   |  6 +--
>  .../drm/amd/powerplay/smumgr/polaris10_smumgr.c| 10 ++---
>  drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 14 +++---
>  drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c   | 16 +++
>  .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c|  4 +-
>  22 files changed, 140 insertions(+), 134 deletions(-)
> 



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Re: [PATCH 1/2] drm/amd/powerplay: add prefix for all powerplay pr_* prints

[Edward O'Callaghan]

On 12/23/2016 08:54 PM, Huang Rui wrote:
> On Fri, Dec 23, 2016 at 05:32:58PM +0800, Edward O'Callaghan wrote:
>> Hi,
>>
>> I would say drop all the header relocation churn, it distracts away from
>> the functional changes in this commit. Also see inline comments.
>>
> 
> Yes, if double check undef, it needn't move macro before 

If you want to reshuffle headers I would say that is a seperate patch
and the functional changes as their own changeset. That's my view any way.

> 
>> With those fixes,
>> Acked-by: Edward O'Callaghan <funfunc...@folklore1984.net>
>>
>> Kindest Regards,
>> Edward.
>>
>> On 12/23/2016 01:45 PM, Huang Rui wrote:
>>> Powerplay will be used them instead of raw printk, and we can dynamic
>>> change the debug level with it.
>>>
>>> The prefix is like below:
>>>
>>> [  197.755167] [powerplay] amdgpu: powerplay initialized
>>
>> Ideally I think it would be better to look like this:
>>
>> [  xxx.xx ] amdgpu: [powerplay] initialized.
>>
>> but certainly drop repeating "powerplay" twice..
>>
> 
> We define it as below: 
> 
> #define pr_fmt(fmt) "amdgpu: [powerplay] " fmt
> 
> But we need refine most detail prints message with more patches in the
> codes.

I suggest if your going to touch it you may as well go all the way and
get the thing fixed up properly, then its done.

> 
>>>
>>> Suggested-by: Grazvydas Ignotas <nota...@gmail.com>
>>> Signed-off-by: Huang Rui <ray.hu...@amd.com>
>>> Cc: Arindam Nath <arindam.n...@amd.com>
>>> ---
>>>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c   |  2 +-
>>>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c  |  3 +--
>>>  drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c   |  2 +-
>>>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c |  3 ++-
>>>  drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c|  2 +-
>>>  drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c |  2 +-
>>>  drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c   |  2 +-
>>>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c|  2 +-
>>>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c|  2 +-
>>>  drivers/gpu/drm/amd/powerplay/inc/pp_debug.h| 10 --
>>>  drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c |  2 +-
>>>  drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c  |  2 +-
>>>  drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c  |  2 +-
>>>  drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c   |  2 +-
>>>  drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c|  2 +-
>>>  drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c |  2 +-
>>>  drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c  |  2 +-
>>>  drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c|  2 +-
>>>  drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c |  2 +-
>>>  19 files changed, 27 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
>>> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> index cc72190..8b85153 100644
>>> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> @@ -20,6 +20,7 @@
>>>   * OTHER DEALINGS IN THE SOFTWARE.
>>>   *
>>>   */
>>> +#include "pp_debug.h"
>>>  #include 
>>>  #include 
>>>  #include 
>>> @@ -29,7 +30,6 @@
>>>  #include "pp_instance.h"
>>>  #include "power_state.h"
>>>  #include "eventmanager.h"
>>> -#include "pp_debug.h"
>>>  
>>>  
>>>  #define PP_CHECK(handle)   \
>>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
>>> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>>> index 74dbbd1..d043337 100644
>>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>>> @@ -20,13 +20,13 @@
>>>   * OTHER DEALINGS IN THE SOFTWARE.
>>>   *
>>>   */
>>> +#include "pp_debug.h"
>>>  #include 
>>>  #include 
>>>  #include 
>>>  #include "atom-types.h"
>>>  #include "atombios.h"
>>>  #include "processpptables.h"
>&

Re: [PATCH 1/2] drm/amd/powerplay: add prefix for all powerplay pr_* prints

[Edward O'Callaghan]

Hi,

I would say drop all the header relocation churn, it distracts away from
the functional changes in this commit. Also see inline comments.

With those fixes,
Acked-by: Edward O'Callaghan <funfunc...@folklore1984.net>

Kindest Regards,
Edward.

On 12/23/2016 01:45 PM, Huang Rui wrote:
> Powerplay will be used them instead of raw printk, and we can dynamic
> change the debug level with it.
> 
> The prefix is like below:
> 
> [  197.755167] [powerplay] amdgpu: powerplay initialized

Ideally I think it would be better to look like this:

[  xxx.xx ] amdgpu: [powerplay] initialized.

but certainly drop repeating "powerplay" twice..

> 
> Suggested-by: Grazvydas Ignotas <nota...@gmail.com>
> Signed-off-by: Huang Rui <ray.hu...@amd.com>
> Cc: Arindam Nath <arindam.n...@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c   |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c  |  3 +--
>  drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c   |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c |  3 ++-
>  drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c|  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c   |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c|  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c|  2 +-
>  drivers/gpu/drm/amd/powerplay/inc/pp_debug.h| 10 --
>  drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c |  2 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c  |  2 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c  |  2 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c   |  2 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c|  2 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c |  2 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c  |  2 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c|  2 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c |  2 +-
>  19 files changed, 27 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index cc72190..8b85153 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -20,6 +20,7 @@
>   * OTHER DEALINGS IN THE SOFTWARE.
>   *
>   */
> +#include "pp_debug.h"
>  #include 
>  #include 
>  #include 
> @@ -29,7 +30,6 @@
>  #include "pp_instance.h"
>  #include "power_state.h"
>  #include "eventmanager.h"
> -#include "pp_debug.h"
>  
>  
>  #define PP_CHECK(handle) \
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index 74dbbd1..d043337 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> @@ -20,13 +20,13 @@
>   * OTHER DEALINGS IN THE SOFTWARE.
>   *
>   */
> +#include "pp_debug.h"
>  #include 
>  #include 
>  #include 
>  #include "atom-types.h"
>  #include "atombios.h"
>  #include "processpptables.h"
> -#include "pp_debug.h"
>  #include "cgs_common.h"
>  #include "smu/smu_8_0_d.h"
>  #include "smu8_fusion.h"
> @@ -38,7 +38,6 @@
>  #include "cz_hwmgr.h"
>  #include "power_state.h"
>  #include "cz_clockpowergating.h"
> -#include "pp_debug.h"
>  
>  #define ixSMUSVI_NB_CURRENTVID 0xD8230044
>  #define CURRENT_NB_VID_MASK 0xff00
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> index c355a0f..0eb8e886 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> @@ -20,11 +20,11 @@
>   * OTHER DEALINGS IN THE SOFTWARE.
>   *
>   */
> +#include "pp_debug.h"
>  #include 
>  #include "hwmgr.h"
>  #include "hardwaremanager.h"
>  #include "power_state.h"
> -#include "pp_debug.h"
>  
>  #define PHM_FUNC_CHECK(hw) \
>   do {\
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index b036064..fcfd648 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/d

Re: [PATCH] drm/amdgpu: Remove checking for atombios

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 12/15/2016 07:52 AM, Nils Wallménius wrote:
> This is a left over from radeon, amdgpu doesn't support any
> non-atombios parts and amdgpu_device_init would bail if the
> check for atombios failed anyway.
> 
> Signed-off-by: Nils Wallménius <nils.wallmen...@gmail.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  1 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c   | 10 --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c   | 12 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  8 +---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c| 10 --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c|  3 +--
>  drivers/gpu/drm/amd/amdgpu/atombios_encoders.c |  6 --
>  7 files changed, 16 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 29d3a91..11de710 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1330,7 +1330,6 @@ struct amdgpu_device {
>  
>   /* BIOS */
>   uint8_t *bios;
> - boolis_atom_bios;
>   struct amdgpu_bo*stollen_vga_memory;
>   uint32_tbios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
>  
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> index 5796539..ef79551 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> @@ -672,12 +672,10 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
>  
>   if ((enc->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
>   enc->enc_priv) {
> - if (adev->is_atom_bios) {
> - struct amdgpu_encoder_atom_dig *dig = 
> enc->enc_priv;
> - if (dig->bl_dev) {
> - atif->encoder_for_bl = enc;
> - break;
> - }
> + struct amdgpu_encoder_atom_dig *dig = 
> enc->enc_priv;
> + if (dig->bl_dev) {
> + atif->encoder_for_bl = enc;
> + break;
>   }
>   }
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> index b7e2762..1103259 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> @@ -387,15 +387,15 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)
>   if (!bios_header_start) {
>   goto free_bios;
>   }
> +
> + /* Must be an ATOMBIOS */
>   tmp = bios_header_start + 4;
> - if (!memcmp(adev->bios + tmp, "ATOM", 4) ||
> - !memcmp(adev->bios + tmp, "MOTA", 4)) {
> - adev->is_atom_bios = true;
> - } else {
> - adev->is_atom_bios = false;
> + if (memcmp(adev->bios + tmp, "ATOM", 4) &&
> + memcmp(adev->bios + tmp, "MOTA", 4)) {
> + goto free_bios;
>   }
>  
> - DRM_DEBUG("%sBIOS detected\n", adev->is_atom_bios ? "ATOM" : "COM");
> + DRM_DEBUG("ATOMBIOS detected\n");
>   return true;
>  free_bios:
>   kfree(adev->bios);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index d907411..dc017d1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1603,7 +1603,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>   adev->pdev = pdev;
>   adev->flags = flags;
>   adev->asic_type = flags & AMD_ASIC_MASK;
> - adev->is_atom_bios = false;
>   adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
>   adev->mc.gtt_size = 512 * 1024 * 1024;
>   adev->accel_working = false;
> @@ -1718,12 +1717,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>   r = -EINVAL;
>   goto failed;
>   }
> - /* Must be an ATOMBIOS */
> - if (!adev->is_atom_bios) {
> - dev_err(adev->dev, "Expecting atombios for GPU\n");
> - r = -EINVAL;
> - goto failed;
> - }
> +
>   r = amdgpu_a

Re: [PATCH] drm/amdgpu: use pin rather than pin_restricted in a few cases

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 12/08/2016 08:17 AM, Alex Deucher wrote:
> We don't require a resticted pinning in these cases, so just
> use plain pin.
> 
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 741144f..581601c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -187,7 +187,7 @@ int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
>   goto cleanup;
>   }
>  
> - r = amdgpu_bo_pin_restricted(new_abo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, 
> );
> + r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM, );
>   if (unlikely(r != 0)) {
>   r = -EINVAL;
>   DRM_ERROR("failed to pin new abo buffer before flip\n");
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> index f1c9e59..24629be 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> @@ -171,7 +171,7 @@ static int amdgpufb_create_pinned_object(struct 
> amdgpu_fbdev *rfbdev,
>   }
>  
>  
> - ret = amdgpu_bo_pin_restricted(abo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, NULL);
> + ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
>   if (ret) {
>   amdgpu_bo_unreserve(abo);
>   goto out_unref;
> 



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Re: [PATCH 1/3] drm/amd/amdgpu: Add debugfs support for reading GPRs

[Edward O'Callaghan]

Hi Tom,

On 12/06/2016 05:36 AM, Tom St Denis wrote:
> Implemented for SGPRs for GFX v8 initially.
> 
> Signed-off-by: Tom St Denis 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 72 
> ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 25 +++
>  3 files changed, 99 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 4f64bb16a8d3..2834451eef8a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -844,6 +844,8 @@ struct amdgpu_gfx_funcs {
>   uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
>   void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 
> sh_num, u32 instance);
>   void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 
> uint32_t wave, uint32_t *dst, int *no_fields);
> + void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, 
> uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
> + void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 
> uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
>  };
>  
>  struct amdgpu_gfx {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 25ad736b5ca5..7f9cb1c85d75 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3055,6 +3055,71 @@ static ssize_t amdgpu_debugfs_wave_read(struct file 
> *f, char __user *buf,
>   return result;
>  }
>  
> +static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
> + size_t size, loff_t *pos)
> +{
> + struct amdgpu_device *adev = f->f_inode->i_private;

Could f potentially be null here?

> + int r;
> + ssize_t result=0;

result = 0

> + uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
> +
> + if (size & 3 || *pos & 3)
> + return -EINVAL;
> +
> + /* decode offset */
> + offset = (*pos & 0xFFF);
> + se = ((*pos >> 12) & 0xFF);
> + sh = ((*pos >> 20) & 0xFF);
> + cu = ((*pos >> 28) & 0xFF);
> + wave = ((*pos >> 36) & 0xFF);
> + simd = ((*pos >> 44) & 0xFF);
> + thread = ((*pos >> 52) & 0xFF);
> + bank = ((*pos >> 60) & 1);
> +
> + /* sanity check offset/size */
> + if (offset + size > (adev->gfx.config.max_gprs << 2))
> + return -EINVAL;
> +
> + data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + /* switch to the specific se/sh/cu */
> + mutex_lock(>grbm_idx_mutex);
> + amdgpu_gfx_select_se_sh(adev, se, sh, cu);
> +
> + if (bank == 0) {
> + if (adev->gfx.funcs->read_wave_vgprs)
> + adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, 
> thread, offset>>2, size>>2, data);
> + } else {
> + if (adev->gfx.funcs->read_wave_sgprs)
> + adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, 
> offset>>2, size>>2, data);
> + }
> +
> + amdgpu_gfx_select_se_sh(adev, 0x, 0x, 0x);
> + mutex_unlock(>grbm_idx_mutex);
> +
> + while (size) {
> + uint32_t value;
> +
> + value = data[offset >> 2];
> + r = put_user(value, (uint32_t *)buf);
> + if (r) {
> + result = r;
> + goto err;
> + }
> +
> + result += 4;
> + buf += 4;
> + offset += 4;
> + size -= 4;
> + }
> +
> +err:
> + kfree(data);
> + return result;
> +}
> +
>  static const struct file_operations amdgpu_debugfs_regs_fops = {
>   .owner = THIS_MODULE,
>   .read = amdgpu_debugfs_regs_read,
> @@ -3097,6 +3162,11 @@ static const struct file_operations 
> amdgpu_debugfs_wave_fops = {
>   .read = amdgpu_debugfs_wave_read,
>   .llseek = default_llseek
>  };
> +static const struct file_operations amdgpu_debugfs_gpr_fops = {
> + .owner = THIS_MODULE,
> + .read = amdgpu_debugfs_gpr_read,
> + .llseek = default_llseek
> +};
>  
>  static const struct file_operations *debugfs_regs[] = {
>   _debugfs_regs_fops,
> @@ -3106,6 +3176,7 @@ static const struct file_operations *debugfs_regs[] = {
>   _debugfs_gca_config_fops,
>   _debugfs_sensors_fops,
>   _debugfs_wave_fops,
> + _debugfs_gpr_fops,
>  };
>  
>  static const char *debugfs_regs_names[] = {
> @@ -3116,6 +3187,7 @@ static const char *debugfs_regs_names[] = {
>   "amdgpu_gca_config",
>   "amdgpu_sensors",
>   "amdgpu_wave",
> + "amdgpu_gpr",
>  };
>  
>  static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 

amdgpu: ratelimit on vm faults to avoid spaming console

[Edward O'Callaghan]

These are rather minor however should help stop some folks
machines grinding to a halt when a userspace application somehow
gets the GPU into some horrible state causing the console to fill
very quickly. Applies on top of master.

Please kindly review,

Edward O'Callaghan (2):
 [PATCH v2 1/2] amdgpu: Use dev_err() over vanilla printk() in
 [PATCH v2 2/2] amdgpu: Wrap dev_err() calls on vm faults with
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[PATCH v2 1/2] amdgpu: Use dev_err() over vanilla printk() in vm_decode_fault()

[Edward O'Callaghan]

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index aa0c4b9..a0df431 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -711,7 +711,7 @@ static void gmc_v7_0_vm_decode_fault(struct amdgpu_device 
*adev,
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
  MEMORY_CLIENT_ID);
 
-   printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) 
(%d)\n",
+   dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' 
(0x%08x) (%d)\n",
   protections, vmid, addr,
   REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 MEMORY_CLIENT_RW) ?
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index a16b220..7285294 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -837,7 +837,7 @@ static void gmc_v8_0_vm_decode_fault(struct amdgpu_device 
*adev,
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
  MEMORY_CLIENT_ID);
 
-   printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) 
(%d)\n",
+   dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' 
(0x%08x) (%d)\n",
   protections, vmid, addr,
   REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 MEMORY_CLIENT_RW) ?
-- 
2.7.4

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Re: [PATCH 2/2] amdgpu: Use 'dev_err_ratelimited()' over 'dev_err()' on vm faults

[Edward O'Callaghan]

On 11/07/2016 02:55 PM, Michel Dänzer wrote:
> On 07/11/16 12:47 PM, Edward O'Callaghan wrote:
>> It can be the case that upon GPU page faults we start trashing
>> the logs, and so let us ratelimit here to avoid that.
>>
>> Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 8 
>>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 
>>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 
>>  3 files changed, 12 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> index b13c8aa..79af3f2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> @@ -549,7 +549,7 @@ static void gmc_v6_0_vm_decode_fault(struct 
>> amdgpu_device *adev,
>>  mc_id = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS,
>>xxMEMORY_CLIENT_ID);
>>  
>> -dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' 
>> (0x%08x) (%d)\n",
>> +dev_err_ratelimited(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, 
>> %s from '%s' (0x%08x) (%d)\n",
>> protections, vmid, addr,
>> REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS,
>>   xxMEMORY_CLIENT_RW) ?
>> @@ -1007,11 +1007,11 @@ static int gmc_v6_0_process_interrupt(struct 
>> amdgpu_device *adev,
>>  if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
>>  gmc_v6_0_set_fault_enable_default(adev, false);
>>  
>> -dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
>> +dev_err_ratelimited(adev->dev, "GPU fault detected: %d 0x%08x\n",
>>  entry->src_id, entry->src_data);
>> -dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
>> +dev_err_ratelimited(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   
>> 0x%08X\n",
>>  addr);
>> -dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
>> +dev_err_ratelimited(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 
>> 0x%08X\n",
>>  status);
>>  gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
> 
> If calling dev_err_ratelimited separately for each line means that some
> lines corresponding to a single VM fault may or may not appear depending
> on the rate, it'd be better to use a single call per VM fault.
Ah ok, yes I was not 100% that was definitely the case - easy to fix, I
will resend a update to address it. Thanks, Ed.

> 
> 



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[PATCH 1/2] amdgpu: Use dev_err() over vanilla printk() in vm_decode_fault()

[Edward O'Callaghan]

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index aa0c4b9..a0df431 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -711,7 +711,7 @@ static void gmc_v7_0_vm_decode_fault(struct amdgpu_device 
*adev,
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
  MEMORY_CLIENT_ID);
 
-   printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) 
(%d)\n",
+   dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' 
(0x%08x) (%d)\n",
   protections, vmid, addr,
   REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 MEMORY_CLIENT_RW) ?
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index a16b220..7285294 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -837,7 +837,7 @@ static void gmc_v8_0_vm_decode_fault(struct amdgpu_device 
*adev,
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
  MEMORY_CLIENT_ID);
 
-   printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) 
(%d)\n",
+   dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' 
(0x%08x) (%d)\n",
   protections, vmid, addr,
   REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 MEMORY_CLIENT_RW) ?
-- 
2.7.4

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[PATCH 2/2] amdgpu: Use 'dev_err_ratelimited()' over 'dev_err()' on vm faults

[Edward O'Callaghan]

It can be the case that upon GPU page faults we start trashing
the logs, and so let us ratelimit here to avoid that.

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 8 
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index b13c8aa..79af3f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -549,7 +549,7 @@ static void gmc_v6_0_vm_decode_fault(struct amdgpu_device 
*adev,
mc_id = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS,
  xxMEMORY_CLIENT_ID);
 
-   dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' 
(0x%08x) (%d)\n",
+   dev_err_ratelimited(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, 
%s from '%s' (0x%08x) (%d)\n",
   protections, vmid, addr,
   REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS,
 xxMEMORY_CLIENT_RW) ?
@@ -1007,11 +1007,11 @@ static int gmc_v6_0_process_interrupt(struct 
amdgpu_device *adev,
if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
gmc_v6_0_set_fault_enable_default(adev, false);
 
-   dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
+   dev_err_ratelimited(adev->dev, "GPU fault detected: %d 0x%08x\n",
entry->src_id, entry->src_data);
-   dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
+   dev_err_ratelimited(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   
0x%08X\n",
addr);
-   dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
+   dev_err_ratelimited(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 
0x%08X\n",
status);
gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index a0df431..4ed97c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -711,7 +711,7 @@ static void gmc_v7_0_vm_decode_fault(struct amdgpu_device 
*adev,
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
  MEMORY_CLIENT_ID);
 
-   dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' 
(0x%08x) (%d)\n",
+   dev_err_ratelimited(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, 
%s from '%s' (0x%08x) (%d)\n",
   protections, vmid, addr,
   REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 MEMORY_CLIENT_RW) ?
@@ -1198,11 +1198,11 @@ static int gmc_v7_0_process_interrupt(struct 
amdgpu_device *adev,
if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
gmc_v7_0_set_fault_enable_default(adev, false);
 
-   dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
+   dev_err_ratelimited(adev->dev, "GPU fault detected: %d 0x%08x\n",
entry->src_id, entry->src_data);
-   dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
+   dev_err_ratelimited(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   
0x%08X\n",
addr);
-   dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
+   dev_err_ratelimited(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 
0x%08X\n",
status);
gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 7285294..050a884 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -837,7 +837,7 @@ static void gmc_v8_0_vm_decode_fault(struct amdgpu_device 
*adev,
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
  MEMORY_CLIENT_ID);
 
-   dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' 
(0x%08x) (%d)\n",
+   dev_err_ratelimited(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, 
%s from '%s' (0x%08x) (%d)\n",
   protections, vmid, addr,
   REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 MEMORY_CLIENT_RW) ?
@@ -1242,11 +1242,11 @@ static int gmc_v8_0_process_interrupt(struct 
amdgpu_device *adev,
if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
gmc_v8_0_set_fault_enable_default(adev, false);
 
-  

amdgpu: ratelimit on vm faults to avoid spaming console

[Edward O'Callaghan]

These are rather minor however should help stop some folks
machines grinding to a halt when a userspace application somehow
gets the GPU into some horrible state causing the console to fill
very quickly. Applies on top of master.

Please kindly review,

Edward O'Callaghan (2):
 [PATCH 1/2] amdgpu: Use dev_err() over vanilla printk() in
 [PATCH 2/2] amdgpu: Use 'dev_err_ratelimited()' over 'dev_err()' on
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Re: [PATCH 1/2] drm/amd/powerplay: export a function to read fan rpm

[Edward O'Callaghan]

Howdy,

On 10/30/2016 07:28 AM, Grazvydas Ignotas wrote:
> Powerplay hwmgr already has an implementation, all we need to do is to call 
> it.
> 
> Signed-off-by: Grazvydas Ignotas 
> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 ++
>  drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h |  1 +
>  2 files changed, 19 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 0b1f220..1f49764 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -582,6 +582,23 @@ static int pp_dpm_get_fan_speed_percent(void *handle, 
> uint32_t *speed)
>   return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
>  }
>  
> +static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)

why not type the handle rather than have 'void *' and a coercion (I
didn't check the call site yet..)

> +{
> + struct pp_hwmgr *hwmgr;
> +
> + if (handle == NULL)

if (!handle)

> + return -EINVAL;
> +
> + hwmgr = ((struct pp_instance *)handle)->hwmgr;
> +
> + PP_CHECK_HW(hwmgr);
> +
> + if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)

if (!hwmgr->hwmgr_func->get_fan_speed_rpm)

> + return -EINVAL;
> +
> + return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
> +}
> +
>  static int pp_dpm_get_temperature(void *handle)
>  {
>   struct pp_hwmgr  *hwmgr;
> @@ -852,6 +869,7 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {
>   .get_fan_control_mode = pp_dpm_get_fan_control_mode,
>   .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
>   .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
> + .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
>   .get_pp_num_states = pp_dpm_get_pp_num_states,
>   .get_pp_table = pp_dpm_get_pp_table,
>   .set_pp_table = pp_dpm_set_pp_table,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h 
> b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> index eb3e83d..2892b4e 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> @@ -349,6 +349,7 @@ struct amd_powerplay_funcs {
>   int (*get_fan_control_mode)(void *handle);
>   int (*set_fan_speed_percent)(void *handle, uint32_t percent);
>   int (*get_fan_speed_percent)(void *handle, uint32_t *speed);
> + int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
>   int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
>   int (*get_pp_table)(void *handle, char **table);
>   int (*set_pp_table)(void *handle, const char *buf, size_t size);
> 



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Re: [PATCH] drm/amd/powerplay: don't succeed in getters if fan is missing

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 10/30/2016 07:32 AM, Grazvydas Ignotas wrote:
> Otherwise callers end up using uninitialized data.
> 
> Signed-off-by: Grazvydas Ignotas <nota...@gmail.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
> index fb6c6f6..29d0319 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
> @@ -30,7 +30,7 @@ int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
>   struct phm_fan_speed_info *fan_speed_info)
>  {
>   if (hwmgr->thermal_controller.fanInfo.bNoFan)
> - return 0;
> + return -ENODEV;
>  
>   fan_speed_info->supports_percent_read = true;
>   fan_speed_info->supports_percent_write = true;
> @@ -60,7 +60,7 @@ int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr 
> *hwmgr,
>   uint64_t tmp64;
>  
>   if (hwmgr->thermal_controller.fanInfo.bNoFan)
> - return 0;
> + return -ENODEV;
>  
>   duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
>   CG_FDO_CTRL1, FMAX_DUTY100);
> @@ -89,7 +89,7 @@ int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, 
> uint32_t *speed)
>   if (hwmgr->thermal_controller.fanInfo.bNoFan ||
>   (hwmgr->thermal_controller.fanInfo.
>   ucTachometerPulsesPerRevolution == 0))
> - return 0;
> + return -ENODEV;
>  
>   tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 
> CGS_IND_REG__SMC,
>   CG_TACH_STATUS, TACH_PERIOD);
> 



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Re: [PATCH] drm/amdgpu: update kernel-doc for some functions

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 10/24/2016 05:31 AM, Grazvydas Ignotas wrote:
> The names were wrong.
> 
> Signed-off-by: Grazvydas Ignotas <nota...@gmail.com>
> ---
>  drivers/gpu/drm/amd/scheduler/sched_fence.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/scheduler/sched_fence.c 
> b/drivers/gpu/drm/amd/scheduler/sched_fence.c
> index 6b63bea..3653b5a 100644
> --- a/drivers/gpu/drm/amd/scheduler/sched_fence.c
> +++ b/drivers/gpu/drm/amd/scheduler/sched_fence.c
> @@ -103,7 +103,7 @@ static void amd_sched_fence_free(struct rcu_head *rcu)
>  }
>  
>  /**
> - * amd_sched_fence_release - callback that fence can be freed
> + * amd_sched_fence_release_scheduled - callback that fence can be freed
>   *
>   * @fence: fence
>   *
> @@ -118,7 +118,7 @@ static void amd_sched_fence_release_scheduled(struct 
> fence *f)
>  }
>  
>  /**
> - * amd_sched_fence_release_scheduled - drop extra reference
> + * amd_sched_fence_release_finished - drop extra reference
>   *
>   * @f: fence
>   *
> 



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Re: [PATCH] drm/amdgpu: use amdgpu_bo_[create|free]_kernel for wb

[Edward O'Callaghan]

Acked-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 10/22/2016 06:31 AM, Alex Deucher wrote:
> Rather than open coding it.
> 
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 37 
> ++
>  1 file changed, 7 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index b7b6542..314295f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -443,13 +443,9 @@ void amdgpu_doorbell_get_kfd_info(struct amdgpu_device 
> *adev,
>  static void amdgpu_wb_fini(struct amdgpu_device *adev)
>  {
>   if (adev->wb.wb_obj) {
> - if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
> - amdgpu_bo_kunmap(adev->wb.wb_obj);
> - amdgpu_bo_unpin(adev->wb.wb_obj);
> - amdgpu_bo_unreserve(adev->wb.wb_obj);
> - }
> - amdgpu_bo_unref(>wb.wb_obj);
> - adev->wb.wb = NULL;
> + amdgpu_bo_free_kernel(>wb.wb_obj,
> +   >wb.gpu_addr,
> +   (void **)>wb.wb);
>   adev->wb.wb_obj = NULL;
>   }
>  }
> @@ -468,33 +464,14 @@ static int amdgpu_wb_init(struct amdgpu_device *adev)
>   int r;
>  
>   if (adev->wb.wb_obj == NULL) {
> - r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
> -  AMDGPU_GEM_DOMAIN_GTT, 0,  NULL, NULL,
> -  >wb.wb_obj);
> + r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * 4,
> + PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
> + >wb.wb_obj, 
> >wb.gpu_addr,
> + (void **)>wb.wb);
>   if (r) {
>   dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
>   return r;
>   }
> - r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
> - if (unlikely(r != 0)) {
> - amdgpu_wb_fini(adev);
> - return r;
> - }
> - r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
> - >wb.gpu_addr);
> - if (r) {
> - amdgpu_bo_unreserve(adev->wb.wb_obj);
> - dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
> - amdgpu_wb_fini(adev);
> - return r;
> - }
> - r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)>wb.wb);
> - amdgpu_bo_unreserve(adev->wb.wb_obj);
> - if (r) {
> - dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
> - amdgpu_wb_fini(adev);
> - return r;
> - }
>  
>   adev->wb.num_wb = AMDGPU_MAX_WB;
>   memset(>wb.used, 0, sizeof(adev->wb.used));
> 



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Re: [PATCH] drm/amdgpu/atom: remove a bunch of unused functions

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 10/22/2016 06:55 AM, Alex Deucher wrote:
> Leftovers from the radeon.
> 
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 82 
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 10 
>  2 files changed, 92 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> index 76cbb1d..56a86dd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> @@ -1115,49 +1115,6 @@ int amdgpu_atombios_get_memory_pll_dividers(struct 
> amdgpu_device *adev,
>   return 0;
>  }
>  
> -uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev)
> -{
> - GET_ENGINE_CLOCK_PS_ALLOCATION args;
> - int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
> -
> - amdgpu_atom_execute_table(adev->mode_info.atom_context, index, 
> (uint32_t *));
> - return le32_to_cpu(args.ulReturnEngineClock);
> -}
> -
> -uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev)
> -{
> - GET_MEMORY_CLOCK_PS_ALLOCATION args;
> - int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
> -
> - amdgpu_atom_execute_table(adev->mode_info.atom_context, index, 
> (uint32_t *));
> - return le32_to_cpu(args.ulReturnMemoryClock);
> -}
> -
> -void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev,
> -   uint32_t eng_clock)
> -{
> - SET_ENGINE_CLOCK_PS_ALLOCATION args;
> - int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
> -
> - args.ulTargetEngineClock = cpu_to_le32(eng_clock);  /* 10 khz */
> -
> - amdgpu_atom_execute_table(adev->mode_info.atom_context, index, 
> (uint32_t *));
> -}
> -
> -void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
> -   uint32_t mem_clock)
> -{
> - SET_MEMORY_CLOCK_PS_ALLOCATION args;
> - int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
> -
> - if (adev->flags & AMD_IS_APU)
> - return;
> -
> - args.ulTargetMemoryClock = cpu_to_le32(mem_clock);  /* 10 khz */
> -
> - amdgpu_atom_execute_table(adev->mode_info.atom_context, index, 
> (uint32_t *));
> -}
> -
>  void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
>u32 eng_clock, u32 mem_clock)
>  {
> @@ -1256,45 +1213,6 @@ int 
> amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *
>   return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, 
> leakage_idx, voltage);
>  }
>  
> -void amdgpu_atombios_set_voltage(struct amdgpu_device *adev,
> -  u16 voltage_level,
> -  u8 voltage_type)
> -{
> - union set_voltage args;
> - int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
> - u8 frev, crev, volt_index = voltage_level;
> -
> - if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, 
> , ))
> - return;
> -
> - /* 0xff01 is a flag rather then an actual voltage */
> - if (voltage_level == 0xff01)
> - return;
> -
> - switch (crev) {
> - case 1:
> - args.v1.ucVoltageType = voltage_type;
> - args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
> - args.v1.ucVoltageIndex = volt_index;
> - break;
> - case 2:
> - args.v2.ucVoltageType = voltage_type;
> - args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
> - args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
> - break;
> - case 3:
> - args.v3.ucVoltageType = voltage_type;
> - args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
> - args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
> - break;
> - default:
> - DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
> - return;
> - }
> -
> - amdgpu_atom_execute_table(adev->mode_info.atom_context, index, 
> (uint32_t *));
> -}
> -
>  int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
> u16 *leakage_id)
>  {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
> index e4afb16..70e9ace 100644
> --- a/drivers/gpu/

Re: [PATCH 1/3] x86/pat: export io memory reserve/free api.

[Edward O'Callaghan]

On 10/18/2016 07:29 PM, Dave Airlie wrote:
> On 18 Oct. 2016 17:23, "Edward O'Callaghan" <funfunc...@folklore1984.net
> <mailto:funfunc...@folklore1984.net>> wrote:
>>
>> NACK,
>>
>> I think you want to use 'iomap_create_wc()' instead to avoid aliasing.
> 
> Please explain what can alias here?

Ah disregard the alias comment, I was remembering how it was introduced
and that referred to 'io_mapping_create_wc()' not hard coding WC.

Any way, I think 'iomap_create_wc()' is what your looking for so no need
to expose those symbols and hook them though.

Cheers,
Edward.

> 
> Dave.
> 
>>
>> Kind Regards,
>> Edward.
>>
>> On 10/18/2016 05:13 PM, Dave Airlie wrote:
>> > From: Dave Airlie <airl...@redhat.com <mailto:airl...@redhat.com>>
>> >
>> > These functions are needed for gpu/ttm drivers to reserve the
>> > VRAM area as write combined. In a lot of places we don't ioremap
>> > but still need to insert pfn from it into a VMA using vm_insert_mixed,
>> > but a recent change in mixed insertion means we need to reserve
>> > VRAM as WC upfront, so we need these APIs exported.
>> >
>> > Signed-off-by: Dave Airlie <airl...@redhat.com
> <mailto:airl...@redhat.com>>
>> > ---
>> >  arch/x86/mm/pat.c | 2 ++
>> >  1 file changed, 2 insertions(+)
>> >
>> > diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
>> > index 170cc4f..5ce2fbb 100644
>> > --- a/arch/x86/mm/pat.c
>> > +++ b/arch/x86/mm/pat.c
>> > @@ -719,6 +719,7 @@ out_free:
>> >  out_err:
>> >   return ret;
>> >  }
>> > +EXPORT_SYMBOL(io_reserve_memtype);
>> >
>> >  /**
>> >   * io_free_memtype - Release a memory type mapping for a region of
> memory
>> > @@ -729,6 +730,7 @@ void io_free_memtype(resource_size_t start,
> resource_size_t end)
>> >  {
>> >   free_memtype(start, end);
>> >  }
>> > +EXPORT_SYMBOL(io_free_memtype);
>> >
>> >  pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
>> >   unsigned long size, pgprot_t vma_prot)
>> >
>>
> 



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Re: [PATCH 1/3] x86/pat: export io memory reserve/free api.

[Edward O'Callaghan]

NACK,

I think you want to use 'iomap_create_wc()' instead to avoid aliasing.

Kind Regards,
Edward.

On 10/18/2016 05:13 PM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> These functions are needed for gpu/ttm drivers to reserve the
> VRAM area as write combined. In a lot of places we don't ioremap
> but still need to insert pfn from it into a VMA using vm_insert_mixed,
> but a recent change in mixed insertion means we need to reserve
> VRAM as WC upfront, so we need these APIs exported.
> 
> Signed-off-by: Dave Airlie 
> ---
>  arch/x86/mm/pat.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
> index 170cc4f..5ce2fbb 100644
> --- a/arch/x86/mm/pat.c
> +++ b/arch/x86/mm/pat.c
> @@ -719,6 +719,7 @@ out_free:
>  out_err:
>   return ret;
>  }
> +EXPORT_SYMBOL(io_reserve_memtype);
>  
>  /**
>   * io_free_memtype - Release a memory type mapping for a region of memory
> @@ -729,6 +730,7 @@ void io_free_memtype(resource_size_t start, 
> resource_size_t end)
>  {
>   free_memtype(start, end);
>  }
> +EXPORT_SYMBOL(io_free_memtype);
>  
>  pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
>   unsigned long size, pgprot_t vma_prot)
> 



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Re: [PATCH] drm/amdgpu: fix warning in dce_virtual.c

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

if possible can you squash it into the original bad commit?

On 10/15/2016 05:00 AM, Alex Deucher wrote:
> copy paste typo when I re-arranged the code.
> 
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> index 2eefa5d..48973b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> @@ -657,18 +657,18 @@ static int dce_virtual_connector_encoder_init(struct 
> amdgpu_device *adev,
>  
>   /* add a new encoder */
>   encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
> - if (!encoder) {
> - kfree(connector);
> + if (!encoder)
>   return -ENOMEM;
> - }
>   encoder->possible_crtcs = 1 << index;
>   drm_encoder_init(adev->ddev, encoder, _virtual_encoder_funcs,
>DRM_MODE_ENCODER_VIRTUAL, NULL);
>   drm_encoder_helper_add(encoder, _virtual_encoder_helper_funcs);
>  
>   connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
> - if (!connector)
> + if (!connector) {
> + kfree(encoder);
>   return -ENOMEM;
> + }
>  
>   /* add a new connector */
>   drm_connector_init(adev->ddev, connector, _virtual_connector_funcs,
> 



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Re: [PATCH] drm/radeon: allow TA_CS_BC_BASE_ADDR on SI

[Edward O'Callaghan]

On 10/10/2016 10:23 PM, Marek Olšák wrote:
> From: Marek Olšák <marek.ol...@amd.com>
> 
> Required for border colors in compute shaders.
> 
> Signed-off-by: Marek Olšák <marek.ol...@amd.com>

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

> ---
>  drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-
>  drivers/gpu/drm/radeon/si.c | 1 +
>  drivers/gpu/drm/radeon/sid.h| 1 +
>  3 files changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
> b/drivers/gpu/drm/radeon/radeon_drv.c
> index a192653..a95263c 100644
> --- a/drivers/gpu/drm/radeon/radeon_drv.c
> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> @@ -90,23 +90,24 @@
>   *   2.39.0 - Add INFO query for number of active CUs
>   *   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
>   *CS to GPU on >= r600
>   *   2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing 
> support
>   *   2.42.0 - Add VCE/VUI (Video Usability Information) support
>   *   2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
>   *   2.44.0 - SET_APPEND_CNT packet3 support
>   *   2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
>   *   2.46.0 - Add PFP_SYNC_ME support on evergreen
>   *   2.47.0 - Add UVD_NO_OP register support
> + *   2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
>   */
>  #define KMS_DRIVER_MAJOR 2
> -#define KMS_DRIVER_MINOR 47
> +#define KMS_DRIVER_MINOR 48
>  #define KMS_DRIVER_PATCHLEVEL0
>  int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
>  int radeon_driver_unload_kms(struct drm_device *dev);
>  void radeon_driver_lastclose_kms(struct drm_device *dev);
>  int radeon_driver_open_kms(struct drm_device *dev, struct drm_file 
> *file_priv);
>  void radeon_driver_postclose_kms(struct drm_device *dev,
>struct drm_file *file_priv);
>  void radeon_driver_preclose_kms(struct drm_device *dev,
>   struct drm_file *file_priv);
>  int radeon_suspend_kms(struct drm_device *dev, bool suspend,
> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
> index 7ee9aaf..e402be8 100644
> --- a/drivers/gpu/drm/radeon/si.c
> +++ b/drivers/gpu/drm/radeon/si.c
> @@ -4424,20 +4424,21 @@ static bool si_vm_reg_valid(u32 reg)
>   case PA_SC_LINE_STIPPLE_STATE:
>   case PA_SC_ENHANCE:
>   case SQC_CACHES:
>   case SPI_STATIC_THREAD_MGMT_1:
>   case SPI_STATIC_THREAD_MGMT_2:
>   case SPI_STATIC_THREAD_MGMT_3:
>   case SPI_PS_MAX_WAVE_ID:
>   case SPI_CONFIG_CNTL:
>   case SPI_CONFIG_CNTL_1:
>   case TA_CNTL_AUX:
> + case TA_CS_BC_BASE_ADDR:
>   return true;
>   default:
>   DRM_ERROR("Invalid register 0x%x in CS\n", reg);
>   return false;
>   }
>  }
>  
>  static int si_vm_packet3_ce_check(struct radeon_device *rdev,
> u32 *ib, struct radeon_cs_packet *pkt)
>  {
> diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
> index eb220ee..65a911d 100644
> --- a/drivers/gpu/drm/radeon/sid.h
> +++ b/drivers/gpu/drm/radeon/sid.h
> @@ -1138,20 +1138,21 @@
>  #define  CGTS_USER_TCC_DISABLE   0x914C
>  #define  TCC_DISABLE_MASK
> 0x
>  #define  TCC_DISABLE_SHIFT   16
>  #define  CGTS_SM_CTRL_REG0x9150
>  #define  OVERRIDE(1 << 21)
>  #define  LS_OVERRIDE (1 << 22)
>  
>  #define  SPI_LB_CU_MASK  0x9354
>  
>  #define  TA_CNTL_AUX 0x9508
> +#define  TA_CS_BC_BASE_ADDR  0x950C
>  
>  #define CC_RB_BACKEND_DISABLE0x98F4
>  #define  BACKEND_DISABLE(x)  ((x) << 16)
>  #define GB_ADDR_CONFIG   0x98F8
>  #define  NUM_PIPES(x)((x) << 0)
>  #define  NUM_PIPES_MASK  0x0007
>  #define  NUM_PIPES_SHIFT 0
>  #define  PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
>  #define  PIPE_INTERLEAVE_SIZE_MASK   0x0070
>  #define  PIPE_INTERLEAVE_SIZE_SHIFT  4
> 



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Re: [PATCH 9/9] drm/amdgpu:properly fix some JumpTable issues

[Edward O'Callaghan]

On 09/28/2016 06:36 PM, Monk Liu wrote:
> we found some MEC ucode leads to IB test fail or even
> ring test fail if Jump Table of it is not start in
> FW bo with page aligned address, fixed by always make
> JT address page aligned.
> 
> we don't need to patch JT2 for MEC2, because for VI,
> MEC2 is a copy of MEC1, thus when converting fw_type
> for MEC_JT2 we just return MEC1,hw can use the same
> JT for both MEC1 & MEC2.
> 
> above two change fixed some ring/ib test failure issue
> for some version of MEC ucode.
> 
> Change-Id: Ie3b3c4c5722fdf68f64547cdfbf9c0d3274a2a15
> Signed-off-by: Frank Min 
> Signed-off-by: Monk Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c   | 21 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 32 
> +++
>  2 files changed, 47 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> index cb1ade1..7278898 100755
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> @@ -685,11 +685,14 @@ static uint32_t fw_type_convert(struct cgs_device 
> *cgs_device, uint32_t fw_type)
>   result = AMDGPU_UCODE_ID_CP_MEC1;
>   break;
>   case CGS_UCODE_ID_CP_MEC_JT2:
> - if (adev->asic_type == CHIP_TONGA || adev->asic_type == 
> CHIP_POLARIS11
> -   || adev->asic_type == CHIP_POLARIS10)
> - result = AMDGPU_UCODE_ID_CP_MEC2;
> - else
> + /* for VI. JT2 should be the same as JT1, because:
> + 1, MEC2 and MEC1 use exactly same FW.
> + 2, JT2 is not pached but JT1 is.
> + */
> + if (adev->asic_type >= CHIP_TOPAZ)
>   result = AMDGPU_UCODE_ID_CP_MEC1;
> + else
> + result = AMDGPU_UCODE_ID_CP_MEC2;
>   break;
>   case CGS_UCODE_ID_RLC_G:
>   result = AMDGPU_UCODE_ID_RLC_G;
> @@ -779,12 +782,18 @@ static int amdgpu_cgs_get_firmware_info(struct 
> cgs_device *cgs_device,
>  
>   if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
>   (type == CGS_UCODE_ID_CP_MEC_JT2)) {
> - gpu_addr += le32_to_cpu(header->jt_offset) << 2;
> + gpu_addr += 
> ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE);
>   data_size = le32_to_cpu(header->jt_size) << 2;
>   }
> - info->mc_addr = gpu_addr;
> +
> + info->kptr = ucode->kaddr;
>   info->image_size = data_size;
> + info->mc_addr = gpu_addr;
>   info->version = 
> (uint16_t)le32_to_cpu(header->header.ucode_version);
> +
> + if (CGS_UCODE_ID_CP_MEC == type)
> + info->image_size = (header->jt_offset) << 2;
> +
>   info->fw_version = amdgpu_get_firmware_version(cgs_device, 
> type);
>   info->feature_version = 
> (uint16_t)le32_to_cpu(header->ucode_feature_version);
>   } else {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> index 06baac9..e2ea2c9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> @@ -239,6 +239,31 @@ static int amdgpu_ucode_init_single_fw(struct 
> amdgpu_firmware_info *ucode,
>   return 0;
>  }
>  
> +static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
> + uint64_t mc_addr, void *kptr)
> +{
> + const struct gfx_firmware_header_v1_0 *header = NULL;
> + const struct common_firmware_header *comm_hdr = NULL;
> + uint8_t* src_addr = NULL;
> + uint8_t* dst_addr = NULL;
> +
> + if (NULL == ucode->fw)
Can be simplified to just:
+   if (!ucode->fw)

> + return 0;
Do you really want to return 0 here? In fact, at the moment the return
value isn't used nor is it currently useful. Maybe just drop it.

> +
> + comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
> + header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
> + dst_addr = ucode->kaddr +
> +ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
> +PAGE_SIZE);
> + src_addr = (uint8_t *)ucode->fw->data +
> +le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
> +(le32_to_cpu(header->jt_offset) * 4);
> + memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
> +
> + return 0;
> +}
> +
> +
>  int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
>  {
>   struct amdgpu_bo **bo = >firmware.fw_buf;
> @@ -285,6 +310,13 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
>   header = (const struct common_firmware_header 
> *)ucode->fw->data;
>   

Re: [PATCH 2/2] drm/amdkfd: Decode bit fields in 'cik_ih_ring_entry' directly

[Edward O'Callaghan]

Excellent point Christian, it did occur to me that endianness could be a
problem so will definitely fix this one up as Tom suggested.

Kind Regards,
Edward.

On 09/27/2016 11:02 PM, StDenis, Tom wrote:
> Better would be to add them to a bitmask header and then use
> REG_GET_FIELD() so it's nice and clean looking.
> 
> 
> Tom
> 
> 
> 
> 
> *From:* amd-gfx <amd-gfx-boun...@lists.freedesktop.org> on behalf of
> Christian König <deathsim...@vodafone.de>
> *Sent:* Tuesday, September 27, 2016 08:52
> *To:* Edward O'Callaghan; amd-gfx@lists.freedesktop.org
> *Subject:* Re: [PATCH 2/2] drm/amdkfd: Decode bit fields in
> 'cik_ih_ring_entry' directly
>  
> NAK, don't use bitfields to decode hardware values. They aren't portable.
> 
> Regards,
> Christian.
> 
> Am 27.09.2016 um 14:47 schrieb Edward O'Callaghan:
>> Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
>> ---
>>   drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c | 15 +--
>>   drivers/gpu/drm/amd/amdkfd/cik_int.h | 20 
>>   2 files changed, 21 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c 
>> b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
>> index 211fc48..1c47b9e 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
>> @@ -27,14 +27,12 @@
>>   static bool cik_event_interrupt_isr(struct kfd_dev *dev,
>>const uint32_t *ih_ring_entry)
>>   {
>> - unsigned int pasid;
>>const struct cik_ih_ring_entry *ihre =
>>(const struct cik_ih_ring_entry *)ih_ring_entry;
>>   
>> - pasid = (ihre->ring_id & 0x) >> 16;
>>   
>>/* Do not process in ISR, just request it to be forwarded to WQ. */
>> - return (pasid != 0) &&
>> + return (ihre->pasid != 0) &&
>>(ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE ||
>>ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG ||
>>ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE);
>> @@ -43,21 +41,18 @@ static bool cik_event_interrupt_isr(struct kfd_dev *dev,
>>   static void cik_event_interrupt_wq(struct kfd_dev *dev,
>>const uint32_t *ih_ring_entry)
>>   {
>> - unsigned int pasid;
>>const struct cik_ih_ring_entry *ihre =
>>(const struct cik_ih_ring_entry *)ih_ring_entry;
>>   
>> - pasid = (ihre->ring_id & 0x) >> 16;
>> -
>> - if (pasid == 0)
>> + if (ihre->pasid == 0)
>>return;
>>   
>>if (ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE)
>> - kfd_signal_event_interrupt(pasid, 0, 0);
>> + kfd_signal_event_interrupt(ihre->pasid, 0, 0);
>>else if (ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG)
>> - kfd_signal_event_interrupt(pasid, ihre->data & 0xFF, 8);
>> + kfd_signal_event_interrupt(ihre->pasid, ihre->data & 0xFF, 8);
>>else if (ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE)
>> - kfd_signal_hw_exception_event(pasid);
>> + kfd_signal_hw_exception_event(ihre->pasid);
>>   }
>>   
>>   const struct kfd_event_interrupt_class event_interrupt_class_cik = {
>> diff --git a/drivers/gpu/drm/amd/amdkfd/cik_int.h 
>> b/drivers/gpu/drm/amd/amdkfd/cik_int.h
>> index 79a16d2..27d1ede 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/cik_int.h
>> +++ b/drivers/gpu/drm/amd/amdkfd/cik_int.h
>> @@ -26,10 +26,22 @@
>>   #include 
>>   
>>   struct cik_ih_ring_entry {
>> - uint32_t source_id;
>> - uint32_t data;
>> - uint32_t ring_id;
>> - uint32_t reserved;
>> + uint32_t source_id:8;
>> + uint32_t reserved1:8;
>> + uint32_t reserved2:16;
>> +
>> + uint32_t data:28;
>> + uint32_t reserved3:4;
>> +
>> + /* pipeid, meid and unused3 are officially called RINGID,
>> +  * but for our purposes, they always decode into pipe and ME. */
>> + uint32_t pipeid:2;
>> + uint32_t meid:2;
>> + uint32_t reserved4:4;
>> + uint32_t vmid:8;
>> + uint32_t pasid:16;
>> +
>> + uint32_t reserved5;
>>   };
>>   
>>   #define CIK_INTSRC_DEQUEUE_COMPLETE 0xC6
> 
&

Additional amdkfd cleanups for 4.9

[Edward O'Callaghan]

These additional minor changes apply on top of my previous set. Nothing
too interesting here just yet more clean ups to make way for future changes.

Please review,
Kind Regards,

Edward O'Callaghan (2):
 [PATCH 1/2] drm/amdkfd: Use kfd_vm_info struct to carry consts state
 [PATCH 2/2] drm/amdkfd: Decode bit fields in 'cik_ih_ring_entry'
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[PATCH 2/2] drm/amdkfd: Decode bit fields in 'cik_ih_ring_entry' directly

[Edward O'Callaghan]

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c | 15 +--
 drivers/gpu/drm/amd/amdkfd/cik_int.h | 20 
 2 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c 
b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
index 211fc48..1c47b9e 100644
--- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
+++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
@@ -27,14 +27,12 @@
 static bool cik_event_interrupt_isr(struct kfd_dev *dev,
const uint32_t *ih_ring_entry)
 {
-   unsigned int pasid;
const struct cik_ih_ring_entry *ihre =
(const struct cik_ih_ring_entry *)ih_ring_entry;
 
-   pasid = (ihre->ring_id & 0x) >> 16;
 
/* Do not process in ISR, just request it to be forwarded to WQ. */
-   return (pasid != 0) &&
+   return (ihre->pasid != 0) &&
(ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE ||
ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG ||
ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE);
@@ -43,21 +41,18 @@ static bool cik_event_interrupt_isr(struct kfd_dev *dev,
 static void cik_event_interrupt_wq(struct kfd_dev *dev,
const uint32_t *ih_ring_entry)
 {
-   unsigned int pasid;
const struct cik_ih_ring_entry *ihre =
(const struct cik_ih_ring_entry *)ih_ring_entry;
 
-   pasid = (ihre->ring_id & 0x) >> 16;
-
-   if (pasid == 0)
+   if (ihre->pasid == 0)
return;
 
if (ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE)
-   kfd_signal_event_interrupt(pasid, 0, 0);
+   kfd_signal_event_interrupt(ihre->pasid, 0, 0);
else if (ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG)
-   kfd_signal_event_interrupt(pasid, ihre->data & 0xFF, 8);
+   kfd_signal_event_interrupt(ihre->pasid, ihre->data & 0xFF, 8);
else if (ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE)
-   kfd_signal_hw_exception_event(pasid);
+   kfd_signal_hw_exception_event(ihre->pasid);
 }
 
 const struct kfd_event_interrupt_class event_interrupt_class_cik = {
diff --git a/drivers/gpu/drm/amd/amdkfd/cik_int.h 
b/drivers/gpu/drm/amd/amdkfd/cik_int.h
index 79a16d2..27d1ede 100644
--- a/drivers/gpu/drm/amd/amdkfd/cik_int.h
+++ b/drivers/gpu/drm/amd/amdkfd/cik_int.h
@@ -26,10 +26,22 @@
 #include 
 
 struct cik_ih_ring_entry {
-   uint32_t source_id;
-   uint32_t data;
-   uint32_t ring_id;
-   uint32_t reserved;
+   uint32_t source_id:8;
+   uint32_t reserved1:8;
+   uint32_t reserved2:16;
+
+   uint32_t data:28;
+   uint32_t reserved3:4;
+
+   /* pipeid, meid and unused3 are officially called RINGID,
+* but for our purposes, they always decode into pipe and ME. */
+   uint32_t pipeid:2;
+   uint32_t meid:2;
+   uint32_t reserved4:4;
+   uint32_t vmid:8;
+   uint32_t pasid:16;
+
+   uint32_t reserved5;
 };
 
 #define CIK_INTSRC_DEQUEUE_COMPLETE0xC6
-- 
2.7.4

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[PATCH 1/2] drm/amdkfd: Use kfd_vm_info struct to carry consts state

[Edward O'Callaghan]

Use a struct to carry the calculated const state inside the
main kfd_dev state to use where we need it. Minor cleanups
while we are here.

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c|  9 ++---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c|  7 +++
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  | 13 ++---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h  |  3 ---
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  7 +++
 drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  2 +-
 6 files changed, 23 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
index d5e19b5..2114c66 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
@@ -800,13 +800,8 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, 
struct kfd_process *p)
union GRBM_GFX_INDEX_BITS reg_gfx_index;
struct kfd_process_device *pdd;
struct dbg_wave_control_info wac_info;
-   int temp;
-   int first_vmid_to_scan = 8;
-   int last_vmid_to_scan = 15;
-
-   first_vmid_to_scan = ffs(dev->shared_resources.compute_vmid_bitmap) - 1;
-   temp = dev->shared_resources.compute_vmid_bitmap >> first_vmid_to_scan;
-   last_vmid_to_scan = first_vmid_to_scan + ffz(temp);
+   int first_vmid_to_scan = dev->vm_info.first_vmid_kfd;
+   int last_vmid_to_scan = dev->vm_info.last_vmid_kfd;
 
reg_sq_cmd.u32All = 0;
status = 0;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 3f95f7c..2417b44 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -223,9 +223,16 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 const struct kgd2kfd_shared_resources *gpu_resources)
 {
unsigned int size;
+   unsigned int vmid_bitmap_kfd;
 
kfd->shared_resources = *gpu_resources;
 
+   vmid_bitmap_kfd = kfd->shared_resources.compute_vmid_bitmap;
+   kfd->vm_info.first_vmid_kfd = ffs(vmid_bitmap_kfd) - 1;
+   kfd->vm_info.last_vmid_kfd = fls(vmid_bitmap_kfd) - 1;
+   kfd->vm_info.vmid_num_kfd = 1 + kfd->vm_info.last_vmid_kfd
+   - kfd->vm_info.first_vmid_kfd;
+
/* calculate max size of mqds needed for queues */
size = max_num_of_queues_per_device *
kfd->device_info->mqd_size_aligned;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index f49c551..f13058c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -100,11 +100,11 @@ static int allocate_vmid(struct device_queue_manager *dqm,
if (dqm->vmid_bitmap == 0)
return -ENOMEM;
 
-   bit = find_first_bit((unsigned long *)>vmid_bitmap, CIK_VMID_NUM);
+   bit = find_first_bit((unsigned long *)>vmid_bitmap,
+   dqm->dev->vm_info.vmid_num_kfd);
clear_bit(bit, (unsigned long *)>vmid_bitmap);
 
-   /* Kaveri kfd vmid's starts from vmid 8 */
-   allocated_vmid = bit + KFD_VMID_START_OFFSET;
+   allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
pr_debug("kfd: vmid allocation %d\n", allocated_vmid);
qpd->vmid = allocated_vmid;
q->properties.vmid = allocated_vmid;
@@ -119,7 +119,7 @@ static void deallocate_vmid(struct device_queue_manager 
*dqm,
struct qcm_process_device *qpd,
struct queue *q)
 {
-   int bit = qpd->vmid - KFD_VMID_START_OFFSET;
+   int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
 
/* Release the vmid mapping */
set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
@@ -570,7 +570,7 @@ static int initialize_nocpsch(struct device_queue_manager 
*dqm)
for (i = 0; i < get_pipes_num(dqm); i++)
dqm->allocated_queues[i] = (1 << QUEUES_PER_PIPE) - 1;
 
-   dqm->vmid_bitmap = (1 << VMID_PER_DEVICE) - 1;
+   dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
 
init_scheduler(dqm);
@@ -684,8 +684,7 @@ static int set_sched_resources(struct device_queue_manager 
*dqm)
 
queue_num = get_pipes_num_cpsch() * QUEUES_PER_PIPE;
queue_mask = (1 << queue_num) - 1;
-   res.vmid_mask = (1 << VMID_PER_DEVICE) - 1;
-   res.vmid_mask <<= KFD_VMID_START_OFFSET;
+   res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
res.queue_mask = queue_mask &l

Re: VRAM manager

[Edward O'Callaghan]

This series is, to the best of my ability,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 09/27/2016 07:49 PM, Christian König wrote:
> Hi guys,
> 
> after fixing all those nasty little bugs this seems to be stable now.
> 
> Anybody brave enough to give it an review?
> 
> Cheers,
> Christian.
> 
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> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> 



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Re: [PATCH 3/3] drm/amd/amdgpu: Various cleanups for DCEv6

[Edward O'Callaghan]

This patch is,
Review-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 09/23/2016 02:43 AM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 46 
> ---
>  1 file changed, 10 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index dce5414f4ae3..a4fa30b9924a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -1474,10 +1474,7 @@ static void dce_v6_0_vga_enable(struct drm_crtc *crtc, 
> bool enable)
>   u32 vga_control;
>  
>   vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
> - if (enable)
> - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
> - else
> - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
> + WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 
> 1 : 0));
>  }
>  
>  static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
> @@ -1486,10 +1483,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc 
> *crtc, bool enable)
>   struct drm_device *dev = crtc->dev;
>   struct amdgpu_device *adev = dev->dev_private;
>  
> - if (enable)
> - WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
> - else
> - WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
> + WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 
> 0);
>  }
>  
>  static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
> @@ -1519,8 +1513,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc 
> *crtc,
>   if (atomic) {
>   amdgpu_fb = to_amdgpu_framebuffer(fb);
>   target_fb = fb;
> - }
> - else {
> + } else {
>   amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
>   target_fb = crtc->primary->fb;
>   }
> @@ -1534,9 +1527,9 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc 
> *crtc,
>   if (unlikely(r != 0))
>   return r;
>  
> - if (atomic)
> + if (atomic) {
>   fb_location = amdgpu_bo_gpu_offset(abo);
> - else {
> + } else {
>   r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, _location);
>   if (unlikely(r != 0)) {
>   amdgpu_bo_unreserve(abo);
> @@ -1632,8 +1625,9 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc 
> *crtc,
>   fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
>   fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
>   fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
> - } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 
> ARRAY_1D_TILED_THIN1)
> + } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 
> ARRAY_1D_TILED_THIN1) {
>   fb_format |= 
> EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
> + }
>  
>   pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
>   fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config);
> @@ -1797,26 +1791,13 @@ static int dce_v6_0_pick_dig_encoder(struct 
> drm_encoder *encoder)
>  
>   switch (amdgpu_encoder->encoder_id) {
>   case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
> - if (dig->linkb)
> - return 1;
> - else
> - return 0;
> - break;
> + return dig->linkb ? 1 : 0;
>   case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
> - if (dig->linkb)
> - return 3;
> - else
> - return 2;
> - break;
> + return dig->linkb ? 3 : 2;
>   case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
> - if (dig->linkb)
> - return 5;
> - else
> - return 4;
> - break;
> + return dig->linkb ? 5 : 4;
>   case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
>   return 6;
> - break;
>   default:
>   DRM_ERROR("invalid encoder_id: 0x%x\n", 
> amdgpu_encoder->encoder_id);
>   return 0;
> @@ -2051,7 +2032,6 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
>   amdgpu_crtc->cursor_y);
>  
>   dce_v6_0_show_cursor(crtc);
> -
>   dce_v6_0_lock_cursor(crtc, false);
>   }
>  }
> @@ -2372,15 +2352,11 @@ stat

Re: [PATCH 1/5] drm/amdgpu:changes of virtualization cases probe (v2)

[Edward O'Callaghan]

On 09/20/2016 03:12 AM, Alex Deucher wrote:
> From: Monk Liu 
> 
> 1,Changes on virtualization detections
> 2,Don't load smu & mc firmware if using sr-iov bios
> 3,skip vPost for sriov & force vPost if dev pass-through
> 
> v2: agd: fix missed SI case
> 
> Signed-off-by: Monk Liu 
> Reviewed-by: Alex Deucher 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 38 
> +++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 25 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  2 +-
>  drivers/gpu/drm/amd/amdgpu/cik.c   |  7 --
>  drivers/gpu/drm/amd/amdgpu/fiji_smc.c  |  2 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  4 +++-
>  drivers/gpu/drm/amd/amdgpu/iceland_smc.c   |  2 +-
>  drivers/gpu/drm/amd/amdgpu/si.c|  7 --
>  drivers/gpu/drm/amd/amdgpu/tonga_smc.c |  2 +-
>  drivers/gpu/drm/amd/amdgpu/vi.c| 36 ++--
>  10 files changed, 74 insertions(+), 51 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index ee45d9f..ff6e683 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1827,6 +1827,8 @@ struct amdgpu_asic_funcs {
>   bool (*read_disabled_bios)(struct amdgpu_device *adev);
>   bool (*read_bios_from_rom)(struct amdgpu_device *adev,
>  u8 *bios, u32 length_bytes);
> + void (*detect_hw_virtualization) (struct amdgpu_device *adev);
> + void (*detect_sriov_bios)(struct amdgpu_device *adev);
>   int (*read_register)(struct amdgpu_device *adev, u32 se_num,
>u32 sh_num, u32 reg_offset, u32 *value);
>   void (*set_vga_state)(struct amdgpu_device *adev, bool state);
> @@ -1836,8 +1838,6 @@ struct amdgpu_asic_funcs {
>   /* MM block clocks */
>   int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
>   int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
> - /* query virtual capabilities */
> - u32 (*get_virtual_caps)(struct amdgpu_device *adev);
>   /* static power management */
>   int (*get_pcie_lanes)(struct amdgpu_device *adev);
>   void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
> @@ -1934,15 +1934,36 @@ struct cgs_device *amdgpu_cgs_create_device(struct 
> amdgpu_device *adev);
>  void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
>  
>  
> +#define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS  (1 << 0) /* vBIOS is sr-iov ready */
> +#define AMDGPU_SRIOV_CAPS_ENABLE_IOV   (1 << 1) /* sr-iov is enabled on this 
> GPU */
> +#define AMDGPU_SRIOV_CAPS_IS_VF(1 << 2) /* this GPU is a virtual 
> function */
> +#define AMDGPU_PASSTHROUGH_MODE(1 << 3) /* thw whole GPU is pass 
> through for VM */
>  /* GPU virtualization */
> -#define AMDGPU_VIRT_CAPS_SRIOV_EN   (1 << 0)
> -#define AMDGPU_VIRT_CAPS_IS_VF  (1 << 1)
>  struct amdgpu_virtualization {
> - bool supports_sr_iov;
> - bool is_virtual;
> - u32 caps;
> + uint32_t virtual_caps;
>  };
>  
> +#define amdgpu_sriov_enabled(adev) \
> +((adev)->virtualization.virtual_caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
> +
> +#define amdgpu_sriov_vf(adev) \
> +((adev)->virtualization.virtual_caps & AMDGPU_SRIOV_CAPS_IS_VF)
> +
> +#define amdgpu_sriov_bios(adev) \
> +((adev)->virtualization.virtual_caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
> +
> +#define amdgpu_passthrough(adev) \
> +((adev)->virtualization.virtual_caps & AMDGPU_PASSTHROUGH_MODE)
> +
> +static inline bool is_virtual_machine(void)
> +{
> +#ifdef CONFIG_X86
> + return boot_cpu_has(X86_FEATURE_HYPERVISOR);
> +#else
> + return false;
> +#endif
> +}
> +
>  /*
>   * Core structure, functions and helpers.
>   */
> @@ -2260,12 +2281,13 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
>  #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
>  #define amdgpu_asic_set_uvd_clocks(adev, v, d) 
> (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
>  #define amdgpu_asic_set_vce_clocks(adev, ev, ec) 
> (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
> -#define amdgpu_asic_get_virtual_caps(adev) 
> ((adev)->asic_funcs->get_virtual_caps((adev)))
>  #define amdgpu_get_pcie_lanes(adev) 
> (adev)->asic_funcs->get_pcie_lanes((adev))
>  #define amdgpu_set_pcie_lanes(adev, l) 
> (adev)->asic_funcs->set_pcie_lanes((adev), (l))
>  #define amdgpu_asic_get_gpu_clock_counter(adev) 
> (adev)->asic_funcs->get_gpu_clock_counter((adev))
>  #define amdgpu_asic_read_disabled_bios(adev) 
> (adev)->asic_funcs->read_disabled_bios((adev))
>  #define amdgpu_asic_read_bios_from_rom(adev, b, l) 
> (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
> +#define amdgpu_asic_detect_hw_virtualization(adev) 
> (adev)->asic_funcs->detect_hw_virtualization((adev))
> 

Re: [PATCH 2/5] drm/amdgpu: make sriov bios detection generic (v2)

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

as with the rest of the respective series.

On 09/20/2016 04:44 AM, Alex Deucher wrote:
> It's not asic specific.
> 
> v2: drop asic macro
> 
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 +++--
>  drivers/gpu/drm/amd/amdgpu/vi.c| 7 ---
>  3 files changed, 7 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index ff6e683..fb8d603 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1828,7 +1828,6 @@ struct amdgpu_asic_funcs {
>   bool (*read_bios_from_rom)(struct amdgpu_device *adev,
>  u8 *bios, u32 length_bytes);
>   void (*detect_hw_virtualization) (struct amdgpu_device *adev);
> - void (*detect_sriov_bios)(struct amdgpu_device *adev);
>   int (*read_register)(struct amdgpu_device *adev, u32 se_num,
>u32 sh_num, u32 reg_offset, u32 *value);
>   void (*set_vga_state)(struct amdgpu_device *adev, bool state);
> @@ -2287,7 +2286,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
>  #define amdgpu_asic_read_disabled_bios(adev) 
> (adev)->asic_funcs->read_disabled_bios((adev))
>  #define amdgpu_asic_read_bios_from_rom(adev, b, l) 
> (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
>  #define amdgpu_asic_detect_hw_virtualization(adev) 
> (adev)->asic_funcs->detect_hw_virtualization((adev))
> -#define amdgpu_asic_detect_sriov_bios(adev) 
> (adev)->asic_funcs->detect_sriov_bios((adev))
>  #define amdgpu_asic_read_register(adev, se, sh, offset, 
> v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
>  #define amdgpu_gart_flush_gpu_tlb(adev, vmid) 
> (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
>  #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) 
> (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index ca161e9..76f8298 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1535,6 +1535,12 @@ static bool amdgpu_device_is_virtual(void)
>  #endif
>  }
>  
> +static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
> +{
> + if (amdgpu_atombios_has_gpu_virtualization_table(adev))
> + adev->virtualization.virtual_caps |= 
> AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
> +}
> +
>  /**
>   * amdgpu_device_init - initialize the driver
>   *
> @@ -1690,8 +1696,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>   }
>  
>   /* detect if we are with an SRIOV vbios */
> - if (adev->asic_funcs->detect_sriov_bios)
> - amdgpu_asic_detect_sriov_bios(adev);
> + amdgpu_device_detect_sriov_bios(adev);
>  
>   /* Post card if necessary */
>   if (amdgpu_vpost_needed(adev)) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 81780f1..a8154d0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -462,12 +462,6 @@ static void vi_detect_hw_virtualization(struct 
> amdgpu_device *adev)
>   }
>  }
>  
> -static void vi_detect_sriov_bios(struct amdgpu_device *adev)
> -{
> - if (amdgpu_atombios_has_gpu_virtualization_table(adev))
> - adev->virtualization.virtual_caps |= 
> AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
> -}
> -
>  static const struct amdgpu_allowed_register_entry 
> tonga_allowed_read_registers[] = {
>   {mmGB_MACROTILE_MODE7, true},
>  };
> @@ -1531,7 +1525,6 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
>   .read_disabled_bios = _read_disabled_bios,
>   .read_bios_from_rom = _read_bios_from_rom,
>   .detect_hw_virtualization = vi_detect_hw_virtualization,
> - .detect_sriov_bios = vi_detect_sriov_bios,
>   .read_register = _read_register,
>   .reset = _asic_reset,
>   .set_vga_state = _vga_set_state,
> 



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Re: [PATCH 1/5] drm/amdgpu/vi: whitespace fixes

[Edward O'Callaghan]

Series is,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 09/20/2016 04:35 AM, Alex Deucher wrote:
> function declaration parens should be a new line.
> 
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/vi.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 5141393..81780f1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -445,7 +445,8 @@ static bool vi_read_bios_from_rom(struct amdgpu_device 
> *adev,
>   return true;
>  }
>  
> -static void vi_detect_hw_virtualization(struct amdgpu_device *adev) {
> +static void vi_detect_hw_virtualization(struct amdgpu_device *adev)
> +{
>   uint32_t reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
>   /* bit0: 0 means pf and 1 means vf */
>   /* bit31: 0 means disable IOV and 1 means enable */
> @@ -461,7 +462,8 @@ static void vi_detect_hw_virtualization(struct 
> amdgpu_device *adev) {
>   }
>  }
>  
> -static void vi_detect_sriov_bios(struct amdgpu_device *adev) {
> +static void vi_detect_sriov_bios(struct amdgpu_device *adev)
> +{
>   if (amdgpu_atombios_has_gpu_virtualization_table(adev))
>   adev->virtualization.virtual_caps |= 
> AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
>  }
> 



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Re: [PATCH] drm/amdgpu: use powerplay module for dgpu of VI.

[Edward O'Callaghan]

So now just pure PP paths for Tonga, Fiji & Topaz. Is there any perf or
power usage difference from this change-set across any of these ASIC's?

Acked-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 09/19/2016 10:17 PM, Rex Zhu wrote:
> delete vi dpm related code and files.
> 
> Change-Id: I080de47df12d45be06a72fe229695675cf6648d6
> Signed-off-by: Rex Zhu <rex@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/Makefile   |   5 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c |  13 +-
>  drivers/gpu/drm/amd/amdgpu/fiji_dpm.c | 186 --
>  drivers/gpu/drm/amd/amdgpu/fiji_smc.c | 863 
> --
>  drivers/gpu/drm/amd/amdgpu/fiji_smum.h|  42 --
>  drivers/gpu/drm/amd/amdgpu/iceland_dpm.c  | 200 --
>  drivers/gpu/drm/amd/amdgpu/iceland_smc.c  | 677 
>  drivers/gpu/drm/amd/amdgpu/iceland_smum.h |  41 --
>  drivers/gpu/drm/amd/amdgpu/tonga_dpm.c| 186 --
>  drivers/gpu/drm/amd/amdgpu/tonga_smc.c| 862 -
>  drivers/gpu/drm/amd/amdgpu/tonga_smum.h   |  42 --
>  drivers/gpu/drm/amd/amdgpu/vi.c   |   3 +
>  12 files changed, 6 insertions(+), 3114 deletions(-)
>  delete mode 100644 drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
>  delete mode 100644 drivers/gpu/drm/amd/amdgpu/fiji_smc.c
>  delete mode 100644 drivers/gpu/drm/amd/amdgpu/fiji_smum.h
>  delete mode 100644 drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
>  delete mode 100644 drivers/gpu/drm/amd/amdgpu/iceland_smc.c
>  delete mode 100644 drivers/gpu/drm/amd/amdgpu/iceland_smum.h
>  delete mode 100644 drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
>  delete mode 100644 drivers/gpu/drm/amd/amdgpu/tonga_smc.c
>  delete mode 100644 drivers/gpu/drm/amd/amdgpu/tonga_smum.h
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index f2b97cb..786b28a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -59,10 +59,7 @@ amdgpu-y += \
>  amdgpu-y += \
>   amdgpu_dpm.o \
>   amdgpu_powerplay.o \
> - cz_smc.o cz_dpm.o \
> - tonga_smc.o tonga_dpm.o \
> - fiji_smc.o fiji_dpm.o \
> - iceland_smc.o iceland_dpm.o
> + cz_smc.o cz_dpm.o
>  
>  # add DCE block
>  amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> index 1e7f160..68ad241 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> @@ -80,15 +80,6 @@ static int amdgpu_powerplay_init(struct amdgpu_device 
> *adev)
>   amd_pp->ip_funcs = _dpm_ip_funcs;
>   break;
>  #endif
> - case CHIP_TOPAZ:
> - amd_pp->ip_funcs = _dpm_ip_funcs;
> - break;
> - case CHIP_TONGA:
> - amd_pp->ip_funcs = _dpm_ip_funcs;
> - break;
> - case CHIP_FIJI:
> - amd_pp->ip_funcs = _dpm_ip_funcs;
> - break;
>   case CHIP_CARRIZO:
>   case CHIP_STONEY:
>   amd_pp->ip_funcs = _dpm_ip_funcs;
> @@ -110,11 +101,11 @@ static int amdgpu_pp_early_init(void *handle)
>   switch (adev->asic_type) {
>   case CHIP_POLARIS11:
>   case CHIP_POLARIS10:
> - adev->pp_enabled = true;
> - break;
>   case CHIP_TONGA:
>   case CHIP_FIJI:
>   case CHIP_TOPAZ:
> + adev->pp_enabled = true;
> + break;
>   case CHIP_CARRIZO:
>   case CHIP_STONEY:
>   adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
> diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c 
> b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
> deleted file mode 100644
> index ed03b75..000
> --- a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
> +++ /dev/null
> @@ -1,186 +0,0 @@
> -/*
> - * Copyright 2014 Advanced Micro Devices, Inc.
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE S

Re: [PATCH 0/3] drm/amdgpu: implement raster configuration

[Edward O'Callaghan]

This series is,
Acked-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 09/18/2016 12:36 PM, Huang Rui wrote:
> Hi all,
> 
> This patch set is to introduce the raster configuration for all gfx
> generations.
> 
> Thanks,
> Rui
> 
> Huang Rui (3):
>   drm/amdgpu: implement raster configuration for gfx v6
>   drm/amdgpu: implement raster configuration for gfx v7
>   drm/amdgpu: implement raster configuration for gfx v8
> 
>  drivers/gpu/drm/amd/amdgpu/cikd.h |  36 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 133 +++-
>  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 160 +++-
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 168 
> +-
>  drivers/gpu/drm/amd/amdgpu/vid.h  |  37 ++
>  drivers/gpu/drm/amd/include/asic_reg/si/sid.h |  35 ++
>  6 files changed, 566 insertions(+), 3 deletions(-)
> 



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[PATCH 5/6] drm/amdkfd: Unify multiple calls to pr_debug() into one

[Edward O'Callaghan]

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
index a7d3cb3..453c5d6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
@@ -142,13 +142,15 @@ int kfd_doorbell_mmap(struct kfd_process *process, struct 
vm_area_struct *vma)
 
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 
-   pr_debug("mapping doorbell page:\n");
-   pr_debug(" target user address == 0x%08llX\n",
-   (unsigned long long) vma->vm_start);
-   pr_debug(" physical address== 0x%08llX\n", address);
-   pr_debug(" vm_flags== 0x%04lX\n", vma->vm_flags);
-   pr_debug(" size== 0x%04lX\n",
-doorbell_process_allocation());
+   pr_debug("kfd: mapping doorbell page in %s\n"
+" target user address == 0x%08llX\n"
+" physical address== 0x%08llX\n"
+" vm_flags== 0x%04lX\n"
+" size== 0x%04lX\n",
+__func__,
+(unsigned long long) vma->vm_start, address, vma->vm_flags,
+doorbell_process_allocation());
+
 
return io_remap_pfn_range(vma,
vma->vm_start,
-- 
2.7.4

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[PATCH 4/6] drm/amdkfd: Fix possible infinite loop

[Edward O'Callaghan]

When the loop predicating timeout parameter passed happens to
not be a multiple of 20 the unsigned integer will overflow and
the loop will become unbounded.

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
Reviewed-by: Oded Gabbay <oded.gab...@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 17 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 17 +
 2 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 362bedc..1a0a5f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -103,11 +103,11 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, 
uint64_t queue_address,
uint32_t pipe_id, uint32_t queue_id);
 
 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
-   unsigned int timeout, uint32_t pipe_id,
+   unsigned int utimeout, uint32_t pipe_id,
uint32_t queue_id);
 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
-   unsigned int timeout);
+   unsigned int utimeout);
 static int kgd_address_watch_disable(struct kgd_dev *kgd);
 static int kgd_address_watch_execute(struct kgd_dev *kgd,
unsigned int watch_point_id,
@@ -437,11 +437,12 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, 
void *mqd)
 }
 
 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
-   unsigned int timeout, uint32_t pipe_id,
+   unsigned int utimeout, uint32_t pipe_id,
uint32_t queue_id)
 {
struct amdgpu_device *adev = get_amdgpu_device(kgd);
uint32_t temp;
+   int timeout = utimeout;
 
acquire_queue(kgd, pipe_id, queue_id);
WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
@@ -452,9 +453,8 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t 
reset_type,
temp = RREG32(mmCP_HQD_ACTIVE);
if (temp & CP_HQD_ACTIVE__ACTIVE_MASK)
break;
-   if (timeout == 0) {
-   pr_err("kfd: cp queue preemption time out (%dms)\n",
-   temp);
+   if (timeout <= 0) {
+   pr_err("kfd: cp queue preemption time out.\n");
release_queue(kgd);
return -ETIME;
}
@@ -467,12 +467,13 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t 
reset_type,
 }
 
 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
-   unsigned int timeout)
+   unsigned int utimeout)
 {
struct amdgpu_device *adev = get_amdgpu_device(kgd);
struct cik_sdma_rlc_registers *m;
uint32_t sdma_base_addr;
uint32_t temp;
+   int timeout = utimeout;
 
m = get_sdma_mqd(mqd);
sdma_base_addr = get_sdma_base_addr(m);
@@ -485,7 +486,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void 
*mqd,
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
break;
-   if (timeout == 0)
+   if (timeout <= 0)
return -ETIME;
msleep(20);
timeout -= 20;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 04b744d..6697612 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -62,10 +62,10 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, 
uint64_t queue_address,
uint32_t pipe_id, uint32_t queue_id);
 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
-   unsigned int timeout, uint32_t pipe_id,
+   unsigned int utimeout, uint32_t pipe_id,
uint32_t queue_id);
 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
-   unsigned int timeout);
+   unsigned int utimeout);
 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
 static int kgd_address_watch_disable(struct kgd_dev *kgd);
 static int kgd_address_watch_execute(struct kgd_dev *kgd,
@@ -349,11 +349,12 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, 
void

[PATCH 1/6] drm/amdkfd: Tidy up kfd_generate_gpu_id() uint64_t bitshift unpack

[Edward O'Callaghan]

Dereference the one time and unpack the lower and upper 32bit
portions with the proper kernel helper macros.

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
Reviewed-by: Oded Gabbay <oded.gab...@gmail.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 884c96f..1e50647 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1090,19 +1090,21 @@ static uint32_t kfd_generate_gpu_id(struct kfd_dev *gpu)
 {
uint32_t hashout;
uint32_t buf[7];
+   uint64_t local_mem_size;
int i;
 
if (!gpu)
return 0;
 
+   local_mem_size = gpu->kfd2kgd->get_vmem_size(gpu->kgd);
+
buf[0] = gpu->pdev->devfn;
buf[1] = gpu->pdev->subsystem_vendor;
buf[2] = gpu->pdev->subsystem_device;
buf[3] = gpu->pdev->device;
buf[4] = gpu->pdev->bus->number;
-   buf[5] = (uint32_t)(gpu->kfd2kgd->get_vmem_size(gpu->kgd)
-   & 0x);
-   buf[6] = (uint32_t)(gpu->kfd2kgd->get_vmem_size(gpu->kgd) >> 32);
+   buf[5] = lower_32_bits(local_mem_size);
+   buf[6] = upper_32_bits(local_mem_size);
 
for (i = 0, hashout = 0; i < 7; i++)
hashout ^= hash_32(buf[i], KFD_GPU_ID_HASH_WIDTH);
-- 
2.7.4

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[PATCH 2/6] drm/amdkfd: Add some missing memset zero'ing in queue init func

[Edward O'Callaghan]

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
Reviewed-by: Oded Gabbay <oded.gab...@gmail.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 9beae87..291c69d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -47,6 +47,9 @@ static bool initialize(struct kernel_queue *kq, struct 
kfd_dev *dev,
pr_debug("amdkfd: In func %s initializing queue type %d size %d\n",
__func__, KFD_QUEUE_TYPE_HIQ, queue_size);
 
+   memset(, 0, sizeof(prop));
+   memset(, 0, sizeof(nop));
+
nop.opcode = IT_NOP;
nop.type = PM4_TYPE_3;
nop.u32all |= PM4_COUNT_ZERO;
-- 
2.7.4

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drm/amdkfd: Misc patchset lineup for drm-next-4.9

[Edward O'Callaghan]

Hi,

Most of these have already been reviewed and some of the more
invasive patches have been dropped from the orginal series. As
I wish to get the low hanging fruit out the way as quickly as
possible. I shall try to find the time this weekend to prepare
the second more interesting set but don't wait up.

Please review..
Kind Regards,

Edward O'Callaghan (6):
 [PATCH 1/6] drm/amdkfd: Tidy up kfd_generate_gpu_id() uint64_t
 [PATCH 2/6] drm/amdkfd: Add some missing memset zero'ing in queue
 [PATCH 3/6] drm/amdkfd: Reuse function to find a process through
 [PATCH 4/6] drm/amdkfd: Fix possible infinite loop
 [PATCH 5/6] drm/amdkfd: Unify multiple calls to pr_debug() into one
 [PATCH 6/6] drm/amdkfd: Pass 'struct queue_propertices' by reference
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[PATCH 6/6] drm/amdkfd: Pass 'struct queue_propertices' by reference

[Edward O'Callaghan]

Allow init_queue() to take 'struct queue_properties' by reference.

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c  | 2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  | 2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_queue.c | 4 ++--
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 291c69d..d135cd0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -124,7 +124,7 @@ static bool initialize(struct kernel_queue *kq, struct 
kfd_dev *dev,
prop.eop_ring_buffer_address = kq->eop_gpu_addr;
prop.eop_ring_buffer_size = PAGE_SIZE;
 
-   if (init_queue(>queue, prop) != 0)
+   if (init_queue(>queue, ) != 0)
goto err_init_queue;
 
kq->queue->device = dev;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 80113c3..4750cab 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -619,7 +619,7 @@ int kfd_init_apertures(struct kfd_process *process);
 /* Queue Context Management */
 struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd);
 
-int init_queue(struct queue **q, struct queue_properties properties);
+int init_queue(struct queue **q, const struct queue_properties *properties);
 void uninit_queue(struct queue *q);
 void print_queue_properties(struct queue_properties *q);
 void print_queue(struct queue *q);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index 7b69070..e1fb40b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -129,7 +129,7 @@ static int create_cp_queue(struct process_queue_manager 
*pqm,
q_properties->vmid = 0;
q_properties->queue_id = qid;
 
-   retval = init_queue(q, *q_properties);
+   retval = init_queue(q, q_properties);
if (retval != 0)
goto err_init_queue;
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_queue.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_queue.c
index 9a0c90b..0ab1970 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_queue.c
@@ -63,7 +63,7 @@ void print_queue(struct queue *q)
pr_debug("Queue Device Address: 0x%p\n", q->device);
 }
 
-int init_queue(struct queue **q, struct queue_properties properties)
+int init_queue(struct queue **q, const struct queue_properties *properties)
 {
struct queue *tmp;
 
@@ -73,7 +73,7 @@ int init_queue(struct queue **q, struct queue_properties 
properties)
if (!tmp)
return -ENOMEM;
 
-   memcpy(>properties, , sizeof(struct queue_properties));
+   memcpy(>properties, properties, sizeof(struct queue_properties));
 
*q = tmp;
return 0;
-- 
2.7.4

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Re: Powerplay sensors (v2.5)

[Edward O'Callaghan]

This series is,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 09/16/2016 10:44 PM, Tom St Denis wrote:
> I've rebased the backend to squash the carrizo + rest patches together
> and then touched up the debugfs entry per Edwards suggestions.
> 
> Tested on Tonga, Carrizo, and Stoney.
> 
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Re: [PATCH 1/3] drm/amdgpu: cleanup VM shadow BO unreferencing

[Edward O'Callaghan]

Series is,
Acked-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 09/16/2016 10:12 PM, Christian König wrote:
> From: Christian König <christian.koe...@amd.com>
> 
> Unreference the shadow BOs in the error path as well and drop the NULL checks.
> 
> Signed-off-by: Christian König <christian.koe...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 ++--
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 8928a2a..19c7bf7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -1429,6 +1429,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
>  
>   r = amdgpu_vm_clear_bo(adev, vm, pt);
>   if (r) {
> + amdgpu_bo_unref(>shadow);
>   amdgpu_bo_unref();
>   goto error_free;
>   }
> @@ -1635,6 +1636,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
> amdgpu_vm *vm)
>   return 0;
>  
>  error_free_page_directory:
> + amdgpu_bo_unref(>page_directory->shadow);
>   amdgpu_bo_unref(>page_directory);
>   vm->page_directory = NULL;
>  
> @@ -1677,15 +1679,17 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, 
> struct amdgpu_vm *vm)
>   }
>  
>   for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) {
> - if (vm->page_tables[i].entry.robj &&
> - vm->page_tables[i].entry.robj->shadow)
> - amdgpu_bo_unref(>page_tables[i].entry.robj->shadow);
> - amdgpu_bo_unref(>page_tables[i].entry.robj);
> + struct amdgpu_bo *pt = vm->page_tables[i].entry.robj;
> +
> + if (!pt)
> + continue;
> +
> + amdgpu_bo_unref(>shadow);
> + amdgpu_bo_unref();
>   }
>   drm_free_large(vm->page_tables);
>  
> - if (vm->page_directory->shadow)
> - amdgpu_bo_unref(>page_directory->shadow);
> + amdgpu_bo_unref(>page_directory->shadow);
>   amdgpu_bo_unref(>page_directory);
>   fence_put(vm->page_directory_fence);
>  }
> 



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Re: libdrm/amdgpu - Fixup typedef not to hide pointer type

[Edward O'Callaghan]

Hi Christian,

On 09/16/2016 06:49 PM, Christian König wrote:
> NAK, that is clearly an API breakage.

It should have never been typedef'ed in the first place. Does that mean
we would have to bump version for API change? What is the procedure there?

> 
> BTW: Why would we want to stop hiding the type?

Quite a few reasons, I'll start with to justify the change:

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/CodingStyle?id=refs/tags/v4.8-rc6#n276

Suppose you have 'amdgpu_semaphore_handle' as typedef of a pointer type
and you had some function 'void f(amdgpu_semaphore_handle * h) {}'.
Suppose now, within 'f()' we deference 'h' and use the result in some
way. The issue is that it is not directly obvious that we have a double
pointer type and so while it maybe the case that '(*h != NULL)' it could
well be the case that '(h == NULL)'.

Kind Regards,
Edward.

> 
> Christian.
> 
> Am 16.09.2016 um 10:46 schrieb Edward O'Callaghan:
>> Oops, turns out I mailed to dri-devel by mistake so resending here.
>>
>> The following series fixes up libdrm/amdgpu such that to not hide
>> a pointer type behind a typedef.
>>
>> Please Review,
>>
>> Edward O'Callaghan (3):
>>   [PATCH 1/3] amdgpu: Fix amdgpu_va_handle typedef not to hide pointer
>>   [PATCH 2/3] amdgpu: Fix amdgpu_semaphore_handle typedef not to hide
>>   [PATCH 3/3] amdgpu: Fix amdgpu_bo_list_handle typedef not to hide
>> ___
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> 
> 



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[PATCH 2/3] amdgpu: Fix amdgpu_semaphore_handle typedef not to hide pointer type

[Edward O'Callaghan]

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 amdgpu/amdgpu.h| 10 +-
 amdgpu/amdgpu_cs.c | 20 ++--
 tests/amdgpu/basic_tests.c |  2 +-
 3 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index f322497..9332fab 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -127,7 +127,7 @@ typedef struct amdgpu_va amdgpu_va_handle_t;
 /**
  * Define handle for semaphore
  */
-typedef struct amdgpu_semaphore *amdgpu_semaphore_handle;
+typedef struct amdgpu_semaphore amdgpu_semaphore_handle_t;
 
 /*--*/
 /* -- Structures -- */
@@ -1194,7 +1194,7 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
  *  <0 - Negative POSIX Error code
  *
 */
-int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem);
+int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle_t ** sem);
 
 /**
  *  signal semaphore
@@ -1213,7 +1213,7 @@ int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
   uint32_t ip_type,
   uint32_t ip_instance,
   uint32_t ring,
-  amdgpu_semaphore_handle sem);
+  amdgpu_semaphore_handle_t * sem);
 
 /**
  *  wait semaphore
@@ -1232,7 +1232,7 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
 uint32_t ip_type,
 uint32_t ip_instance,
 uint32_t ring,
-amdgpu_semaphore_handle sem);
+amdgpu_semaphore_handle_t * sem);
 
 /**
  *  destroy semaphore
@@ -1243,6 +1243,6 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
  *  <0 - Negative POSIX Error code
  *
 */
-int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem);
+int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle_t * sem);
 
 #endif /* #ifdef _AMDGPU_H_ */
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index fb5b3a8..c72825a 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -40,8 +40,8 @@
 #include "amdgpu_drm.h"
 #include "amdgpu_internal.h"
 
-static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem);
-static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem);
+static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle_t * sem);
+static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle_t * sem);
 
 /**
  * Create command submission context
@@ -124,7 +124,7 @@ int amdgpu_cs_ctx_free(amdgpu_context_handle context)
for (i = 0; i < AMDGPU_HW_IP_NUM; i++) {
for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++) {
for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++) {
-   amdgpu_semaphore_handle sem;
+   amdgpu_semaphore_handle_t * sem;
LIST_FOR_EACH_ENTRY(sem, 
>sem_list[i][j][k], list) {
list_del(>list);
amdgpu_cs_reset_sem(sem);
@@ -179,7 +179,7 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle 
context,
struct drm_amdgpu_cs_chunk_dep *dependencies = NULL;
struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
struct list_head *sem_list;
-   amdgpu_semaphore_handle sem, tmp;
+   amdgpu_semaphore_handle_t * sem, * tmp;
uint32_t i, size, sem_count = 0;
bool user_fence;
int r = 0;
@@ -443,7 +443,7 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence 
*fence,
return r;
 }
 
-int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem)
+int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle_t ** sem)
 {
struct amdgpu_semaphore *gpu_semaphore;
 
@@ -464,7 +464,7 @@ int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
   uint32_t ip_type,
   uint32_t ip_instance,
   uint32_t ring,
-  amdgpu_semaphore_handle sem)
+  amdgpu_semaphore_handle_t * sem)
 {
if (NULL == ctx)
return -EINVAL;
@@ -492,7 +492,7 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
 uint32_t ip_type,
 uint32_t ip_instance,
 uint32_t ring,
-amdgpu_semaphore_handle sem)
+amdgpu_semaphore_handle_t * sem)
 {
if (NULL == ctx)
return -EINVAL;
@@ -512,7 +512,7 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
return 0;
 }
 
-static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem)
+static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle_t * sem)
 {

[PATCH 3/3] amdgpu: Fix amdgpu_bo_list_handle typedef not to hide pointer type

[Edward O'Callaghan]

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 amdgpu/amdgpu.h| 10 +-
 amdgpu/amdgpu_bo.c |  6 +++---
 tests/amdgpu/amdgpu_test.h |  2 +-
 tests/amdgpu/basic_tests.c |  8 
 4 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 9332fab..77ddb87 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -117,7 +117,7 @@ typedef struct amdgpu_bo *amdgpu_bo_handle;
 /**
  * Define handle for list of BOs
  */
-typedef struct amdgpu_bo_list *amdgpu_bo_list_handle;
+typedef struct amdgpu_bo_list amdgpu_bo_list_handle_t;
 
 /**
  * Define handle to be used to work with VA allocated ranges
@@ -332,7 +332,7 @@ struct amdgpu_cs_request {
/**
 * List handle with resources used by this request.
 */
-   amdgpu_bo_list_handle resources;
+   amdgpu_bo_list_handle_t * resources;
 
/**
 * Number of dependencies this Command submission needs to
@@ -747,7 +747,7 @@ int amdgpu_bo_list_create(amdgpu_device_handle dev,
  uint32_t number_of_resources,
  amdgpu_bo_handle *resources,
  uint8_t *resource_prios,
- amdgpu_bo_list_handle *result);
+ amdgpu_bo_list_handle_t ** result);
 
 /**
  * Destroys a BO list handle.
@@ -759,7 +759,7 @@ int amdgpu_bo_list_create(amdgpu_device_handle dev,
  *
  * \sa amdgpu_bo_list_create()
 */
-int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle);
+int amdgpu_bo_list_destroy(amdgpu_bo_list_handle_t * handle);
 
 /**
  * Update resources for existing BO list
@@ -774,7 +774,7 @@ int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle);
  *
  * \sa amdgpu_bo_list_update()
 */
-int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
+int amdgpu_bo_list_update(amdgpu_bo_list_handle_t * handle,
  uint32_t number_of_resources,
  amdgpu_bo_handle *resources,
  uint8_t *resource_prios);
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index d30fd1e..e57e733 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -565,7 +565,7 @@ int amdgpu_bo_list_create(amdgpu_device_handle dev,
  uint32_t number_of_resources,
  amdgpu_bo_handle *resources,
  uint8_t *resource_prios,
- amdgpu_bo_list_handle *result)
+ amdgpu_bo_list_handle_t ** result)
 {
struct drm_amdgpu_bo_list_entry *list;
union drm_amdgpu_bo_list args;
@@ -616,7 +616,7 @@ int amdgpu_bo_list_create(amdgpu_device_handle dev,
return 0;
 }
 
-int amdgpu_bo_list_destroy(amdgpu_bo_list_handle list)
+int amdgpu_bo_list_destroy(amdgpu_bo_list_handle_t * list)
 {
union drm_amdgpu_bo_list args;
int r;
@@ -634,7 +634,7 @@ int amdgpu_bo_list_destroy(amdgpu_bo_list_handle list)
return r;
 }
 
-int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
+int amdgpu_bo_list_update(amdgpu_bo_list_handle_t * handle,
  uint32_t number_of_resources,
  amdgpu_bo_handle *resources,
  uint8_t *resource_prios)
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index acf3359..d4f1873 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -226,7 +226,7 @@ amdgpu_bo_unmap_and_free(amdgpu_bo_handle bo, 
amdgpu_va_handle_t * va_handle,
 
 static inline int
 amdgpu_get_bo_list(amdgpu_device_handle dev, amdgpu_bo_handle bo1,
-  amdgpu_bo_handle bo2, amdgpu_bo_list_handle *list)
+  amdgpu_bo_handle bo2, amdgpu_bo_list_handle_t ** list)
 {
amdgpu_bo_handle resources[] = {bo1, bo2};
 
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 7838249..509154c 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -292,7 +292,7 @@ static void amdgpu_command_submission_gfx_separate_ibs(void)
struct amdgpu_cs_fence fence_status = {0};
uint32_t *ptr;
uint32_t expired;
-   amdgpu_bo_list_handle bo_list;
+   amdgpu_bo_list_handle_t * bo_list;
amdgpu_va_handle_t * va_handle, va_handle_ce;
int r;
 
@@ -381,7 +381,7 @@ static void amdgpu_command_submission_gfx_shared_ib(void)
struct amdgpu_cs_fence fence_status = {0};
uint32_t *ptr;
uint32_t expired;
-   amdgpu_bo_list_handle bo_list;
+   amdgpu_bo_list_handle_t * bo_list;
amdgpu_va_handle_t * va_handle;
int r;
 
@@ -488,7 +488,7 @@ static void amdgpu_semaphore_test(void)
struct amdgpu_cs_fence fence_status = {0};
uint32_t *ptr;
uint32_t expired;
-   amdgpu_bo_list_handle bo_list[2];
+   amdgpu_bo_list_handle_t * bo_list[2];
amdgpu_va_handle_t * va_handle[2];
int r, i;
 
@@ -618,7 +618,7 @@ stati

libdrm/amdgpu - Fixup typedef not to hide pointer type

[Edward O'Callaghan]

Oops, turns out I mailed to dri-devel by mistake so resending here.

The following series fixes up libdrm/amdgpu such that to not hide
a pointer type behind a typedef.

Please Review,

Edward O'Callaghan (3):
 [PATCH 1/3] amdgpu: Fix amdgpu_va_handle typedef not to hide pointer
 [PATCH 2/3] amdgpu: Fix amdgpu_semaphore_handle typedef not to hide
 [PATCH 3/3] amdgpu: Fix amdgpu_bo_list_handle typedef not to hide
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[PATCH 1/3] amdgpu: Fix amdgpu_va_handle typedef not to hide pointer type

[Edward O'Callaghan]

Fundamentally this change stops us hiding the following pointer
type behind a typedef:

 -typedef struct amdgpu_va *amdgpu_va_handle;
 +typedef struct amdgpu_va amdgpu_va_handle_t;

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 amdgpu/amdgpu.h|  6 +++---
 amdgpu/amdgpu_vamgr.c  |  4 ++--
 tests/amdgpu/amdgpu_test.h | 10 +-
 tests/amdgpu/basic_tests.c | 20 ++--
 tests/amdgpu/bo_tests.c|  2 +-
 tests/amdgpu/cs_tests.c| 10 +-
 tests/amdgpu/vce_tests.c   |  6 +++---
 7 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 5d5a2c6..f322497 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -122,7 +122,7 @@ typedef struct amdgpu_bo_list *amdgpu_bo_list_handle;
 /**
  * Define handle to be used to work with VA allocated ranges
  */
-typedef struct amdgpu_va *amdgpu_va_handle;
+typedef struct amdgpu_va amdgpu_va_handle_t;
 
 /**
  * Define handle for semaphore
@@ -1126,7 +1126,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev,
   uint64_t va_base_alignment,
   uint64_t va_base_required,
   uint64_t *va_base_allocated,
-  amdgpu_va_handle *va_range_handle,
+  amdgpu_va_handle_t ** va_range_handle,
   uint64_t flags);
 
 /**
@@ -1140,7 +1140,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev,
  * <0 - Negative POSIX Error code
  *
 */
-int amdgpu_va_range_free(amdgpu_va_handle va_range_handle);
+int amdgpu_va_range_free(amdgpu_va_handle_t * va_range_handle);
 
 /**
 * Query virtual address range
diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c
index 8a707cb..7fae7cf 100644
--- a/amdgpu/amdgpu_vamgr.c
+++ b/amdgpu/amdgpu_vamgr.c
@@ -230,7 +230,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev,
  uint64_t va_base_alignment,
  uint64_t va_base_required,
  uint64_t *va_base_allocated,
- amdgpu_va_handle *va_range_handle,
+ amdgpu_va_handle_t ** va_range_handle,
  uint64_t flags)
 {
struct amdgpu_bo_va_mgr *vamgr;
@@ -274,7 +274,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev,
return 0;
 }
 
-int amdgpu_va_range_free(amdgpu_va_handle va_range_handle)
+int amdgpu_va_range_free(amdgpu_va_handle_t * va_range_handle)
 {
if(!va_range_handle || !va_range_handle->address)
return 0;
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index fca92ad..acf3359 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -111,7 +111,7 @@ static inline amdgpu_bo_handle gpu_mem_alloc(
uint32_t type,
uint64_t flags,
uint64_t *vmc_addr,
-   amdgpu_va_handle *va_handle)
+   amdgpu_va_handle_t ** va_handle)
 {
struct amdgpu_bo_alloc_request req = {0};
amdgpu_bo_handle buf_handle;
@@ -140,7 +140,7 @@ static inline amdgpu_bo_handle gpu_mem_alloc(
 }
 
 static inline int gpu_mem_free(amdgpu_bo_handle bo,
-  amdgpu_va_handle va_handle,
+  amdgpu_va_handle_t * va_handle,
   uint64_t vmc_addr,
   uint64_t size)
 {
@@ -162,11 +162,11 @@ static inline int
 amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size,
unsigned alignment, unsigned heap, uint64_t flags,
amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address,
-   amdgpu_va_handle *va_handle)
+   amdgpu_va_handle_t ** va_handle)
 {
struct amdgpu_bo_alloc_request request = {};
amdgpu_bo_handle buf_handle;
-   amdgpu_va_handle handle;
+   amdgpu_va_handle_t * handle;
uint64_t vmc_addr;
int r;
 
@@ -212,7 +212,7 @@ error_va_alloc:
 }
 
 static inline int
-amdgpu_bo_unmap_and_free(amdgpu_bo_handle bo, amdgpu_va_handle va_handle,
+amdgpu_bo_unmap_and_free(amdgpu_bo_handle bo, amdgpu_va_handle_t * va_handle,
 uint64_t mc_addr, uint64_t size)
 {
amdgpu_bo_cpu_unmap(bo);
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 11f6a63..40e9ef1 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -237,7 +237,7 @@ static void amdgpu_query_info_test(void)
 static void amdgpu_memory_alloc(void)
 {
amdgpu_bo_handle bo;
-   amdgpu_va_handle va_handle;
+   amdgpu_va_handle_t * va_handle;
uint64_t bo_mc;
int r;
 
@@ -293,7 +293,7 @@ static void amdgpu_command_submission_gfx_separate_ibs(void)
uint32_t *ptr;
uint

Re: [PATCH 1/3] drm/amdgpu/gfx6: drop duplicate code

[Edward O'Callaghan]

This series is,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

P.S., keep these hedge cuttings coming!

On 09/16/2016 05:55 AM, Alex Deucher wrote:
> The compute functions just called the gfx functions, drop
> the wrapper.
> 
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 33 +
>  1 file changed, 9 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 9697994..3cf4e9e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -1324,8 +1324,8 @@ static void gfx_v6_0_ring_emit_hdp_invalidate(struct 
> amdgpu_ring *ring)
>   amdgpu_ring_write(ring, 0x1);
>  }
>  
> -static void gfx_v6_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
> -  u64 seq, unsigned flags)
> +static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
> +  u64 seq, unsigned flags)
>  {
>   bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
>   bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
> @@ -1351,17 +1351,9 @@ static void gfx_v6_0_ring_emit_fence_gfx(struct 
> amdgpu_ring *ring, u64 addr,
>   amdgpu_ring_write(ring, upper_32_bits(seq));
>  }
>  
> -static void gfx_v6_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
> -  u64 addr, u64 seq,
> -  unsigned flags)
> -{
> - gfx_v6_0_ring_emit_fence_gfx(ring, addr, seq, flags);
> -}
> -
> -
> -static void gfx_v6_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
> -   struct amdgpu_ib *ib,
> -   unsigned vm_id, bool ctx_switch)
> +static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
> +   struct amdgpu_ib *ib,
> +   unsigned vm_id, bool ctx_switch)
>  {
>   u32 header, control = 0;
>  
> @@ -1388,13 +1380,6 @@ static void gfx_v6_0_ring_emit_ib_gfx(struct 
> amdgpu_ring *ring,
>   amdgpu_ring_write(ring, control);
>  }
>  
> -static void gfx_v6_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
> -   struct amdgpu_ib *ib,
> -   unsigned vm_id, bool ctx_switch)
> -{
> - gfx_v6_0_ring_emit_ib_gfx(ring, ib, vm_id, ctx_switch);
> -}
> -
>  /**
>   * gfx_v6_0_ring_test_ib - basic ring IB test
>   *
> @@ -3119,8 +3104,8 @@ static const struct amdgpu_ring_funcs 
> gfx_v6_0_ring_funcs_gfx = {
>   .get_wptr = gfx_v6_0_ring_get_wptr,
>   .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
>   .parse_cs = NULL,
> - .emit_ib = gfx_v6_0_ring_emit_ib_gfx,
> - .emit_fence = gfx_v6_0_ring_emit_fence_gfx,
> + .emit_ib = gfx_v6_0_ring_emit_ib,
> + .emit_fence = gfx_v6_0_ring_emit_fence,
>   .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
>   .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
>   .emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
> @@ -3136,8 +3121,8 @@ static const struct amdgpu_ring_funcs 
> gfx_v6_0_ring_funcs_compute = {
>   .get_wptr = gfx_v6_0_ring_get_wptr,
>   .set_wptr = gfx_v6_0_ring_set_wptr_compute,
>   .parse_cs = NULL,
> - .emit_ib = gfx_v6_0_ring_emit_ib_compute,
> - .emit_fence = gfx_v6_0_ring_emit_fence_compute,
> + .emit_ib = gfx_v6_0_ring_emit_ib,
> + .emit_fence = gfx_v6_0_ring_emit_fence,
>   .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
>   .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
>   .emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
> 



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Re: [PATCH] drm/amd/amdgpu: Add sensors debugfs support

[Edward O'Callaghan]

On 09/15/2016 11:22 PM, Tom St Denis wrote:
> This patch adds a callback to powerplay which
> reads specific PP sensors (vdd/clocks/load) which is then
> accessible via debugfs.  The idea being is it'll be a standard
> interface between different ASICs that userland tools can
> read.
> 
> Currently only CZ/ST is supported but the others are
> NULL'ed off so they shouldn't cause any sort of oops.
> 
> Signed-off-by: Tom St Denis 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 +++
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 20 +
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 96 
> ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   |  1 +
>  .../gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c|  1 +
>  .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  |  1 +
>  drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  |  1 +
>  drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  | 10 +++
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  1 +
>  9 files changed, 162 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 9103e7baf26e..b6a4588c95ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2841,6 +2841,29 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct 
> file *f, char __user *buf,
>   return result;
>  }
>  
> +static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
> + size_t size, loff_t *pos)
> +{
> + struct amdgpu_device *adev = f->f_inode->i_private;
> + int r;
> + int32_t value;
> +
> + if (size != 4 || *pos & 0x3)

Just some minor questions,

maybe I miss-read but maybe dereference pos the once and have it const?

> + return -EINVAL;
> +
> + /* convert offset to sensor number */
> + *pos >>= 2;
Is the intent here just a local mutation or a in-place global state
transition?

Kind Regards,
Edward.

> +
> + if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
> + r = 
> adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, *pos, 
> );
> + else
> + r = -EINVAL;
> +
> + if (!r)
> + r = put_user(value, (int32_t *)buf);
> +
> + return !r ? 4 : r;
> +}
>  
>  static const struct file_operations amdgpu_debugfs_regs_fops = {
>   .owner = THIS_MODULE,
> @@ -2873,12 +2896,19 @@ static const struct file_operations 
> amdgpu_debugfs_gca_config_fops = {
>   .llseek = default_llseek
>  };
>  
> +static const struct file_operations amdgpu_debugfs_sensors_fops = {
> + .owner = THIS_MODULE,
> + .read = amdgpu_debugfs_sensor_read,
> + .llseek = default_llseek
> +};
> +
>  static const struct file_operations *debugfs_regs[] = {
>   _debugfs_regs_fops,
>   _debugfs_regs_didt_fops,
>   _debugfs_regs_pcie_fops,
>   _debugfs_regs_smc_fops,
>   _debugfs_gca_config_fops,
> + _debugfs_sensors_fops,
>  };
>  
>  static const char *debugfs_regs_names[] = {
> @@ -2887,6 +2917,7 @@ static const char *debugfs_regs_names[] = {
>   "amdgpu_regs_pcie",
>   "amdgpu_regs_smc",
>   "amdgpu_gca_config",
> + "amdgpu_sensors",
>  };
>  
>  static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index b1d19409bf86..ee0368381e82 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -894,6 +894,25 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t 
> value)
>   return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
>  }
>  
> +static int pp_dpm_read_sensor(void *handle, int idx, int32_t *value)
> +{
> + struct pp_hwmgr *hwmgr;
> +
> + if (!handle)
> + return -EINVAL;
> +
> + hwmgr = ((struct pp_instance *)handle)->hwmgr;
> +
> + PP_CHECK_HW(hwmgr);
> +
> + if (hwmgr->hwmgr_func->read_sensor == NULL) {
> + printk(KERN_INFO "%s was not implemented.\n", __func__);
> + return 0;
> + }
> +
> + return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value);
> +}
> +
>  const struct amd_powerplay_funcs pp_dpm_funcs = {
>   .get_temperature = pp_dpm_get_temperature,
>   .load_firmware = pp_dpm_load_fw,
> @@ -920,6 +939,7 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {
>   .set_sclk_od = pp_dpm_set_sclk_od,
>   .get_mclk_od = pp_dpm_get_mclk_od,
>   .set_mclk_od = pp_dpm_set_mclk_od,
> + .read_sensor = pp_dpm_read_sensor,
>  };
>  
>  static int amd_pp_instance_init(struct amd_pp_init *pp_init,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index 5ecef1732e20..9f3c5a8a903c 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c

Re: Add read_sensor() support for fiji/tonga/iceland/polaris10

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 09/16/2016 04:21 AM, Tom St Denis wrote:
> Tested on my Tonga but should in theory work for the others as 
> well since they're 99% copy/paste (except which SMC reg is read
> for GPU load...)
> 
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Re: [PATCH 0/3] rename file name.

[Edward O'Callaghan]

This series is,
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>

On 09/12/2016 06:22 PM, Rex Zhu wrote:
> As tonga/fiji/polaris10/11 use ppt table version 1.
> so rename tonga_processtable to process_pptables_v1_0 
> 
> 
> Rex Zhu (3):
>   drm/amd/powerplay: rename tonga_processpptable* to
> processpptable_v1_0*.
>   drm/amd/powerplay: add pp_table_version in hwmgr.
>   drm/amd/powerplay: add pptable point check before use it
> 
>  drivers/gpu/drm/amd/powerplay/hwmgr/Makefile   |2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   |   10 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c|4 +-
>  .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  |   10 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h |  436 +++
>  .../amd/powerplay/hwmgr/process_pptables_v1_0.c| 1326 
> 
>  .../amd/powerplay/hwmgr/process_pptables_v1_0.h|   35 +
>  drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  |   10 +-
>  .../gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h|  436 ---
>  .../amd/powerplay/hwmgr/tonga_processpptables.c| 1326 
> 
>  .../amd/powerplay/hwmgr/tonga_processpptables.h|   35 -
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |8 +
>  12 files changed, 1824 insertions(+), 1814 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h
>  create mode 100644 
> drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
>  create mode 100644 
> drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.h
>  delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
>  delete mode 100644 
> drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
>  delete mode 100644 
> drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.h
> 



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Re: [PATCH 4/7] drm/amdkfd: Make kfd_lookup_process_by_pasid() well defined

[Edward O'Callaghan]

On 09/11/2016 01:55 AM, Oded Gabbay wrote:
> On Sat, Sep 10, 2016 at 4:31 AM, Edward O'Callaghan
> <funfunc...@folklore1984.net> wrote:
>> Ensure we return a NULL on the fail branch so that the call
>> site may BUG_ON() it.
>>
>> Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
>> ---
>>  drivers/gpu/drm/amd/amdkfd/kfd_process.c | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
>> b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
>> index 4f3849a..8d78052 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
>> @@ -481,13 +481,14 @@ bool kfd_has_process_device_data(struct kfd_process *p)
>>  /* This returns with process->mutex locked. */
>>  struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid)
>>  {
>> -   struct kfd_process *p;
>> +   struct kfd_process *p, *ret_p = NULL;
>> unsigned int temp;
>>
>> int idx = srcu_read_lock(_processes_srcu);
>>
>> hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
>> if (p->pasid == pasid) {
>> +   ret_p = p;
>> mutex_lock(>mutex);
>> break;
>> }
>> @@ -495,5 +496,5 @@ struct kfd_process *kfd_lookup_process_by_pasid(unsigned 
>> int pasid)
>>
>> srcu_read_unlock(_processes_srcu, idx);
>>
>> -   return p;
>> +   return ret_p;
>>  }
>> --
>> 2.7.4
>>
>> ___
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> 
> This patch is not needed. p will always be a valid pointer on return or NULL.
> Unless we hit the "p->pasid == pasid" condition, in which case p is
> valid, p will always be NULL when finishing the hash_for_each_rcu
> macro.

Ah you are correct, I didn't notice it was initialized inside the macro.

> 
> Oded
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[PATCH 7/7] drm/amdkfd: Fix possible infinite loop

[Edward O'Callaghan]

When the loop predicating timeout parameter passed happens to
not be a multiple of 20 the unsigned integer will overflow and
the loop will become unbounded.

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 17 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 17 +
 2 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index dc69cf7..b0485b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -103,11 +103,11 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, 
uint64_t queue_address,
uint32_t pipe_id, uint32_t queue_id);
 
 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
-   unsigned int timeout, uint32_t pipe_id,
+   unsigned int utimeout, uint32_t pipe_id,
uint32_t queue_id);
 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
-   unsigned int timeout);
+   unsigned int utimeout);
 static int kgd_address_watch_disable(struct kgd_dev *kgd);
 static int kgd_address_watch_execute(struct kgd_dev *kgd,
unsigned int watch_point_id,
@@ -437,11 +437,12 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, 
void *mqd)
 }
 
 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
-   unsigned int timeout, uint32_t pipe_id,
+   unsigned int utimeout, uint32_t pipe_id,
uint32_t queue_id)
 {
struct amdgpu_device *adev = get_amdgpu_device(kgd);
uint32_t temp;
+   int timeout = utimeout;
 
acquire_queue(kgd, pipe_id, queue_id);
WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
@@ -452,9 +453,8 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t 
reset_type,
temp = RREG32(mmCP_HQD_ACTIVE);
if (temp & CP_HQD_ACTIVE__ACTIVE_MASK)
break;
-   if (timeout == 0) {
-   pr_err("kfd: cp queue preemption time out (%dms)\n",
-   temp);
+   if (timeout <= 0) {
+   pr_err("kfd: cp queue preemption time out.\n");
release_queue(kgd);
return -ETIME;
}
@@ -467,12 +467,13 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t 
reset_type,
 }
 
 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
-   unsigned int timeout)
+   unsigned int utimeout)
 {
struct amdgpu_device *adev = get_amdgpu_device(kgd);
struct cik_sdma_rlc_registers *m;
uint32_t sdma_base_addr;
uint32_t temp;
+   int timeout = utimeout;
 
m = get_sdma_mqd(mqd);
sdma_base_addr = get_sdma_base_addr(m);
@@ -485,7 +486,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void 
*mqd,
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
break;
-   if (timeout == 0)
+   if (timeout <= 0)
return -ETIME;
msleep(20);
timeout -= 20;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 342a037..a5c027d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -62,10 +62,10 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, 
uint64_t queue_address,
uint32_t pipe_id, uint32_t queue_id);
 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
-   unsigned int timeout, uint32_t pipe_id,
+   unsigned int utimeout, uint32_t pipe_id,
uint32_t queue_id);
 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
-   unsigned int timeout);
+   unsigned int utimeout);
 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
 static int kgd_address_watch_disable(struct kgd_dev *kgd);
 static int kgd_address_watch_execute(struct kgd_dev *kgd,
@@ -349,11 +349,12 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, 
void *mqd)
 }
 
 static int kgd_hqd_destroy(

[PATCH 2/7] radeonkfd/amdkfd: Implement get_local_mem_info()

[Edward O'Callaghan]

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 32 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c |  2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c |  6 -
 drivers/gpu/drm/amd/include/kgd_kfd_interface.h   | 13 +++--
 drivers/gpu/drm/radeon/radeon_kfd.c   | 22 +---
 7 files changed, 66 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index d080d08..63a2e84 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -226,14 +226,38 @@ void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
kfree(mem);
 }
 
-uint64_t get_vmem_size(struct kgd_dev *kgd)
+void get_local_mem_info(struct kgd_dev *kgd,
+   struct kfd_local_mem_info *mem_info)
 {
-   struct amdgpu_device *rdev =
-   (struct amdgpu_device *)kgd;
+   struct amdgpu_device *rdev = (struct amdgpu_device *)kgd;
+   uint64_t address_mask;
+   resource_size_t aper_limit;
 
BUG_ON(kgd == NULL);
 
-   return rdev->mc.real_vram_size;
+   memset(mem_info, 0, sizeof(*mem_info));
+
+   address_mask = ~((1UL << 40) - 1);
+   aper_limit = rdev->mc.aper_base + rdev->mc.aper_size;
+
+   if (!(rdev->mc.aper_base & address_mask ||
+   aper_limit & address_mask)) {
+   mem_info->local_mem_size_public = rdev->mc.visible_vram_size;
+   mem_info->local_mem_size_private = rdev->mc.real_vram_size -
+   rdev->mc.visible_vram_size;
+   } else {
+   mem_info->local_mem_size_public = 0;
+   mem_info->local_mem_size_private = rdev->mc.real_vram_size;
+   }
+   mem_info->vram_width = rdev->mc.vram_width;
+
+   if (amdgpu_powerplay || rdev->pm.funcs->get_mclk)
+   mem_info->mem_clk_max = amdgpu_dpm_get_mclk(rdev, false) / 100;
+
+   pr_debug("amdgpu: address base: 0x%llx limit 0x%llx public 0x%llx 
private 0x%llx\n",
+   rdev->mc.aper_base, aper_limit,
+   mem_info->local_mem_size_public,
+   mem_info->local_mem_size_private);
 }
 
 uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index de530f68d..31da026 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -57,7 +57,8 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
void **mem_obj, uint64_t *gpu_addr,
void **cpu_ptr);
 void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj);
-uint64_t get_vmem_size(struct kgd_dev *kgd);
+void get_local_mem_info(struct kgd_dev *kgd,
+   struct kfd_local_mem_info *mem_info);
 uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
 
 uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 362bedc..dc69cf7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -131,7 +131,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum 
kgd_engine_type type);
 static const struct kfd2kgd_calls kfd2kgd = {
.init_gtt_mem_allocation = alloc_gtt_mem,
.free_gtt_mem = free_gtt_mem,
-   .get_vmem_size = get_vmem_size,
+   .get_local_mem_info = get_local_mem_info,
.get_gpu_clock_counter = get_gpu_clock_counter,
.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
.program_sh_mem_settings = kgd_program_sh_mem_settings,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 04b744d..342a037 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -90,7 +90,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum 
kgd_engine_type type);
 static const struct kfd2kgd_calls kfd2kgd = {
.init_gtt_mem_allocation = alloc_gtt_mem,
.free_gtt_mem = free_gtt_mem,
-   .get_vmem_size = get_vmem_size,
+   .get_local_mem_info = get_local_mem_info,
.get_gpu_clock_counter = get_gpu_clock_counter,
.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
.program_sh_mem_settings = kgd_program_sh_mem_settings,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 1e50647..6ea7b

[PATCH 4/7] drm/amdkfd: Make kfd_lookup_process_by_pasid() well defined

[Edward O'Callaghan]

Ensure we return a NULL on the fail branch so that the call
site may BUG_ON() it.

Signed-off-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
 drivers/gpu/drm/amd/amdkfd/kfd_process.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 4f3849a..8d78052 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -481,13 +481,14 @@ bool kfd_has_process_device_data(struct kfd_process *p)
 /* This returns with process->mutex locked. */
 struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid)
 {
-   struct kfd_process *p;
+   struct kfd_process *p, *ret_p = NULL;
unsigned int temp;
 
int idx = srcu_read_lock(_processes_srcu);
 
hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
if (p->pasid == pasid) {
+   ret_p = p;
mutex_lock(>mutex);
break;
}
@@ -495,5 +496,5 @@ struct kfd_process *kfd_lookup_process_by_pasid(unsigned 
int pasid)
 
srcu_read_unlock(_processes_srcu, idx);
 
-   return p;
+   return ret_p;
 }
-- 
2.7.4

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