RE: [PATCH] drm/amd/display: use the proper fb offset for DM
[AMD Official Use Only - General] Reviewed-by: Huang Rui -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Wednesday, November 30, 2022 2:17 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH] drm/amd/display: use the proper fb offset for DM This fixes DMCU initialization in APU GPU passthrough. The DMCU needs the GPU physical address, not the CPU physical address. This ends up working out on bare metal because we always use the physical address, but doesn't work in passthrough because the addresses are different. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3792a181253b..850432e220a8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1096,7 +1096,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) /* Initialize hardware. */ memset(&hw_params, 0, sizeof(hw_params)); hw_params.fb_base = adev->gmc.fb_start; - hw_params.fb_offset = adev->gmc.aper_base; + hw_params.fb_offset = adev->vm_manager.vram_base_offset; /* backdoor load firmware and trigger dmub running */ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) @@ -1218,7 +1218,7 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_ pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; pa_config->system_aperture.fb_base = adev->gmc.fb_start; - pa_config->system_aperture.fb_offset = adev->gmc.aper_base; + pa_config->system_aperture.fb_offset = +adev->vm_manager.vram_base_offset; pa_config->system_aperture.fb_top = adev->gmc.fb_end; pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; -- 2.38.1 <>
RE: [PATCH] drm/amdgpu: clean up asd on the ta_firmware_header_v2_0
[AMD Official Use Only - General]
Acked-by: Huang Rui
-Original Message-
From: Liang, Prike
Sent: Friday, May 20, 2022 2:12 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Liu, Aaron ; Zhang, Yifan
; Liang, Prike
Subject: [PATCH] drm/amdgpu: clean up asd on the ta_firmware_header_v2_0
On the psp13 series use ta_firmware_header_v2_0 and the asd firmware was
buildin ta, so needn't request asd firmware separately.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index d6d79e97def9..f2e3b6ede77b 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -32,13 +32,10 @@
MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
-MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin");
MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
-MODULE_FIRMWARE("amdgpu/psp_13_0_5_asd.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
-MODULE_FIRMWARE("amdgpu/psp_13_0_8_asd.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
@@ -93,9 +90,6 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
case IP_VERSION(13, 0, 3):
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 8):
- err = psp_init_asd_microcode(psp, chip_name);
- if (err)
- return err;
err = psp_init_toc_microcode(psp, chip_name);
if (err)
return err;
--
2.25.1
RE: [PATCH] drm/amdgpu: align ip discovery naming with legacy ASICs
[AMD Official Use Only]
Acked-by: Huang Rui
-Original Message-
From: Zhang, Yifan
Sent: Tuesday, March 8, 2022 2:21 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: align ip discovery naming with legacy ASICs
There some code assuming ASIC names are non-space character.
e.g.
runKfdTest() {
if [ "$RUN_IN_DOCKER" == "true" ]; then
for hsaNode in $hsaNodes; do
nodeName=$(getNodeName $hsaNode)
if [ "$PLATFORM" != "" ] && [ "$PLATFORM" != "$nodeName" ]; then
echo "WARNING: Actual ASIC $nodeName treated as $PLATFORM"
nodeName="$PLATFORM"
fi
getFilter $nodeName
}
getFilter() {
local platform=$1;
}
if launch run_kfdtest.sh on a ip discovery ASIC, platform in getFilter will be
"ip"
instead of "ip discovery"
$ ./run_kfdtest.sh
Unsupported platform ip. Exiting
Replace whitespace with underscore to align the naming.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7abdf5e3dc05..0a66f724a4eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -123,7 +123,7 @@ const char *amdgpu_asic_name[] = {
"DIMGREY_CAVEFISH",
"BEIGE_GOBY",
"YELLOW_CARP",
- "IP DISCOVERY",
+ "IP_DISCOVERY",
"LAST",
};
--
2.25.1
RE: [PATCH 1/2] drm/amdgpu: change registers in error checking for smu 13.0.5
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Zhang, Yifan
Sent: Monday, March 7, 2022 3:54 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Zhang, Yifan
Subject: [PATCH 1/2] drm/amdgpu: change registers in error checking for smu
13.0.5
smu 13.0.5 use new registers for smu msg and param.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 590a6ed12d54..89b22b261066 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -160,11 +160,17 @@ static void __smu_cmn_reg_print_error(struct smu_context
*smu, {
struct amdgpu_device *adev = smu->adev;
const char *message = smu_get_message_name(smu, msg);
+ u32 msg_idx, prm;
switch (reg_c2pmsg_90) {
case SMU_RESP_NONE: {
- u32 msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66);
- u32 prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
+ msg_idx = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2);
+ prm = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
+ } else {
+ msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66);
+ prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ }
dev_err_ratelimited(adev->dev,
"SMU: I'm not done with your previous
command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X",
msg_idx, prm);
--
2.25.1
RE: [PATCH] drm/amdgpu: add gfxoff support for smu 13.0.5
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Zhang, Yifan
Sent: Friday, February 25, 2022 4:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: add gfxoff support for smu 13.0.5
this patch adds gfxoff support for smu 13.0.5
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 261a3749c089..4e557f4f7c4d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -751,6 +751,7 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool
enable)
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
+ case IP_VERSION(13, 0, 5):
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return 0;
if (enable)
--
2.25.1
RE: [PATCH] drm/amdgpu: add mode2 reset support for smu 13.0.5
[AMD Official Use Only] Reviewed-by: Huang Rui -Original Message- From: Zhang, Yifan Sent: Tuesday, February 22, 2022 4:26 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Huang, Ray ; Zhang, Yifan Subject: [PATCH] drm/amdgpu: add mode2 reset support for smu 13.0.5 This patch adds mode2 reset support for smu 13.0.5. Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/nv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 74e0550d00bd..80caf73bc2ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -454,6 +454,7 @@ nv_asic_reset_method(struct amdgpu_device *adev) case IP_VERSION(11, 5, 0): case IP_VERSION(13, 0, 1): case IP_VERSION(13, 0, 3): + case IP_VERSION(13, 0, 5): return AMD_RESET_METHOD_MODE2; case IP_VERSION(11, 0, 7): case IP_VERSION(11, 0, 11): -- 2.25.1
RE: [PATCH] drm/amd/pm: correct the sequence of sending gpu reset msg
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Liu, Aaron
Sent: Monday, February 14, 2022 12:38 PM
To: Zhang, Yifan ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
Subject: RE: [PATCH] drm/amd/pm: correct the sequence of sending gpu reset msg
[AMD Official Use Only]
Yifan,
Please remove Change-Id.
With this fixed, Acked-by: Aaron Liu
--
Best Regards
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of
> Yifan Zhang
> Sent: Monday, February 14, 2022 12:12 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
> ; Liu, Aaron
> Subject: [PATCH] drm/amd/pm: correct the sequence of sending gpu reset
> msg
>
> the 2nd parameter should be smu msg type rather than asic msg index.
>
> Signed-off-by: Yifan Zhang
> Change-Id: I0a65fac53b06c053ce193580d68cf586e77d2c2d
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 9 ++---
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> index e90387a84cbb..e2d099409123 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> @@ -262,14 +262,9 @@ static int yellow_carp_post_smu_init(struct
> smu_context *smu)
>
> static int yellow_carp_mode_reset(struct smu_context *smu, int type) {
> - int ret = 0, index = 0;
> -
> - index = smu_cmn_to_asic_specific_index(smu,
> CMN2ASIC_MAPPING_MSG,
> - SMU_MSG_GfxDeviceDriverReset);
> - if (index < 0)
> - return index == -EACCES ? 0 : index;
> + int ret = 0;
>
> - ret = smu_cmn_send_smc_msg_with_param(smu, (uint16_t)index,
> type, NULL);
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> +SMU_MSG_GfxDeviceDriverReset, type, NULL);
> if (ret)
> dev_err(smu->adev->dev, "Failed to mode reset!\n");
>
> --
> 2.25.1
RE: [PATCH] drm/amdgpu: add support for GC 10.1.4
[Public]
Reviewed-by: Huang Rui
From: Deucher, Alexander
Sent: Thursday, February 10, 2022 10:57 PM
To: Yu, Lang ; amd-gfx@lists.freedesktop.org
Cc: Huang, Ray
Subject: Re: [PATCH] drm/amdgpu: add support for GC 10.1.4
[Public]
Reviewed-by: Alex Deucher
mailto:alexander.deuc...@amd.com>>
From: Yu, Lang mailto:lang...@amd.com>>
Sent: Thursday, February 10, 2022 1:20 AM
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Deucher, Alexander
mailto:alexander.deuc...@amd.com>>; Huang, Ray
mailto:ray.hu...@amd.com>>; Yu, Lang
mailto:lang...@amd.com>>
Subject: [PATCH] drm/amdgpu: add support for GC 10.1.4
Add basic support for GC 10.1.4,
it uses same IP blocks with GC 10.1.3
Signed-off-by: Lang Yu mailto:lang...@amd.com>>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 9 +
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 4 +++-
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c| 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 ++
8 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index eb4b7059633d..cd7e8522c130 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -674,6 +674,7 @@ static int amdgpu_discovery_set_common_ip_blocks(struct
amdgpu_device *adev)
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 1, 4):
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 2):
@@ -709,6 +710,7 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct
amdgpu_device *adev)
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 1, 4):
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 2):
@@ -910,6 +912,7 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct
amdgpu_device *adev)
case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 1, 4):
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
case IP_VERSION(10, 3, 1):
@@ -1044,6 +1047,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct
amdgpu_device *adev)
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 1, 4):
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 2):
@@ -1243,6 +1247,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device
*adev)
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 1, 4):
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
case IP_VERSION(10, 3, 4):
@@ -1264,6 +1269,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device
*adev)
case IP_VERSION(9, 2, 2):
case IP_VERSION(9, 3, 0):
case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 1, 4):
case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 3):
adev->flags |= AMD_IS_APU;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index f2806959736a..9bc9155cbf06 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -137,7 +137,8 @@ static int psp_early_init(void *handle)
psp->autoload_supported = true;
break;
case IP_VERSION(11, 0, 8):
- if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
+ if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2 ||
+ adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4)) {
psp_v11_0_8_set_psp_funcs(psp);
psp->autoload_supported = false;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 3d8c5fea572e..8fb4528c741f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3641,6 +3641,7 @@ static void gfx_v10_0_init_golden_registers(struct
amdgpu_device *adev)
(const
u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
break;
case IP_VERSION(10, 1, 3):
+ case I
RE: [PATCH v2] drm/amdgpu: introduce new amdgpu_fence object to indicate the job embedded fence
[AMD Official Use Only]
Yes, exactly.
AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT is the private flag only for amdgpu. Maybe,
it's cleaner to define another amdgpu_fence_ops which is dedicated for
job-embedded fence.
Thanks,
Ray
From: Grodzovsky, Andrey
Sent: Wednesday, December 15, 2021 1:09 AM
To: Huang, Ray ; dri-de...@lists.freedesktop.org; Koenig,
Christian ; Daniel Vetter ;
Sumit Semwal
Cc: Deucher, Alexander ;
amd-gfx@lists.freedesktop.org; Liu, Monk ;
linux-me...@vger.kernel.org
Subject: Re: [PATCH v2] drm/amdgpu: introduce new amdgpu_fence object to
indicate the job embedded fence
On 2021-12-14 12:03 p.m., Andrey Grodzovsky wrote:
-
- if (job != NULL) {
- /* mark this fence has a parent job */
- set_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &fence->flags);
+ if (job)
+ dma_fence_init(fence, &amdgpu_job_fence_ops,
+ &ring->fence_drv.lock,
+ adev->fence_context + ring->idx, seq);
+ else
+ dma_fence_init(fence, &amdgpu_fence_ops,
+ &ring->fence_drv.lock,
+ adev->fence_context + ring->idx, seq);
}
It's probably me missing something but why can't we just move setting of
AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT
to before dma_fence_init here or even into amdgpu_job_alloc instead of all the
refactoring ?
Andrey
My bad, I see now that dma_fence_init just overrides flags to 0 and immediately
call the trace .
But why then can't we add dma_fence_init_with_flags wrapper to dma-fence ?
Andrey
RE: [PATCH v2] drm/amdgpu: introduce new amdgpu_fence object to indicate the job embedded fence
[AMD Official Use Only]
> -Original Message-
> From: Koenig, Christian
> Sent: Tuesday, December 14, 2021 8:26 PM
> To: Huang, Ray ; dri-de...@lists.freedesktop.org;
> Daniel Vetter ; Sumit Semwal
>
> Cc: amd-gfx@lists.freedesktop.org; linux-me...@vger.kernel.org; Deucher,
> Alexander ; Liu, Monk
>
> Subject: Re: [PATCH v2] drm/amdgpu: introduce new amdgpu_fence object
> to indicate the job embedded fence
>
>
>
> Am 14.12.21 um 12:15 schrieb Huang Rui:
> > The job embedded fence donesn't initialize the flags at
> > dma_fence_init(). Then we will go a wrong way in
> > amdgpu_fence_get_timeline_name callback and trigger a null pointer
> > panic once we enabled the trace event here. So introduce new
> > amdgpu_fence object to indicate the job embedded fence.
> >
> > [ 156.131790] BUG: kernel NULL pointer dereference, address:
> > 02a0 [ 156.131804] #PF: supervisor read access in kernel
> > mode [ 156.131811] #PF: error_code(0x) - not-present page [
> > 156.131817] PGD 0 P4D 0 [ 156.131824] Oops: [#1] PREEMPT SMP PTI
> > [ 156.131832] CPU: 6 PID: 1404 Comm: sdma0 Tainted: G OE
> > 5.16.0-
> rc1-custom #1
> > [ 156.131842] Hardware name: Gigabyte Technology Co., Ltd.
> > Z170XP-SLI/Z170XP-SLI-CF, BIOS F20 11/04/2016 [ 156.131848] RIP:
> > 0010:strlen+0x0/0x20 [ 156.131859] Code: 89 c0 c3 0f 1f 80 00 00 00
> > 00 48 01 fe eb 0f 0f b6 07 38 d0 74 10 48 83 c7 01 84 c0 74 05 48 39
> > f7 75 ec 31 c0 c3 48 89 f8 c3 <80> 3f 00 74 10 48 89 f8 48 83 c0 01 80
> > 38 00 75 f7 48 29 f8 c3 31 [ 156.131872] RSP: 0018:9bd0018dbcf8
> > EFLAGS: 00010206 [ 156.131880] RAX: 02a0 RBX:
> > 8d0305ef01b0 RCX: 000b [ 156.131888] RDX:
> > 8d03772ab924 RSI: 8d0305ef01b0 RDI: 02a0 [
> > 156.131895] RBP: 9bd0018dbd60 R08: 8d03002094d0 R09:
> > [ 156.131901] R10: 005e R11:
> > 0065 R12: 8d03002094d0 [ 156.131907] R13:
> > 001f R14: 00070018 R15: 0007 [
> > 156.131914] FS: () GS:8d062ed8()
> > knlGS: [ 156.131923] CS: 0010 DS: ES: CR0:
> 80050033 [ 156.131929] CR2: 02a0 CR3:
> 1120a005 CR4: 003706e0 [ 156.131937] DR0:
> DR1: DR2:
> [ 156.131942] DR3: DR6: fffe0ff0 DR7:
> 0400 [ 156.131949] Call Trace:
> > [ 156.131953]
> > [ 156.131957] ? trace_event_raw_event_dma_fence+0xcc/0x200
> > [ 156.131973] ? ring_buffer_unlock_commit+0x23/0x130
> > [ 156.131982] dma_fence_init+0x92/0xb0 [ 156.131993]
> > amdgpu_fence_emit+0x10d/0x2b0 [amdgpu] [ 156.132302]
> > amdgpu_ib_schedule+0x2f9/0x580 [amdgpu] [ 156.132586]
> > amdgpu_job_run+0xed/0x220 [amdgpu]
> >
> > Signed-off-by: Huang Rui
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 117
> ++---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 -
> > 4 files changed, 80 insertions(+), 44 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 9f017663ac50..fcaf6e9703f9 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -444,6 +444,7 @@ struct amdgpu_sa_bo {
> >
> > int amdgpu_fence_slab_init(void);
> > void amdgpu_fence_slab_fini(void);
> > +bool is_job_embedded_fence(struct dma_fence *f);
>
> We need a better name for this, especially with amdgpu in it. Something like
> is_amdgpu_job_fence().
>
> But maybe we can avoid that function alltogether, see below.
>
> >
> > /*
> >* IRQS.
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 5625f7736e37..444a19eb2248 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -4483,9 +4483,8 @@ int amdgpu_device_pre_asic_reset(struct
> > amdgpu_device *adev,
> >
> > ptr = &ring->fence_drv.fences[j];
> > old = rcu_dereference_protected(*ptr, 1);
> > - if (old &&
> test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &old->flags)) {
> > + if (old && is_job_embedded_f
RE: [PATCH 1/3] dma-buf: make the flags can be configured during dma fence init
[AMD Official Use Only]
> -Original Message-
> From: Koenig, Christian
> Sent: Tuesday, December 14, 2021 5:24 PM
> To: Huang, Ray ; dri-de...@lists.freedesktop.org;
> Daniel Vetter ; Sumit Semwal
>
> Cc: amd-gfx@lists.freedesktop.org; linux-me...@vger.kernel.org; Deucher,
> Alexander ; Liu, Monk
>
> Subject: Re: [PATCH 1/3] dma-buf: make the flags can be configured during
> dma fence init
>
> Am 14.12.21 um 10:19 schrieb Huang, Ray:
> > [AMD Official Use Only]
> >
> >> -Original Message-
> >> From: Koenig, Christian
> >> Sent: Tuesday, December 14, 2021 4:00 PM
> >> To: Huang, Ray ; dri-de...@lists.freedesktop.org;
> >> Daniel Vetter ; Sumit Semwal
> >>
> >> Cc: amd-gfx@lists.freedesktop.org; linux-me...@vger.kernel.org;
> >> Deucher, Alexander ; Liu, Monk
> >>
> >> Subject: Re: [PATCH 1/3] dma-buf: make the flags can be configured
> >> during dma fence init
> >>
> >> Am 13.12.21 um 07:34 schrieb Huang Rui:
> >>> In some user scenarios, the get_timeline_name callback uses the
> >>> flags to decide which way to return the timeline string name. Once
> >>> the trace_dma_fence_init event is enabled, it will call
> >>> get_timeline_name callback to dump the fence structure. However, at
> >>> this moment, the flags are always 0, and it might trigger some
> >>> issues in get_timeline_name callback implementation of different gpu
> >>> driver. So make a member to initialize the flags in dma_fence_init().
> >> Well that doesn't make much sense to me.
> >>
> >> None of the dma_fence callbacks is called from the dma_fence_init
> >> function (or at least shouldn't). So drivers always have the
> >> opportunity to to adjust the flags.
> >>
> >> So please explain the rational again?
> > Once we enable trace_dma_fence_init event, we will call get_driver_name
> and get_timeline_name callback function to dump the names in
> dma_fence_init().
> > At that time, the flags are always 0. However, in
> amdgpu_fence_get_timeline_name(), it will check the flags
> (AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT) to select which way to get
> the ring.
> > If the fence should be actually embedded in the job (will be set after
> > that),
> it still will trigger a kernel panic (please see patch2) because it go with a
> wrong way. Because we cannot set the flags at the start of dma_fence_init.
> That is the problem.
>
> Well then I think we should fix the whole approach instead because what
> you try to do here is utterly nonsense. You can't modify the ops structure on
> the fly because that is used by all the fences.
>
> Instead please just duplicate the amdgpu_fence_ops() and separate them
> into two structure, one for each case.
>
> This way we should also be able to completely drop the
> AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT flag.
>
OK, you mean this flag is not one of them in standard dma_fence_flag_bits and
it AMD specific, so we would better to drop this to align the dam_fence
structure design?
Thanks,
Ray
> Regards,
> Christian.
>
> >
> > Thanks,
> > Ray
> >
> >> Christian.
> >>
> >>> Signed-off-by: Huang Rui
> >>> ---
> >>>drivers/dma-buf/dma-fence.c | 2 +-
> >>>include/linux/dma-fence.h | 7 +++
> >>>2 files changed, 8 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/dma-buf/dma-fence.c
> >>> b/drivers/dma-buf/dma-fence.c index 066400ed8841..3e0622bf385f
> >>> 100644
> >>> --- a/drivers/dma-buf/dma-fence.c
> >>> +++ b/drivers/dma-buf/dma-fence.c
> >>> @@ -952,7 +952,7 @@ dma_fence_init(struct dma_fence *fence, const
> >> struct dma_fence_ops *ops,
> >>> fence->lock = lock;
> >>> fence->context = context;
> >>> fence->seqno = seqno;
> >>> - fence->flags = 0UL;
> >>> + fence->flags = ops->init_flags;
> >>> fence->error = 0;
> >>>
> >>> trace_dma_fence_init(fence);
> >>> diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h
> >>> index 1ea691753bd3..f9270c5bc07a 100644
> >>> --- a/include/linux/dma-fence.h
> >>> +++ b/include/linux/dma-fence.h
> >>> @@ -131,6 +131,13 @@ struct dma_fence_ops {
> >>>*/
> >>> bool use_64bit_seqno;
> >>>
> >>> + /**
> >>> + * @init_flags:
> >>> + *
> >>> + * The initial value of fence flags (A mask of DMA_FENCE_FLAG_*
> >> defined).
> >>> + */
> >>> + unsigned long init_flags;
> >>> +
> >>> /**
> >>>* @get_driver_name:
> >>>*
RE: [PATCH 2/3] drm/amdgpu: fix the fence timeline null pointer
[AMD Official Use Only]
> -Original Message-
> From: Koenig, Christian
> Sent: Tuesday, December 14, 2021 4:01 PM
> To: Huang, Ray ; dri-de...@lists.freedesktop.org;
> Daniel Vetter ; Sumit Semwal
>
> Cc: amd-gfx@lists.freedesktop.org; linux-me...@vger.kernel.org; Deucher,
> Alexander ; Liu, Monk
>
> Subject: Re: [PATCH 2/3] drm/amdgpu: fix the fence timeline null pointer
>
> Am 13.12.21 um 07:34 schrieb Huang Rui:
> > Initialize the flags for embedded fence in the job at dma_fence_init().
> > Otherwise, we will go a wrong way in amdgpu_fence_get_timeline_name
> > callback and trigger a null pointer panic once we enabled the trace
> > event here.
> >
> > [ 156.131790] BUG: kernel NULL pointer dereference, address:
> > 02a0 [ 156.131804] #PF: supervisor read access in kernel
> > mode [ 156.131811] #PF: error_code(0x) - not-present page [
> > 156.131817] PGD 0 P4D 0 [ 156.131824] Oops: [#1] PREEMPT SMP PTI
> > [ 156.131832] CPU: 6 PID: 1404 Comm: sdma0 Tainted: G OE
> > 5.16.0-
> rc1-custom #1
> > [ 156.131842] Hardware name: Gigabyte Technology Co., Ltd.
> > Z170XP-SLI/Z170XP-SLI-CF, BIOS F20 11/04/2016 [ 156.131848] RIP:
> > 0010:strlen+0x0/0x20 [ 156.131859] Code: 89 c0 c3 0f 1f 80 00 00 00
> > 00 48 01 fe eb 0f 0f b6 07 38 d0 74 10 48 83 c7 01 84 c0 74 05 48 39
> > f7 75 ec 31 c0 c3 48 89 f8 c3 <80> 3f 00 74 10 48 89 f8 48 83 c0 01 80
> > 38 00 75 f7 48 29 f8 c3 31 [ 156.131872] RSP: 0018:9bd0018dbcf8
> > EFLAGS: 00010206 [ 156.131880] RAX: 02a0 RBX:
> > 8d0305ef01b0 RCX: 000b [ 156.131888] RDX:
> > 8d03772ab924 RSI: 8d0305ef01b0 RDI: 02a0 [
> > 156.131895] RBP: 9bd0018dbd60 R08: 8d03002094d0 R09:
> > [ 156.131901] R10: 005e R11:
> > 0065 R12: 8d03002094d0 [ 156.131907] R13:
> > 001f R14: 00070018 R15: 0007 [
> > 156.131914] FS: () GS:8d062ed8()
> > knlGS: [ 156.131923] CS: 0010 DS: ES: CR0:
> 80050033 [ 156.131929] CR2: 02a0 CR3:
> 1120a005 CR4: 003706e0 [ 156.131937] DR0:
> DR1: DR2:
> [ 156.131942] DR3: DR6: fffe0ff0 DR7:
> 0400 [ 156.131949] Call Trace:
> > [ 156.131953]
> > [ 156.131957] ? trace_event_raw_event_dma_fence+0xcc/0x200
> > [ 156.131973] ? ring_buffer_unlock_commit+0x23/0x130
> > [ 156.131982] dma_fence_init+0x92/0xb0 [ 156.131993]
> > amdgpu_fence_emit+0x10d/0x2b0 [amdgpu] [ 156.132302]
> > amdgpu_ib_schedule+0x2f9/0x580 [amdgpu] [ 156.132586]
> > amdgpu_job_run+0xed/0x220 [amdgpu]
> >
> > Signed-off-by: Huang Rui
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 17 +
> > 1 file changed, 9 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> > index 3b7e86ea7167..e2aa71904278 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> > @@ -76,7 +76,7 @@ void amdgpu_fence_slab_fini(void)
> > /*
> >* Cast helper
> >*/
> > -static const struct dma_fence_ops amdgpu_fence_ops;
> > +static struct dma_fence_ops amdgpu_fence_ops;
> > static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence
> *f)
> > {
> > struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence,
> > base); @@ -158,21 +158,22 @@ int amdgpu_fence_emit(struct
> amdgpu_ring *ring, struct dma_fence **f, struct amd
> > }
> >
> > seq = ++ring->fence_drv.sync_seq;
> > - if (job != NULL && job->job_run_counter) {
> > + if (job && job->job_run_counter) {
> > /* reinit seq for resubmitted jobs */
> > fence->seqno = seq;
> > + set_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT,
> &fence->flags);
> > } else {
> > + amdgpu_fence_ops.init_flags = 0;
> > + if (job)
> > + set_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT,
> > + &amdgpu_fence_ops.init_flags);
>
> That is utterly nonsense. The amdgpu_fence_ops are global and can't be
> modified like that.
>
Please check the reply in patch1, we need initialize the fence and assign the
flags together, otherwise it will trigger the panic once the trace event is
enabled.
Thanks,
Ra
RE: [PATCH 1/3] dma-buf: make the flags can be configured during dma fence init
[AMD Official Use Only]
> -Original Message-
> From: Koenig, Christian
> Sent: Tuesday, December 14, 2021 4:00 PM
> To: Huang, Ray ; dri-de...@lists.freedesktop.org;
> Daniel Vetter ; Sumit Semwal
>
> Cc: amd-gfx@lists.freedesktop.org; linux-me...@vger.kernel.org; Deucher,
> Alexander ; Liu, Monk
>
> Subject: Re: [PATCH 1/3] dma-buf: make the flags can be configured during
> dma fence init
>
> Am 13.12.21 um 07:34 schrieb Huang Rui:
> > In some user scenarios, the get_timeline_name callback uses the flags
> > to decide which way to return the timeline string name. Once the
> > trace_dma_fence_init event is enabled, it will call get_timeline_name
> > callback to dump the fence structure. However, at this moment, the
> > flags are always 0, and it might trigger some issues in
> > get_timeline_name callback implementation of different gpu driver. So
> > make a member to initialize the flags in dma_fence_init().
>
> Well that doesn't make much sense to me.
>
> None of the dma_fence callbacks is called from the dma_fence_init function
> (or at least shouldn't). So drivers always have the opportunity to to adjust
> the flags.
>
> So please explain the rational again?
Once we enable trace_dma_fence_init event, we will call get_driver_name and
get_timeline_name callback function to dump the names in dma_fence_init().
At that time, the flags are always 0. However, in
amdgpu_fence_get_timeline_name(), it will check the flags
(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT) to select which way to get the ring.
If the fence should be actually embedded in the job (will be set after that),
it still will trigger a kernel panic (please see patch2) because it go with a
wrong way. Because we cannot set the flags at the start of dma_fence_init. That
is the problem.
Thanks,
Ray
>
> Christian.
>
> >
> > Signed-off-by: Huang Rui
> > ---
> > drivers/dma-buf/dma-fence.c | 2 +-
> > include/linux/dma-fence.h | 7 +++
> > 2 files changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
> > index 066400ed8841..3e0622bf385f 100644
> > --- a/drivers/dma-buf/dma-fence.c
> > +++ b/drivers/dma-buf/dma-fence.c
> > @@ -952,7 +952,7 @@ dma_fence_init(struct dma_fence *fence, const
> struct dma_fence_ops *ops,
> > fence->lock = lock;
> > fence->context = context;
> > fence->seqno = seqno;
> > - fence->flags = 0UL;
> > + fence->flags = ops->init_flags;
> > fence->error = 0;
> >
> > trace_dma_fence_init(fence);
> > diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h
> > index 1ea691753bd3..f9270c5bc07a 100644
> > --- a/include/linux/dma-fence.h
> > +++ b/include/linux/dma-fence.h
> > @@ -131,6 +131,13 @@ struct dma_fence_ops {
> > */
> > bool use_64bit_seqno;
> >
> > + /**
> > +* @init_flags:
> > +*
> > +* The initial value of fence flags (A mask of DMA_FENCE_FLAG_*
> defined).
> > +*/
> > + unsigned long init_flags;
> > +
> > /**
> > * @get_driver_name:
> > *
RE: [PATCH] drm/amdgpu: support B0&B1 external revision id for yellow carp
[AMD Official Use Only] > -Original Message- > From: Liu, Aaron > Sent: Tuesday, October 19, 2021 11:23 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Huang, Ray > ; Liu, Aaron > Subject: [PATCH] drm/amdgpu: support B0&B1 external revision id for yellow > carp > > B0 internal rev_id is 0x01, B1 internal rev_id is 0x02. > The external rev_id for B0 and B1 is 0x20. > The original expression is not suitable for B1. > > Signed-off-by: Aaron Liu Reviewed-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/nv.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c > b/drivers/gpu/drm/amd/amdgpu/nv.c index 898e688be63c..5166a1573e7e > 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nv.c > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c > @@ -1248,7 +1248,7 @@ static int nv_common_early_init(void *handle) > AMD_PG_SUPPORT_VCN_DPG | > AMD_PG_SUPPORT_JPEG; > if (adev->pdev->device == 0x1681) > - adev->external_rev_id = adev->rev_id + 0x19; > + adev->external_rev_id = 0x20; > else > adev->external_rev_id = adev->rev_id + 0x01; > break; > -- > 2.25.1
RE: [PATCH] drm/amdgpu: enable display for cyan skillfish
[AMD Official Use Only] + Charlene. Reviewed-by: Huang Rui -Original Message- From: Yu, Lang Sent: Tuesday, October 12, 2021 2:16 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Huang, Ray ; Yu, Lang Subject: [PATCH] drm/amdgpu: enable display for cyan skillfish Display support for cyan skillfish is ready now. Enable it! Signed-off-by: Lang Yu --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 2bebd2ce6474..4228c7964175 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -736,6 +736,7 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(1, 0, 1): case IP_VERSION(2, 0, 2): case IP_VERSION(2, 0, 0): + case IP_VERSION(2, 0, 3): case IP_VERSION(2, 1, 0): case IP_VERSION(3, 0, 0): case IP_VERSION(3, 0, 2): @@ -745,8 +746,6 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(3, 1, 3): amdgpu_device_ip_block_add(adev, &dm_ip_block); break; - case IP_VERSION(2, 0, 3): - break; default: return -EINVAL; } -- 2.25.1
RE: [PATCH] drm/amdgpu: query default sclk from smu for cyan_skillfish
[AMD Official Use Only]
Acked-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Lang Yu
Sent: Monday, October 11, 2021 4:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Yu, Lang
Subject: [PATCH] drm/amdgpu: query default sclk from smu for cyan_skillfish
Query default sclk instead of hard code.
Signed-off-by: Lang Yu
---
.../gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index 3d4c65bc29dc..d98fd06a2574 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -47,7 +47,6 @@
/* unit: MHz */
#define CYAN_SKILLFISH_SCLK_MIN1000
#define CYAN_SKILLFISH_SCLK_MAX2000
-#define CYAN_SKILLFISH_SCLK_DEFAULT1800
/* unit: mV */
#define CYAN_SKILLFISH_VDDC_MIN700
@@ -59,6 +58,8 @@ static struct gfx_user_settings {
uint32_t vddc;
} cyan_skillfish_user_settings;
+static uint32_t cyan_skillfish_sclk_default;
+
#define FEATURE_MASK(feature) (1ULL << feature) #define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
@@ -365,13 +366,18 @@ static bool cyan_skillfish_is_dpm_running(struct
smu_context *smu)
return false;
ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
-
if (ret)
return false;
feature_enabled = (uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32);
+ /*
+* cyan_skillfish specific, query default sclk inseted of hard code.
+*/
+ cyan_skillfish_get_smu_metrics_data(smu, METRICS_CURR_GFXCLK,
+ &cyan_skillfish_sclk_default);
+
return !!(feature_enabled & SMC_DPM_FEATURE); }
@@ -468,7 +474,7 @@ static int cyan_skillfish_od_edit_dpm_table(struct
smu_context *smu,
return -EINVAL;
}
- cyan_skillfish_user_settings.sclk = CYAN_SKILLFISH_SCLK_DEFAULT;
+ cyan_skillfish_user_settings.sclk = cyan_skillfish_sclk_default;
cyan_skillfish_user_settings.vddc = CYAN_SKILLFISH_VDDC_MAGIC;
break;
--
2.25.1
RE: [PATCH] drm/amdgpu: show both cmd id and name when psp cmd failed
Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Lang Yu
Sent: Friday, August 27, 2021 1:41 PM
To: amd-gfx@lists.freedesktop.org; Clements, John
Cc: Huang, Ray ; Yu, Lang
Subject: [PATCH] drm/amdgpu: show both cmd id and name when psp cmd failed
To cover the corner case that people want to know the ID
of an UNKNOWN CMD.
Suggested-by: John Clements
Signed-off-by: Lang Yu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 23efdc672502..9b41cb8c3de5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -469,10 +469,10 @@ psp_cmd_submit_buf(struct psp_context *psp,
*/
if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) &&
!ras_intr) {
if (ucode)
- DRM_WARN("failed to load ucode (%s) ",
- amdgpu_ucode_name(ucode->ucode_id));
- DRM_WARN("psp gfx command (%s) failed and response status is
(0x%X)\n",
-psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id),
+ DRM_WARN("failed to load ucode %s(0x%X) ",
+ amdgpu_ucode_name(ucode->ucode_id),
ucode->ucode_id);
+ DRM_WARN("psp gfx command %s(0x%X) failed and response status
is (0x%X)\n",
+psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id),
psp->cmd_buf_mem->cmd_id,
psp->cmd_buf_mem->resp.status);
if (!timeout) {
ret = -EINVAL;
--
2.25.1
RE: [PATCH 2/2] drm/amd/display: setup system context for APUs
[AMD Official Use Only]
Nice catch!
Series are Reviewed-by: Huang Rui
Thanks,
Ray
-Original Message-
From: Liu, Aaron
Sent: Friday, August 27, 2021 9:29 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Kazlauskas, Nicholas ; Liu,
Aaron
Subject: [PATCH 2/2] drm/amd/display: setup system context for APUs
Scatter/gather is APU feature starting from carrizo.
adev->apu_flags is not used for all APUs.
adev->flags & AMD_IS_APU can be used for all APUs.
Signed-off-by: Aaron Liu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e1e57e7465a7..7f311bba9735 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1327,7 +1327,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
dc_hardware_init(adev->dm.dc);
#if defined(CONFIG_DRM_AMD_DC_DCN)
- if (adev->apu_flags) {
+ if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
struct dc_phy_addr_space_config pa_config;
mmhub_read_system_context(adev, &pa_config);
--
2.25.1
RE: [PATCH] drm/amd/pm: update smu v13.0.1 firmware header
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Hou, Xiaomeng (Matthew)
Sent: Tuesday, August 3, 2021 11:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Aaron ; Deucher, Alexander
; Huang, Ray ; Hou, Xiaomeng
(Matthew)
Subject: [PATCH] drm/amd/pm: update smu v13.0.1 firmware header
Update smu v13.0.1 firmware header for yellow carp.
Signed-off-by: Xiaomeng Hou
---
drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h
b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h
index 5627de734246..c5e26d619bf0 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h
@@ -111,7 +111,9 @@ typedef struct {
uint32_t InWhisperMode: 1;
uint32_t spare0 : 1;
uint32_t ZstateStatus : 4;
- uint32_t spare1 :12;
+ uint32_t spare1 : 4;
+ uint32_t DstateFun: 4;
+ uint32_t DstateDev: 4;
// MP1_EXT_SCRATCH2
uint32_t P2JobHandler :24;
uint32_t RsmuPmiP2FinishedCnt : 8;
--
2.17.1
RE: [PATCH] drm/amdgpu: Make noretry the default on yellow carp
[AMD Official Use Only] Reviewed-by: Huang Rui -Original Message- From: Liu, Aaron Sent: Wednesday, June 30, 2021 1:57 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Huang, Ray ; Gong, Curry ; Kuehling, Felix ; Liu, Aaron ; Huang, Ray Subject: [PATCH] drm/amdgpu: Make noretry the default on yellow carp From: chen gong Performing kfd page fault tests on the yellow carp platform will fail. >From the scan data after the failure, it can be found that a nack=0x1(retry >fault) is returned. but we did not enable the interrupts for retry faults in >the code. So we need to set noretry = 1 like the above ASICs. Signed-off-by: chen gong Reviewed-by: Aaron Liu Acked-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 1525d957e114..d4e9704dec62 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -591,6 +591,7 @@ void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) case CHIP_ARCTURUS: case CHIP_ALDEBARAN: case CHIP_BEIGE_GOBY: + case CHIP_YELLOW_CARP: /* * noretry = 0 will cause kfd page fault tests fail * for some ASICs, so set default to 1 for these ASICs. -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: enable sdma0 tmz for Raven/Renoir(V2)
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Liu, Aaron
Sent: Monday, June 28, 2021 10:55 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Tuikov, Luben ; Koenig, Christian
; Liu, Aaron
Subject: [PATCH] drm/amdgpu: enable sdma0 tmz for Raven/Renoir(V2)
Without driver loaded, SDMA0_UTCL1_PAGE.TMZ_ENABLE is set to 1 by default for
all asic. On Raven/Renoir, the sdma goldsetting changes
SDMA0_UTCL1_PAGE.TMZ_ENABLE to 0.
This patch restores SDMA0_UTCL1_PAGE.TMZ_ENABLE to 1.
Signed-off-by: Aaron Liu
Acked-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index ae5464e2535a..f6881d99609b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -144,7 +144,7 @@ static const struct soc15_reg_golden
golden_settings_sdma_4_1[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111,
0x0100),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
- SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x03ff,
0x03c0),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x03ff,
+0x03e0),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc00,
0x) };
@@ -288,7 +288,7 @@ static const struct soc15_reg_golden
golden_settings_sdma_4_3[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07,
0x4051),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
- SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x03ff,
0x03c0),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x03ff,
+0x03e0),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc00,
0x03fbe1fe) };
--
2.25.1
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RE: [PATCH] drm/amd/pm: fix warning reported by kernel test robot
Reviewed-by: Huang Rui -Original Message- From: Hou, Xiaomeng (Matthew) Sent: Monday, June 7, 2021 8:46 PM To: amd-gfx@lists.freedesktop.org Cc: Huang, Ray ; Wang, Kevin(Yang) ; Hou, Xiaomeng (Matthew) Subject: [PATCH] drm/amd/pm: fix warning reported by kernel test robot Kernel test robot throws warning -> >> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:483:2: warning: variable 'member_type' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:487:47: note: uninitialized use occurs here return yellow_carp_get_smu_metrics_data(smu, member_type, value); ^~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:465:2: note: variable 'member_type' is declared here MetricsMember_t member_type; ^ 1 warning generated. Fix this warning by return errno when the clk type is unsupported. Signed-off-by: Xiaomeng Hou Reported-by: kernel test robot --- drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c index 031c49fb4582..0cd7902d5172 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c @@ -728,7 +728,7 @@ static int yellow_carp_get_current_clk_freq(struct smu_context *smu, return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, value); default: - break; + return -EINVAL; } return yellow_carp_get_smu_metrics_data(smu, member_type, value); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: modify system reference clock source for navi+ (V2)
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Liu, Aaron
Sent: Tuesday, May 18, 2021 10:16 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Wang, Kevin(Yang) ; Liu, Aaron
Subject: [PATCH] drm/amdgpu: modify system reference clock source for navi+ (V2)
Starting from Navi+, the rlc reference clock is used for system clock from
vbios gfx_info table. It is incorrect to use core_refclk_10khz of vbios
smu_info table as system clock.
Signed-off-by: Aaron Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 8c417014ca89..3b5d13189073 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -546,6 +546,21 @@ int amdgpu_atomfirmware_get_clock_info(struct
amdgpu_device *adev)
ret = 0;
}
+ /* if asic is Navi+, the rlc reference clock is used for system clock
+* from vbios gfx_info table */
+ if (adev->asic_type >= CHIP_NAVI10) {
+ index =
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+ gfx_info);
+ if (amdgpu_atom_parse_data_header(mode_info->atom_context,
index, NULL,
+ &frev, &crev, &data_offset)) {
+ struct atom_gfx_info_v2_2 *gfx_info = (struct
atom_gfx_info_v2_2*)
+ (mode_info->atom_context->bios + data_offset);
+ if ((frev == 2) && (crev >= 2))
+ spll->reference_freq =
le32_to_cpu(gfx_info->rlc_gpu_timer_refclk);
+ ret = 0;
+ }
+ }
+
return ret;
}
--
2.25.1
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RE: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hang
[Public]
I check the patch (below) to disable compute queues for raven is not landed
into drm-next. So actually all queues are enabled at this moment. Nirmoy, can
we get your confirmation?
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 97a8f786cf85..9352fcb77fe9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -812,6 +812,13 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t
reg, uint32_t v)
int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
{
if (amdgpu_num_kcq == -1) {
+/* raven firmware currently can not load balance jobs
+* among multiple compute queues. Enable only one
+* compute queue till we have a firmware fix.
+*/
+if (adev->asic_type == CHIP_RAVEN)
+ return 1;
+
return 8;
} else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
dev_warn(adev->dev, "set kernel compute queue number to 8 due
to invalid parameter provided by user\n");
And I am glad to see that we have a solution to fix this issue at current. Nice
work, Changfeng!
Best Regards,
Ray
From: Deucher, Alexander
Sent: Wednesday, May 19, 2021 11:04 AM
To: Chen, Guchun ; Zhu, Changfeng ;
Alex Deucher ; Das, Nirmoy
Cc: Huang, Ray ; amd-gfx list
Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid
compute hang
[Public]
I thought we had disabled all but one of the compute queues on raven due to
this issue or at least disabled the schedulers for the additional queues, but
maybe I'm misremembering.
Alex
From: Chen, Guchun mailto:guchun.c...@amd.com>>
Sent: Tuesday, May 18, 2021 11:00 PM
To: Zhu, Changfeng mailto:changfeng@amd.com>>;
Deucher, Alexander
mailto:alexander.deuc...@amd.com>>; Alex Deucher
mailto:alexdeuc...@gmail.com>>; Das, Nirmoy
mailto:nirmoy@amd.com>>
Cc: Huang, Ray mailto:ray.hu...@amd.com>>; amd-gfx list
mailto:amd-gfx@lists.freedesktop.org>>
Subject: RE: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid
compute hang
[Public]
Nirmoy's patch landed already if I understand correctly.
d41a39dda140 drm/scheduler: improve job distribution with multiple queues
Regards,
Guchun
From: amd-gfx
mailto:amd-gfx-boun...@lists.freedesktop.org>>
On Behalf Of Zhu, Changfeng
Sent: Wednesday, May 19, 2021 10:56 AM
To: Deucher, Alexander
mailto:alexander.deuc...@amd.com>>; Alex Deucher
mailto:alexdeuc...@gmail.com>>; Das, Nirmoy
mailto:nirmoy@amd.com>>
Cc: Huang, Ray mailto:ray.hu...@amd.com>>; amd-gfx list
mailto:amd-gfx@lists.freedesktop.org>>
Subject: RE: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid
compute hang
[Public]
[Public]
Hi Alex,
This is the issue exposed by Nirmoy's patch that provided better load balancing
across queues.
BR,
Changfeng.
From: Deucher, Alexander
mailto:alexander.deuc...@amd.com>>
Sent: Wednesday, May 19, 2021 10:53 AM
To: Zhu, Changfeng mailto:changfeng@amd.com>>; Alex
Deucher mailto:alexdeuc...@gmail.com>>; Das, Nirmoy
mailto:nirmoy@amd.com>>
Cc: Huang, Ray mailto:ray.hu...@amd.com>>; amd-gfx list
mailto:amd-gfx@lists.freedesktop.org>>
Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid
compute hang
[Public]
+ Nirmoy
I thought we disabled all but one of the compute queues on raven due to this
issue. Maybe that patch never landed? Wasn't this the same issue that was
exposed by Nirmoy's patch that provided better load balancing across queues?
Alex
From: amd-gfx
mailto:amd-gfx-boun...@lists.freedesktop.org>>
on behalf of Zhu, Changfeng
mailto:changfeng@amd.com>>
Sent: Tuesday, May 18, 2021 10:28 PM
To: Alex Deucher mailto:alexdeuc...@gmail.com>>
Cc: Huang, Ray mailto:ray.hu...@amd.com>>; amd-gfx list
mailto:amd-gfx@lists.freedesktop.org>>
Subject: RE: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid
compute hang
[AMD Official Use Only - Internal Distribution Only]
Hi Alex.
I have submitted the patch: drm/amdgpu: disable 3DCGCG on picasso/raven1 to
avoid compute hang
Do you mean we have something else to do for re-enabling the extra compute
queues?
BR,
Changfeng.
-Original Message-
From: Alex Deucher mailto:alexdeuc...@gmail.com>>
Sent: Wednesday, May 19, 2021 10:20 AM
To: Zhu, Changfeng mailto:changfeng@amd.com>>
Cc: Huang, Ray mailto:ray.hu...@amd.com>>; amd-gfx list
mailto:amd-gfx@lists.freedesktop.org>>
Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid
compute hang
Care to submit a patch to re-enable the extra compute qu
RE: [PATCH] drm/amdgpu: update secure display TA header
[AMD Public Use]
Reviewed-by: Huang Rui
-Original Message-
From: Su, Jinzhou (Joe)
Sent: Tuesday, March 9, 2021 10:58 AM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Su, Jinzhou (Joe)
Subject: [PATCH] drm/amdgpu: update secure display TA header
update secure display TA header file.
Signed-off-by: Jinzhou Su
---
drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c | 3 +++
drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
index 834440ab9ff7..9cf856c94f94 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
@@ -69,6 +69,9 @@ void psp_securedisplay_parse_resp_status(struct psp_context
*psp,
case TA_SECUREDISPLAY_STATUS__READ_CRC_ERROR:
dev_err(psp->adev->dev, "Secure display: Failed to Read CRC");
break;
+ case TA_SECUREDISPLAY_STATUS__I2C_INIT_ERROR:
+ dev_err(psp->adev->dev, "Secure display: Failed to initialize
I2C.");
+ break;
default:
dev_err(psp->adev->dev, "Secure display: Failed to parse
status: %d\n", status);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h
b/drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h
index 5039375bb1d4..cf8ff064dc72 100644
--- a/drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h
@@ -50,6 +50,7 @@ enum ta_securedisplay_status {
TA_SECUREDISPLAY_STATUS__I2C_WRITE_ERROR = 0x04, /*
Fail to Write to I2C */
TA_SECUREDISPLAY_STATUS__READ_DIO_SCRATCH_ERROR = 0x05, /*Fail Read
DIO Scratch Register*/
TA_SECUREDISPLAY_STATUS__READ_CRC_ERROR = 0x06, /*
Fail to Read CRC*/
+ TA_SECUREDISPLAY_STATUS__I2C_INIT_ERROR = 0x07, /* Failed
to initialize I2C */
TA_SECUREDISPLAY_STATUS__MAX = 0x7FFF,/*
Maximum Value for status*/
};
--
2.17.1
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RE: [PATCH] drm/amd/pm: make the error log more clear for fine grain tuning function
[AMD Official Use Only - Internal Distribution Only]
+ Alex
Hi all,
Recently, many users reported the issue to us that fine grain not enabled.
Actually, most of them are just caused by not switching to “manual” mode.
if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
- dev_warn(smu->adev->dev, "Fine grain is not enabled!\n");
+ dev_warn(smu->adev->dev,
+ "pp_od_clk_voltage is not accessible if
power_dpm_force_perfomance_level is not in manual mode!\n");
We have to need reminder in the warning message to tell the user where they are.
Any objection for this patch? I found Navi series actually didn’t need this
operation to update max/min clock levels. Would you clarify whether dGPU still
needs this before we move the prints into amdgpu_pm.c?
However, in APU fine grain design, patch looks good for me.
Acked-by: Huang Rui mailto:ray.hu...@amd.com>>
Thanks,
Ray
From: Wang, Kevin(Yang)
Sent: Wednesday, January 20, 2021 12:10 PM
To: Du, Xiaojian ; amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Quan, Evan ; Lazar, Lijo
Subject: Re: [PATCH] drm/amd/pm: make the error log more clear for fine grain
tuning function
[AMD Official Use Only - Internal Distribution Only]
From: Du, Xiaojian mailto:xiaojian...@amd.com>>
Sent: Wednesday, January 20, 2021 11:48 AM
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Huang, Ray mailto:ray.hu...@amd.com>>; Quan, Evan
mailto:evan.q...@amd.com>>; Wang, Kevin(Yang)
mailto:kevin1.w...@amd.com>>; Lazar, Lijo
mailto:lijo.la...@amd.com>>; Du, Xiaojian
mailto:xiaojian...@amd.com>>; Du, Xiaojian
mailto:xiaojian...@amd.com>>
Subject: [PATCH] drm/amd/pm: make the error log more clear for fine grain
tuning function
From: Xiaojian Du mailto:xiaojian...@amd.com>>
From: Xiaojian Du mailto:xiaojian...@amd.com>>
This patch is to make the error log more clear for fine grian tuning
function, it covers Raven/Raven2/Picasso/Renoir/Vangogh.
The fine grain tuning function uses the sysfs file -- pp_od_clk_voltage,
but only when another sysfs file -- power_dpm_force_performance_level is
switched to "manual" mode, it is allowd to access "pp_od_clk_voltage".
Signed-off-by: Xiaojian Du mailto:xiaojian...@amd.com>>
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 3 ++-
3 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 88322781e447..ed05a30d1139 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -1487,7 +1487,7 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr
*hwmgr,
}
if (!smu10_data->fine_grain_enabled) {
- pr_err("Fine grain not started\n");
+ pr_err("pp_od_clk_voltage is not accessible if
power_dpm_force_perfomance_level is not in manual mode!\n");
[kevin]:
for above codes, the old one looks better for me, i prefer to keep current
design.
Best Regards,
Kevin
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 6d3c556dbe6b..a847fa66797e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -1452,7 +1452,8 @@ static int vangogh_od_edit_dpm_table(struct smu_context
*smu, enum PP_OD_DPM_TAB
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
- dev_warn(smu->adev->dev, "Fine grain is not enabled!\n");
+ dev_warn(smu->adev->dev,
+ "pp_od_clk_voltage is not accessible if
power_dpm_force_perfomance_level is not in manual mode!\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index ab15570305f7..4ce8fb1d5ce9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -350,7 +350,8 @@ static int renoir_od_edit_dpm_table(struct smu_context *smu,
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
- dev_warn(smu->adev->dev, "Fine grain is not enabled!\n");
+ dev_warn(smu->adev->dev,
+
RE: [PATCH] drm/amdgpu/sdma5.2: soft reset sdma blocks before setup and start sdma
[AMD Public Use]
Reviewed-by: Huang Rui
-Original Message-
From: Hou, Xiaomeng (Matthew)
Sent: Thursday, December 10, 2020 9:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Gao, Likun ; Hou,
Xiaomeng (Matthew)
Subject: [PATCH] drm/amdgpu/sdma5.2: soft reset sdma blocks before setup and
start sdma
Without doing the soft reset, register mmSDMA0_GFX_RB_WPTR's value could not be
reset to 0 when sdma block resumes. That would cause the ring buffer's read and
write pointers not equal and ring test fail. So add the soft reset step.
Signed-off-by: Xiaomeng Hou
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 39 +-
1 file changed, 32 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 39e17aae655f..5acc1e589672 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -807,6 +807,37 @@ static int sdma_v5_2_load_microcode(struct amdgpu_device
*adev)
return 0;
}
+static int sdma_v5_2_soft_reset(void *handle) {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ u32 grbm_soft_reset = 0;
+ u32 tmp;
+ int i;
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
+ GRBM_SOFT_RESET,
SOFT_RESET_SDMA0,
+ 1);
+ grbm_soft_reset <<= i;
+
+ tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
+ tmp |= grbm_soft_reset;
+ DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
+ WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
+ tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
+
+ udelay(50);
+
+ tmp &= ~grbm_soft_reset;
+ WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
+ tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
+
+ udelay(50);
+ }
+
+ return 0;
+}
+
/**
* sdma_v5_2_start - setup and start the async dma engines
*
@@ -838,6 +869,7 @@ static int sdma_v5_2_start(struct amdgpu_device *adev)
msleep(1000);
}
+ sdma_v5_2_soft_reset(adev);
/* unhalt the MEs */
sdma_v5_2_enable(adev, true);
/* enable sdma ring preemption */
@@ -1366,13 +1398,6 @@ static int sdma_v5_2_wait_for_idle(void *handle)
return -ETIMEDOUT;
}
-static int sdma_v5_2_soft_reset(void *handle) -{
- /* todo */
-
- return 0;
-}
-
static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) {
int i, r = 0;
--
2.17.1
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RE: [PATCH] amdgpu: Add mmhub MGCG and MGLS for vangogh
Reviewed-by: Huang Rui -Original Message- From: Su, Jinzhou (Joe) Sent: Friday, October 30, 2020 2:55 PM To: amd-gfx@lists.freedesktop.org Cc: Huang, Ray ; Su, Jinzhou (Joe) Subject: [PATCH] amdgpu: Add mmhub MGCG and MGLS for vangogh Add AMD_CG_SUPPORT_MC_MGCG and AMD_CG_SUPPORT_MC_LS Change-Id: If58cc127a5b5b2449253af6d0f7f2522628639a3 Signed-off-by: Jinzhou.Su --- drivers/gpu/drm/amd/amdgpu/nv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 026e0a8fd526..1f8659a1a4cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -951,6 +951,8 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS | + AMD_CG_SUPPORT_MC_MGCG | + AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amd/powerplay: update smu12_driver_if.h to align with pmfw
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Huang Rui
-Original Message-
From: Liang, Prike
Sent: Monday, April 20, 2020 10:11 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Liang, Prike
Subject: [PATCH] drm/amd/powerplay: update smu12_driver_if.h to align with pmfw
Update the smu12_driver_if.h header to follow the pmfw release.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/powerplay/inc/smu12_driver_if.h| 40 ++
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
b/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
index 2f85a34..e9315eb 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
@@ -27,7 +27,7 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if // any structure is
changed in this file -#define SMU12_DRIVER_IF_VERSION 11
+#define SMU12_DRIVER_IF_VERSION 14
typedef struct {
int32_t value;
@@ -154,15 +154,19 @@ typedef enum {
} CLOCK_IDs_e;
// Throttler Status Bitmask
-#define THROTTLER_STATUS_BIT_SPL0
-#define THROTTLER_STATUS_BIT_FPPT 1
-#define THROTTLER_STATUS_BIT_SPPT 2
-#define THROTTLER_STATUS_BIT_SPPT_APU 3
-#define THROTTLER_STATUS_BIT_THM_CORE 4
-#define THROTTLER_STATUS_BIT_THM_GFX5
-#define THROTTLER_STATUS_BIT_THM_SOC6
-#define THROTTLER_STATUS_BIT_TDC_VDD7
-#define THROTTLER_STATUS_BIT_TDC_SOC8
+#define THROTTLER_STATUS_BIT_SPL0
+#define THROTTLER_STATUS_BIT_FPPT 1
+#define THROTTLER_STATUS_BIT_SPPT 2
+#define THROTTLER_STATUS_BIT_SPPT_APU 3
+#define THROTTLER_STATUS_BIT_THM_CORE 4
+#define THROTTLER_STATUS_BIT_THM_GFX5
+#define THROTTLER_STATUS_BIT_THM_SOC6
+#define THROTTLER_STATUS_BIT_TDC_VDD7
+#define THROTTLER_STATUS_BIT_TDC_SOC8
+#define THROTTLER_STATUS_BIT_PROCHOT_CPU9
+#define THROTTLER_STATUS_BIT_PROCHOT_GFX 10
+#define THROTTLER_STATUS_BIT_EDC_CPU 11
+#define THROTTLER_STATUS_BIT_EDC_GFX 12
typedef struct {
uint16_t ClockFrequency[CLOCK_COUNT]; //[MHz] @@ -180,7 +184,7 @@ typedef
struct {
uint16_t Power[2];//[mW] indices: VDDCR_VDD, VDDCR_SOC
uint16_t FanPwm; //[milli]
- uint16_t CurrentSocketPower; //[mW]
+ uint16_t CurrentSocketPower; //[W]
uint16_t CoreFrequency[8];//[MHz]
uint16_t CorePower[8];//[mW]
@@ -193,10 +197,16 @@ typedef struct {
uint16_t ThrottlerStatus;
uint16_t spare;
- uint16_t StapmOriginalLimit; //[mW]
- uint16_t StapmCurrentLimit; //[mW]
- uint16_t ApuPower; //[mW]
- uint16_t dGpuPower; //[mW]
+ uint16_t StapmOriginalLimit; //[W]
+ uint16_t StapmCurrentLimit; //[W]
+ uint16_t ApuPower;//[W]
+ uint16_t dGpuPower; //[W]
+
+ uint16_t VddTdcValue; //[mA]
+ uint16_t SocTdcValue; //[mA]
+ uint16_t VddEdcValue; //[mA]
+ uint16_t SocEdcValue; //[mA]
+ uint16_t reserve[2];
} SmuMetrics_t;
--
2.7.4
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RE: [PATCH] drm/amd/powerplay: fix resume failed as smu table initialize early exit
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Huang Rui
-Original Message-
From: Liang, Prike
Sent: Wednesday, April 15, 2020 11:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Liang, Prike
Subject: [PATCH] drm/amd/powerplay: fix resume failed as smu table initialize
early exit
When the amdgpu in the suspend/resume loop need notify the dpm disabled,
otherwise the smu table will be uninitialize and result in resume failed.
Signed-off-by: Prike Liang
Tested-by: Mengbing Wang
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 95eb445..7ddaea8 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -895,12 +895,17 @@ static int renoir_read_sensor(struct smu_context *smu,
static bool renoir_is_dpm_running(struct smu_context *smu) {
+ struct amdgpu_device *adev = smu->adev;
+
/*
* Until now, the pmfw hasn't exported the interface of SMU
* feature mask to APU SKU so just force on all the feature
* at early initial stage.
*/
- return true;
+ if (adev->in_suspend)
+ return false;
+ else
+ return true;
}
--
2.7.4
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RE: [PATCH] drm/amdgpu/vcn: fix gfxoff issue
[AMD Official Use Only - Internal Distribution Only]
This workaround is to fix the s3 issue with video playback on raven1 before.
Changfeng, can you have a quick test whether we don't need it right now?
Thanks,
Ray
-Original Message-
From: Zhu, Changfeng
Sent: Wednesday, April 15, 2020 10:12 AM
To: Zhu, James ; Alex Deucher ;
Zhang, Hawking ; Huang, Ray
Cc: amd-gfx list
Subject: RE: [PATCH] drm/amdgpu/vcn: fix gfxoff issue
[AMD Official Use Only - Internal Distribution Only]
+Ray
BR,
Changfeng.
-Original Message-
From: Zhu, James
Sent: Tuesday, April 14, 2020 11:00 PM
To: Alex Deucher ; Zhu, James ;
Zhang, Hawking
Cc: amd-gfx list ; Zhu, Changfeng
Subject: Re: [PATCH] drm/amdgpu/vcn: fix gfxoff issue
+Hawking
Hi Hawking,
can we drop this WA?
Thanks!
James
On 2020-04-14 10:52 a.m., James Zhu wrote:
> +Rex
>
> This is introduce by below patch.
>
> commit 3fded222f4bf7f4c56ef4854872a39a4de08f7a8
> Author: Rex Zhu
> Date: Fri Jul 27 17:00:02 2018 +0800
>
> drm/amdgpu: Disable gfx off if VCN is busy
>
> this patch is a workaround for the gpu hang
> at video begin/end time if gfx off is enabled.
>
> Reviewed-by: Hawking Zhang
> Signed-off-by: Rex Zhu
> Signed-off-by: Alex Deucher
>
>
> On 2020-04-14 10:22 a.m., Alex Deucher wrote:
>> On Tue, Apr 14, 2020 at 8:05 AM James Zhu wrote:
>>> Turn off gfxoff control when vcn is gated.
>>>
>>> Signed-off-by: James Zhu
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 +---
>>> 1 file changed, 5 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>> index dab34f6..aa9a7a5 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>> @@ -369,9 +369,11 @@ void amdgpu_vcn_ring_begin_use(struct
>>> amdgpu_ring *ring) cancel_delayed_work_sync(&adev->vcn.idle_work);
>>>
>>> mutex_lock(&adev->vcn.vcn_pg_lock);
>>> - amdgpu_gfx_off_ctrl(adev, false);
>>> - amdgpu_device_ip_set_powergating_state(adev,
>>> AMD_IP_BLOCK_TYPE_VCN,
>>> - AMD_PG_STATE_UNGATE);
>>> + if (adev->vcn.cur_state == AMD_PG_STATE_GATE) {
>>> + amdgpu_gfx_off_ctrl(adev, false);
>>> + amdgpu_device_ip_set_powergating_state(adev,
>>> AMD_IP_BLOCK_TYPE_VCN,
>>> + AMD_PG_STATE_UNGATE);
>>> + }
>>>
>> Why are we touching gfxoff with VCN? Was this a leftover from bring
>> up? Can we just drop all of this gfxoff stuff from VCN handling? I
>> don't see why there would be a dependency.
>>
>> Alex
>>
>>> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
>>> struct dpg_pause_state new_state;
>>> --
>>> 2.7.4
>>>
>>> ___
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
>>> sts.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%
>>> 7CJames.Zhu%40amd.com%7C3dd9135c717a4b3011e308d7e07f52b6%7C3dd8961fe
>>> 4884e608e11a82d994e183d%7C0%7C0%7C637224709763391845&sdata=Y%2Bt
>>> sJQNB1TXCQ9v86DW%2F0FC63gOSHsfzzZFu0MDvCHw%3D&reserved=0
>>>
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RE: [PATCH libdrm 0/4] amdgpu: use amdgpu_cs_submit_raw2 for amdgpu tests
[AMD Public Use] Hi Alex, MR = merge request? Should I create account to send merge request in the freedesktop gitlab? Thanks, Ray From: Deucher, Alexander Sent: Tuesday, February 11, 2020 10:30 PM To: Christian König ; Huang, Ray ; amd-gfx@lists.freedesktop.org Cc: Pelloux-prayer, Pierre-eric ; Olsak, Marek ; Liu, Aaron ; Tuikov, Luben ; Koenig, Christian Subject: Re: [PATCH libdrm 0/4] amdgpu: use amdgpu_cs_submit_raw2 for amdgpu tests [AMD Public Use] Also, libdrm changes should go through a gitlab MR now. Alex From: Christian König mailto:ckoenig.leichtzumer...@gmail.com>> Sent: Tuesday, February 11, 2020 6:39 AM To: Huang, Ray mailto:ray.hu...@amd.com>>; amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org> mailto:amd-gfx@lists.freedesktop.org>> Cc: Pelloux-prayer, Pierre-eric mailto:pierre-eric.pelloux-pra...@amd.com>>; Olsak, Marek mailto:marek.ol...@amd.com>>; Liu, Aaron mailto:aaron@amd.com>>; Tuikov, Luben mailto:luben.tui...@amd.com>>; Deucher, Alexander mailto:alexander.deuc...@amd.com>>; Koenig, Christian mailto:christian.koe...@amd.com>> Subject: Re: [PATCH libdrm 0/4] amdgpu: use amdgpu_cs_submit_raw2 for amdgpu tests Looks good on first glance, but Marek and/or Pierre can probably better judge than me. Christian. Am 11.02.20 um 12:22 schrieb Huang Rui: > So far, the amdgpu_cs_submit_raw2 is used for MesaGL, however the amdgpu tests > still use the legacy interface. So we would like to make amdgpu tests verify > the > amdgpu_cs_submit_raw2 API. > > Thanks, > Ray > > Huang Rui (4): >amdgpu: use alloca for dependencies and sem_dependencies >amdgpu: use amdgpu_cs_submit_raw2 in amdgpu_cs_submit >amdgpu: remove the un-used chunk_array >amdgpu: clean up the cs structure variable > > amdgpu/amdgpu_cs.c | 36 +--- > 1 file changed, 13 insertions(+), 23 deletions(-) > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu/smu: use unified variable smu->is_apu to check apu asic platform
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Huang Rui
-Original Message-
From: Wang, Kevin(Yang)
Sent: Monday, December 23, 2019 6:28 PM
To: amd-gfx-boun...@lists.freedesktop.org
Cc: Feng, Kenneth ; Huang, Ray ;
Liang, Prike ; Deucher, Alexander
; Wang, Kevin(Yang)
Subject: [PATCH] drm/amdgpu/smu: use unified variable smu->is_apu to check apu
asic platform
use unified variable smu->is_apu to check apu asic in smu driver.
related patch:
drm/amd/powerplay: bypass dpm_context null pointer check guard for some smu
series
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 -
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 6 +++---
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index f76a1717ffbd..6aa27a1e9495 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -643,12 +643,11 @@ int smu_feature_init_dpm(struct smu_context *smu)
int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask
mask) {
- struct amdgpu_device *adev = smu->adev;
struct smu_feature *feature = &smu->smu_feature;
int feature_id;
int ret = 0;
- if (adev->flags & AMD_IS_APU)
+ if (smu->is_apu)
return 1;
feature_id = smu_feature_get_index(smu, mask); @@ -1241,7 +1240,7 @@
static int smu_hw_init(void *handle)
return ret;
}
- if (adev->flags & AMD_IS_APU) {
+ if (smu->is_apu) {
smu_powergate_sdma(&adev->smu, false);
smu_powergate_vcn(&adev->smu, false);
smu_powergate_jpeg(&adev->smu, false); @@ -1300,7 +1299,7 @@
static int smu_hw_fini(void *handle)
struct smu_table_context *table_context = &smu->smu_table;
int ret = 0;
- if (adev->flags & AMD_IS_APU) {
+ if (smu->is_apu) {
smu_powergate_sdma(&adev->smu, true);
smu_powergate_vcn(&adev->smu, true);
smu_powergate_jpeg(&adev->smu, true); @@ -1376,7 +1375,7 @@
static int smu_suspend(void *handle)
struct smu_context *smu = &adev->smu;
bool baco_feature_is_enabled = false;
- if(!(adev->flags & AMD_IS_APU))
+ if(!smu->is_apu)
baco_feature_is_enabled = smu_feature_is_enabled(smu,
SMU_FEATURE_BACO_BIT);
ret = smu_system_features_control(smu, false); diff --git
a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 2ac7f2f231b6..9e27462d0f4e 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -159,7 +159,7 @@ int smu_v12_0_check_fw_version(struct smu_context *smu)
int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate) {
- if (!(smu->adev->flags & AMD_IS_APU))
+ if (!smu->is_apu)
return 0;
if (gate)
@@ -170,7 +170,7 @@ int smu_v12_0_powergate_sdma(struct smu_context *smu, bool
gate)
int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate) {
- if (!(smu->adev->flags & AMD_IS_APU))
+ if (!smu->is_apu)
return 0;
if (gate)
@@ -181,7 +181,7 @@ int smu_v12_0_powergate_vcn(struct smu_context *smu, bool
gate)
int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate) {
- if (!(smu->adev->flags & AMD_IS_APU))
+ if (!smu->is_apu)
return 0;
if (gate)
--
2.17.1
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Re: [PATCH] drm/amd/powerplay: suppress nonsupport profile mode overrun message
[AMD Official Use Only - Internal Distribution Only]
On Thu, Dec 19, 2019 at 03:04:12PM +0800, Dai, Yuxian (David) wrote:
> For we don't support the mode, so shouldn't print the error message, or
> regard as a error.
> For log message, the error is high level .maybe change from "error" to
> "warning" , it will be much better.
>
>
> -Original Message-
> From: Liang, Prike
> Sent: Thursday, December 19, 2019 2:46 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan ; Huang, Ray ; Dai,
> Yuxian (David) ; Liang, Prike
> Subject: [PATCH] drm/amd/powerplay: suppress nonsupport profile mode overrun
> message
>
> SMU12 not support WORKLOAD_DEFAULT_BIT and WORKLOAD_PPLIB_POWER_SAVING_BIT.
>
Probably smu firmware doesn't expose the feature mask to driver. Can you
confirmware with smu firmware guy whehter this feature is really disabled
or not in SMU12. If that, in my view, issue the message
SMU_MSG_SetWorkloadMask with an unsupported state, it doesn't make sense.
Just work around this with one time warnning is not a good solution.
Thanks,
Ray
> Signed-off-by: Prike Liang
> ---
> drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 784903a3..f9a1817 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -550,14 +550,18 @@ static int renoir_set_power_profile_mode(struct
> smu_context *smu, long *input, u
> /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
> workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
> if (workload_type < 0) {
> - pr_err("Unsupported power profile mode %d on
> RENOIR\n",smu->power_profile_mode);
> + /*
> + * TODO: If some case need switch to powersave/default power
> mode
> + * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for
> power saving.
> + */
> + pr_err_once("Unsupported power profile mode %d on
> RENOIR\n",smu->power_profile_mode);
> return -EINVAL;
> }
>
> ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
> 1 << workload_type);
> if (ret) {
> - pr_err("Fail to set workload type %d\n", workload_type);
> + pr_err_once("Fail to set workload type %d\n", workload_type);
> return ret;
> }
>
> --
> 2.7.4
>
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Re: [PATCH 2/2] drm/amdkfd: expose num_cp_queues data field to topology node
[AMD Official Use Only - Internal Distribution Only]
On Wed, Dec 18, 2019 at 07:40:26AM +0800, Kuehling, Felix wrote:
> See comment inline. Other than that, the series looks good to me.
>
> On 2019-12-16 2:02, Huang Rui wrote:
> > Thunk driver would like to know the num_cp_queues data, however this data
> > relied
> > on different asic specific. So it's better to get it from kfd driver.
> >
> > Signed-off-by: Huang Rui
> > ---
> > drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 3 +++
> > drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 3 ++-
> > 2 files changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > index cc01ccd..203c823 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > @@ -488,6 +488,8 @@ static ssize_t node_show(struct kobject *kobj, struct
> > attribute *attr,
> > dev->node_props.num_sdma_xgmi_engines);
> > sysfs_show_32bit_prop(buffer, "num_sdma_queues_per_engine",
> > dev->node_props.num_sdma_queues_per_engine);
> > + sysfs_show_32bit_prop(buffer, "num_cp_queues",
> > + dev->node_props.num_cp_queues);
> >
> > if (dev->gpu) {
> > log_max_watch_addr =
> > @@ -1316,6 +1318,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
> > dev->node_props.num_gws = (hws_gws_support &&
> > dev->gpu->dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) ?
> > amdgpu_amdkfd_get_num_gws(dev->gpu->kgd) : 0;
> > + dev->node_props.num_cp_queues = get_queues_num(dev->gpu->dqm);
> >
> > kfd_fill_mem_clk_max_info(dev);
> > kfd_fill_iolink_non_crat_info(dev);
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> > b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> > index 9346cc1..e447901 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> > @@ -27,7 +27,7 @@
> > #include
> > #include "kfd_crat.h"
> >
> > -#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 28
> > +#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 24
>
> I don't see why you need to change the name size here. I'm not aware of
> any requirement that the structure size cannot change. This comment
> applies to patch 1 as well.
>
Oh, sorry, I miss read this field as "reserved", so I kept the struct size.
Will updated in V2.
Thanks,
Ray
> Regards,
> Felix
>
> >
> > #define HSA_CAP_HOT_PLUGGABLE 0x0001
> > #define HSA_CAP_ATS_PRESENT 0x0002
> > @@ -82,6 +82,7 @@ struct kfd_node_properties {
> > uint32_t num_sdma_engines;
> > uint32_t num_sdma_xgmi_engines;
> > uint32_t num_sdma_queues_per_engine;
> > + uint32_t num_cp_queues;
> > char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
> > };
> >
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Re: [PATCH] drm/amdgpu: enable gfxoff for raven1 refresh
On Fri, Dec 13, 2019 at 11:24:00AM +0800, Zhu, Changfeng wrote: > From: changzhu > > When smu version is larger than 0x41e2b, it will load > raven_kicker_rlc.bin.To enable gfxoff for raven_kicker_rlc.bin,it > needs to avoid adev->pm.pp_feature &= ~PP_GFXOFF_MASK when it loads > raven_kicker_rlc.bin. > > Change-Id: I4dffa1783c9ceb5d40df9756d821e2cd7feff84d > Signed-off-by: changzhu Reviewed-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 --- > 1 file changed, 4 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index ea58d0e5be4c..68409bb7c9e0 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -1038,17 +1038,10 @@ static void gfx_v9_0_check_if_need_gfxoff(struct > amdgpu_device *adev) > case CHIP_VEGA20: > break; > case CHIP_RAVEN: > - /* Disable GFXOFF on original raven. There are combinations > - * of sbios and platforms that are not stable. > - */ > - if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)) > - adev->pm.pp_feature &= ~PP_GFXOFF_MASK; > - else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) > - &&((adev->gfx.rlc_fw_version != 106 && > - adev->gfx.rlc_fw_version < 531) || > - (adev->gfx.rlc_fw_version == 53815) || > - (adev->gfx.rlc_feature_version < 1) || > - !adev->gfx.rlc.is_rlc_v2_1)) > + if (!(adev->rev_id >= 0x8 || > + adev->pdev->device == 0x15d8) && > + (adev->pm.fw_version < 0x41e2b || /* not raven1 fresh */ > + !adev->gfx.rlc.is_rlc_v2_1)) /* without rlc save restore > ucodes */ > adev->pm.pp_feature &= ~PP_GFXOFF_MASK; > > if (adev->pm.pp_feature & PP_GFXOFF_MASK) > -- > 2.17.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: enable gfxoff for raven1 refresh
[AMD Official Use Only - Internal Distribution Only] On Thu, Dec 12, 2019 at 06:01:55PM +0800, Zhu, Changfeng wrote: > From: changzhu > > When smu version is larger than 0x41e2b, it will load > raven_kicker_rlc.bin.To enable gfxoff for raven_kicker_rlc.bin,it > needs to avoid adev->pm.pp_feature &= ~PP_GFXOFF_MASK when it loads > raven_kicker_rlc.bin. > > Change-Id: I4dffa1783c9ceb5d40df9756d821e2cd7feff84d > Signed-off-by: changzhu > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 - > 1 file changed, 4 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index ea58d0e5be4c..56a38d67a949 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -1038,17 +1038,12 @@ static void gfx_v9_0_check_if_need_gfxoff(struct > amdgpu_device *adev) > case CHIP_VEGA20: > break; > case CHIP_RAVEN: > - /* Disable GFXOFF on original raven. There are combinations > - * of sbios and platforms that are not stable. > - */ Please add comments that only enable gfxoff on raven kicker so far. > - if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)) > - adev->pm.pp_feature &= ~PP_GFXOFF_MASK; > - else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) > - &&((adev->gfx.rlc_fw_version != 106 && > - adev->gfx.rlc_fw_version < 531) || > + if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) > + &&((adev->gfx.rlc_fw_version < 531) || > (adev->gfx.rlc_fw_version == 53815) || > (adev->gfx.rlc_feature_version < 1) || > + !adev->gfx.rlc.is_rlc_v2_1) > + &&(adev->pm.fw_version < 0x41e2b)) I think the if should be below: if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) && adev->pm.fw_version < 0x41e2b /* not raven1 fresh */ || !adev->gfx.rlc.is_rlc_v2_1) /* without rlc save restore ucodes */ Thanks, Ray > adev->pm.pp_feature &= ~PP_GFXOFF_MASK; > > if (adev->pm.pp_feature & PP_GFXOFF_MASK) > -- > 2.17.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: avoid using invalidate semaphore for picasso(v2)
On Tue, Dec 10, 2019 at 10:55:13AM +0800, Zhu, Changfeng wrote:
> From: changzhu
>
> It may cause timeout waiting for sem acquire in VM flush when using
> invalidate semaphore for picasso. So it needs to avoid using invalidate
> semaphore for piasso.
>
> Change-Id: I6dc552bde180919cd5ba6c81c6d9e3f800043b03
> Signed-off-by: changzhu
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 28 +++
> 1 file changed, 20 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 231ea9762cb5..601667246a1c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -464,8 +464,11 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device
> *adev, uint32_t vmid,
>*/
>
> /* TODO: It needs to continue working on debugging with semaphore for
> GFXHUB as well. */
> - if (vmhub == AMDGPU_MMHUB_0 ||
> - vmhub == AMDGPU_MMHUB_1) {
> + if ((vmhub == AMDGPU_MMHUB_0 ||
> + vmhub == AMDGPU_MMHUB_1) &&
> + (!(adev->asic_type == CHIP_RAVEN &&
> +adev->rev_id < 0x8 &&
> +adev->pdev->device == 0x15d8))) {
> for (j = 0; j < adev->usec_timeout; j++) {
> /* a read return value of 1 means semaphore acuqire */
> tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
> @@ -495,8 +498,11 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device
> *adev, uint32_t vmid,
> }
>
> /* TODO: It needs to continue working on debugging with semaphore for
> GFXHUB as well. */
> - if (vmhub == AMDGPU_MMHUB_0 ||
> - vmhub == AMDGPU_MMHUB_1)
> + if ((vmhub == AMDGPU_MMHUB_0 ||
> + vmhub == AMDGPU_MMHUB_1) &&
> + (!(adev->asic_type == CHIP_RAVEN &&
> +adev->rev_id < 0x8 &&
> +adev->pdev->device == 0x15d8)))
> /*
>* add semaphore release after invalidation,
>* write with 0 means semaphore release
> @@ -527,8 +533,11 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct
> amdgpu_ring *ring,
>*/
>
> /* TODO: It needs to continue working on debugging with semaphore for
> GFXHUB as well. */
> - if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> - ring->funcs->vmhub == AMDGPU_MMHUB_1)
> + if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> + ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
> + (!(adev->asic_type == CHIP_RAVEN &&
> +adev->rev_id < 0x8 &&
> +adev->pdev->device == 0x15d8)))
> /* a read return value of 1 means semaphore acuqire */
> amdgpu_ring_emit_reg_wait(ring,
> hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
> @@ -544,8 +553,11 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct
> amdgpu_ring *ring,
> req, 1 << vmid);
>
> /* TODO: It needs to continue working on debugging with semaphore for
> GFXHUB as well. */
> - if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> - ring->funcs->vmhub == AMDGPU_MMHUB_1)
> + if ((ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> + ring->funcs->vmhub == AMDGPU_MMHUB_1) &&
> + (!(adev->asic_type == CHIP_RAVEN &&
> +adev->rev_id < 0x8 &&
> +adev->pdev->device == 0x15d8)))
> /*
>* add semaphore release after invalidation,
>* write with 0 means semaphore release
> --
> 2.17.1
>
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RE: [PATCH] drm/amdkfd: fix a minor typo on user queue init
Sorry, please ignore this patch. Just misunderstood before.
Thanks,
Ray
-Original Message-
From: Huang, Ray
Sent: Wednesday, December 4, 2019 3:22 PM
To: amd-gfx@lists.freedesktop.org; Kuehling, Felix ;
Zhao, Yong
Cc: Deucher, Alexander ; Huang, Ray
Subject: [PATCH] drm/amdkfd: fix a minor typo on user queue init
Fix PQM -> DQM.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index d3eacf7..b7db622 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -183,7 +183,7 @@ static int init_user_queue(struct process_queue_manager
*pqm,
(*q)->device = dev;
(*q)->process = pqm->process;
- pr_debug("PQM After init queue");
+ pr_debug("DQM After init queue");
return retval;
}
--
2.7.4
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Re: [PATCH] drm/amdgpu: invalidate mmhub semphore workaround in gmc9/gmc10
[AMD Official Use Only - Internal Distribution Only]
On Thu, Nov 21, 2019 at 11:47:15PM +0800, Zhu, Changfeng wrote:
> From: changzhu
>
> It may lose gpuvm invalidate acknowldege state across power-gating off
> cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire
> before invalidation and semaphore release after invalidation.
>
> After adding semaphore acquire before invalidation, the semaphore
> register become read-only if another process try to acquire semaphore.
> Then it will not be able to release this semaphore. Then it may cause
> deadlock problem. If this deadlock problem happens, it needs a semaphore
> firmware fix.
>
> Change-Id: I9942a2f451265c1f1038ccfe2f70042c7c8118af
Please remove the chang-id, we don't do gerrit review.
> Signed-off-by: changzhu
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 52 ++
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 52 ++
> drivers/gpu/drm/amd/amdgpu/soc15.h | 4 +-
> 3 files changed, 106 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index af2615ba52aa..e0104b985c42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -234,6 +234,27 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device
> *adev, uint32_t vmid,
> const unsigned eng = 17;
> unsigned int i;
>
> + spin_lock(&adev->gmc.invalidate_lock);
> + /*
> + * It may lose gpuvm invalidate acknowldege state across power-gating
> + * off cycle, add semaphore acquire before invalidation and semaphore
> + * release after invalidation to avoid entering power gated state
> + * to WA the Issue
> + */
Please add the TODO here, and mention you will continue working on
debugging with semaphore for GFXHUB as well. And remove the checking once
you addressed the issue with CP designer.
And the comments should be added before all checking here for "MMHUB".
With that fixed, the patch is Acked-by: Huang Rui
> + if (vmhub == AMDGPU_MMHUB_0 ||
> + vmhub == AMDGPU_MMHUB_1) {
> + for (i = 0; i < adev->usec_timeout; i++) {
> + /* a read return value of 1 means semaphore acuqire */
> + tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
> + if (tmp & 0x1)
> + break;
> + udelay(1);
> + }
> +
> + if (i >= adev->usec_timeout)
> + DRM_ERROR("Timeout waiting for sem acquire in VM
> flush!\n");
> + }
> +
> WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
>
> /*
> @@ -253,6 +274,16 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device
> *adev, uint32_t vmid,
> udelay(1);
> }
>
> + /*
> + * add semaphore release after invalidation,
> + * write with 0 means semaphore release
> + */
> + if (vmhub == AMDGPU_MMHUB_0 ||
> + vmhub == AMDGPU_MMHUB_1)
> + WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
> +
> + spin_unlock(&adev->gmc.invalidate_lock);
> +
> if (i < adev->usec_timeout)
> return;
>
> @@ -338,6 +369,19 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct
> amdgpu_ring *ring,
> uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
> unsigned eng = ring->vm_inv_eng;
>
> + /*
> + * It may lose gpuvm invalidate acknowldege state across power-gating
> + * off cycle, add semaphore acquire before invalidation and semaphore
> + * release after invalidation to avoid entering power gated state
> + * to WA the Issue
> + */
> +
> + /* a read return value of 1 means semaphore acuqire */
> + if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> + ring->funcs->vmhub == AMDGPU_MMHUB_1)
> + amdgpu_ring_emit_reg_wait(ring,
> + hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
> +
> amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
> lower_32_bits(pd_addr));
>
> @@ -348,6 +392,14 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct
> amdgpu_ring *ring,
> hub->vm_inv_eng0_ack + eng,
> req, 1 << vmid);
>
> + /*
> + * add semaphore release after invalidation,
> + * write with 0 means semaphore release
> + */
> + if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
> + ring->funcs->vmhub == AMDGPU_MMHUB_1)
> + amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
> +
> return pd_addr;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index b7f2b184e9b8..816fdd602c85 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -4
Re: [PATCH 1/5] drm/amdgpu: expand sdma copy_buffer interface with tmz parameter
Series are Reviewed-by: Huang Rui
On Mon, Nov 18, 2019 at 01:18:32PM +0800, Liu, Aaron wrote:
> This patch expands sdma copy_buffer interface with tmz parameter.
>
> Signed-off-by: Aaron Liu
> Reviewed-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 5 +++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c| 3 ++-
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++-
> 8 files changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> index 761ff8b..b313465 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> @@ -79,7 +79,8 @@ struct amdgpu_buffer_funcs {
>/* dst addr in bytes */
>uint64_t dst_offset,
>/* number of byte to transfer */
> - uint32_t byte_count);
> + uint32_t byte_count,
> + bool tmz);
>
> /* maximum bytes in a single operation */
> uint32_tfill_max_bytes;
> @@ -97,7 +98,7 @@ struct amdgpu_buffer_funcs {
>uint32_t byte_count);
> };
>
> -#define amdgpu_emit_copy_buffer(adev, ib, s, d, b)
> (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
> +#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t)
> (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t))
> #define amdgpu_emit_fill_buffer(adev, ib, s, d, b)
> (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
>
> struct amdgpu_sdma_instance *
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 339088d..c08c15e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -2022,7 +2022,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object
> *bo,
> dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
> dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
> amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
> - dst_addr, num_bytes);
> + dst_addr, num_bytes, false);
>
> amdgpu_ring_pad_ib(ring, &job->ibs[0]);
> WARN_ON(job->ibs[0].length_dw > num_dw);
> @@ -2093,7 +2093,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
> uint64_t src_offset,
> uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
>
> amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
> - dst_offset, cur_size_in_bytes);
> + dst_offset, cur_size_in_bytes, false);
>
> src_offset += cur_size_in_bytes;
> dst_offset += cur_size_in_bytes;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index c45304f..82cdb8f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -1313,7 +1313,8 @@ static void cik_sdma_set_irq_funcs(struct amdgpu_device
> *adev)
> static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
> uint64_t src_offset,
> uint64_t dst_offset,
> - uint32_t byte_count)
> + uint32_t byte_count,
> + bool tmz)
> {
> ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
> SDMA_COPY_SUB_OPCODE_LINEAR, 0);
> ib->ptr[ib->length_dw++] = byte_count;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index a101758..89e8c74 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -1200,7 +1200,8 @@ static void sdma_v2_4_set_irq_funcs(struct
> amdgpu_device *adev)
> static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
> uint64_t src_offset,
> uint64_t dst_offset,
> -uint32_t byte_count)
> +uint32_t byte_count,
> +bool tmz)
> {
> ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
> SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 5f4e2c6..011fd12 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -
Re: [PATCH 12/12] tests/amdgpu: add test to submit a sdma command with secure context
On Fri, Nov 15, 2019 at 11:34:55AM +0800, Liu, Aaron wrote:
> This patch add test to submit a sdma command with secure context.
>
> Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
> ---
> tests/amdgpu/security_tests.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/tests/amdgpu/security_tests.c b/tests/amdgpu/security_tests.c
> index 0bb4ad2..eb239f4 100644
> --- a/tests/amdgpu/security_tests.c
> +++ b/tests/amdgpu/security_tests.c
> @@ -33,6 +33,8 @@ static uint32_t minor_version;
>
> static void amdgpu_security_alloc_buf_test(void);
> static void amdgpu_security_gfx_submission_test(void);
> +static void amdgpu_security_sdma_submission_test(void);
> +
>
> CU_BOOL suite_security_tests_enable(void)
> {
> @@ -77,6 +79,7 @@ int suite_security_tests_clean(void)
> CU_TestInfo security_tests[] = {
> { "allocate secure buffer test", amdgpu_security_alloc_buf_test },
> { "graphics secure command submission",
> amdgpu_security_gfx_submission_test },
> + { "sdma secure command submission",
> amdgpu_security_sdma_submission_test },
> CU_TEST_INFO_NULL,
> };
>
> @@ -122,3 +125,10 @@ static void amdgpu_security_gfx_submission_test(void)
>
> AMDGPU_HW_IP_GFX,
> true);
> }
> +
> +static void amdgpu_security_sdma_submission_test(void)
> +{
> + amdgpu_command_submission_write_linear_helper_with_secure(device_handle,
> +
> AMDGPU_HW_IP_DMA,
> + true);
> +}
> --
> 2.7.4
>
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Re: [PATCH 10/12] tests/amdgpu: add test to submit a gfx command with secure context
On Fri, Nov 15, 2019 at 11:34:53AM +0800, Liu, Aaron wrote:
> This patch is to test the command submission with secure context.
>
> Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
> ---
> tests/amdgpu/security_tests.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/tests/amdgpu/security_tests.c b/tests/amdgpu/security_tests.c
> index a3807ee..0bb4ad2 100644
> --- a/tests/amdgpu/security_tests.c
> +++ b/tests/amdgpu/security_tests.c
> @@ -32,6 +32,7 @@ static uint32_t major_version;
> static uint32_t minor_version;
>
> static void amdgpu_security_alloc_buf_test(void);
> +static void amdgpu_security_gfx_submission_test(void);
>
> CU_BOOL suite_security_tests_enable(void)
> {
> @@ -75,6 +76,7 @@ int suite_security_tests_clean(void)
>
> CU_TestInfo security_tests[] = {
> { "allocate secure buffer test", amdgpu_security_alloc_buf_test },
> + { "graphics secure command submission",
> amdgpu_security_gfx_submission_test },
> CU_TEST_INFO_NULL,
> };
>
> @@ -113,3 +115,10 @@ static void amdgpu_security_alloc_buf_test(void)
> r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
> CU_ASSERT_EQUAL(r, 0);
> }
> +
> +static void amdgpu_security_gfx_submission_test(void)
> +{
> + amdgpu_command_submission_write_linear_helper_with_secure(device_handle,
> +
> AMDGPU_HW_IP_GFX,
> + true);
> +}
> --
> 2.7.4
>
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Re: [PATCH 09/12] tests/amdgpu: add atomic_mem cp_packet to verify the secure buffer
On Fri, Nov 15, 2019 at 11:34:52AM +0800, Liu, Aaron wrote:
> Secure buffer is only able to be read with trusted ip block.
> So we need use GFX ip to read it back instead of CPU.
> Steps:
> 1. use write_data packet to write 0xdeadbeaf to secure buffer,
> 2. use atmoic_mem packet and ATOMIC_CMPSWAP_RTN_32 opcode to compare
> the cmp_data(0xdeadbeaf) to the written data which has been encrypted.
> If the result is equal, then overwrite the src_data(0x12345678) to the
> secure buffer and return directly. Otherwise loop again until gfx timeout
> and the secure buffer data unchanged.
>
> Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
> ---
> tests/amdgpu/basic_tests.c | 43 +--
> 1 file changed, 41 insertions(+), 2 deletions(-)
>
> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
> index 956be93..907237e 100644
> --- a/tests/amdgpu/basic_tests.c
> +++ b/tests/amdgpu/basic_tests.c
> @@ -160,6 +160,20 @@ CU_TestInfo basic_tests[] = {
>* 2 - ce
>*/
>
> +#define PACKET3_ATOMIC_MEM 0x1E
> +#define TC_OP_ATOMIC_CMPSWAP_RTN_32 0x0008
> +#define ATOMIC_MEM_COMMAND(x) ((x) << 8)
> +/* 0 - single_pass_atomic.
> + * 1 - loop_until_compare_satisfied.
> + */
> +#define ATOMIC_MEM_CACHEPOLICAY(x) ((x) << 25)
> +/* 0 - lru.
> + * 1 - stream.
> + */
> +#define ATOMIC_MEM_ENGINESEL(x) ((x) << 30)
> +/* 0 - micro_engine.
> + */
> +
> #define PACKET3_DMA_DATA0x50
> /* 1. header
> * 2. CONTROL
> @@ -1472,8 +1486,33 @@
> amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle
>
> /* verify if SDMA test result meets with expected */
> i = 0;
> - while(i < sdma_write_length) {
> - CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf);
> + if (!secure) {
> + while(i < sdma_write_length) {
> + CU_ASSERT_EQUAL(bo_cpu[i++],
> 0xdeadbeaf);
> + }
> + } else if (ip_type == AMDGPU_HW_IP_GFX) {
> + memset((void*)pm4, 0, pm4_dw *
> sizeof(uint32_t));
> + pm4[i++] = PACKET3(PACKET3_ATOMIC_MEM, 7);
> + /* atomic opcode for 32b w/ RTN and
> ATOMIC_SWAPCMP_RTN
> + * command, 1-loop_until_compare_satisfied.
> + * single_pass_atomic, 0-lru
> + * engine_sel, 0-micro_engine
> + */
> + pm4[i++] = (TC_OP_ATOMIC_CMPSWAP_RTN_32 |
> + ATOMIC_MEM_COMMAND(1) |
> +
> ATOMIC_MEM_CACHEPOLICAY(0) |
> +
> ATOMIC_MEM_ENGINESEL(0));
> + pm4[i++] = 0xfffc & bo_mc;
> + pm4[i++] = (0x & bo_mc) >> 32;
> + pm4[i++] = 0x12345678;
> + pm4[i++] = 0x0;
> + pm4[i++] = 0xdeadbeaf;
> + pm4[i++] = 0x0;
> + pm4[i++] = 0x100;
> + amdgpu_test_exec_cs_helper_raw(device,
> context_handle,
> + ip_type, ring_id, i,
> pm4,
> + 1, resources, ib_info,
> + ibs_request, true);
> }
>
> r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc,
> --
> 2.7.4
>
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Re: [PATCH 11/12] tests/amdgpu: add atomic dma command to verify the secure buffer
On Fri, Nov 15, 2019 at 11:34:54AM +0800, Liu, Aaron wrote:
> DMA's atomic behavir is unlike GFX,If the comparing data is not
> equal to destination data,
> For GFX, loop again till gfx timeout(system hang).
> For DMA, loop again till timer expired and then send interrupt.
> So testcase can't use interrupt mechanism.
> We take another way to verify. When the comparing data is not
> equal to destination data, overwrite the source data to the destination
> buffer. Otherwise, original destination data unchanged.
> So if the bo_cpu data is overwritten, the result is passed.
>
> Steps:
> 1. use linear write packet to write 0xdeadbeaf to secure buffer,
> 2. use atmoic packet and ATOMIC_CMPSWAP_RTN_32 opcode to compare
> the cmp_data(0xdeadbeaf) to the written data which has been encrypted.
>
> Signed-off-by: Aaron Liu
> ---
> tests/amdgpu/basic_tests.c | 55
> --
> 1 file changed, 53 insertions(+), 2 deletions(-)
>
> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
> index 907237e..5e687e3 100644
> --- a/tests/amdgpu/basic_tests.c
> +++ b/tests/amdgpu/basic_tests.c
> @@ -109,6 +109,20 @@ CU_TestInfo basic_tests[] = {
> #define SDMA_OPCODE_COPY 1
> # define SDMA_COPY_SUB_OPCODE_LINEAR0
>
> +#define SDMA_OPCODE_ATOMIC10
> +#define SDMA_ATOMIC_LOOP(x) ((x) << 0)
> +/* 0 - single_pass_atomic.
> + * 1 - loop_until_compare_satisfied.
> + */
> +#define SDMA_ATOMIC_TMZ(x)((x) << 2)
> + /* 0 - non-TMZ.
> + * 1 - TMZ.
> + */
> +#define SDMA_ATOMIC_OPCODE(x) ((x) << 9)
> + /* TC_OP_ATOMIC_CMPSWAP_RTN_32 0x0008
> + * same as Packet 3
> + */
> +
> #define GFX_COMPUTE_NOP 0x1000
> #define SDMA_NOP 0x0
>
> @@ -1408,6 +1422,7 @@
> amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle
> struct amdgpu_cs_request *ibs_request;
> uint64_t bo_mc;
> volatile uint32_t *bo_cpu;
> + uint32_t bo_cpu_origin;
> int i, j, r, loop, ring_id;
> uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
> amdgpu_va_handle va_handle;
> @@ -1460,8 +1475,9 @@
> amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle
>
> sdma_write_length);
> else
> pm4[i++] =
> SDMA_PACKET(SDMA_OPCODE_WRITE,
> -
> SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
> - pm4[i++] = 0x & bo_mc;
> +
> SDMA_WRITE_SUB_OPCODE_LINEAR,
> +secure ?
> SDMA_ATOMIC_TMZ(1) : 0);
> + pm4[i++] = 0xfffc & bo_mc;
> pm4[i++] = (0x & bo_mc) >> 32;
> if (family_id >= AMDGPU_FAMILY_AI)
> pm4[i++] = sdma_write_length - 1;
> @@ -1513,6 +1529,41 @@
> amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle
> ip_type, ring_id, i,
> pm4,
> 1, resources, ib_info,
> ibs_request, true);
> + } else if (ip_type == AMDGPU_HW_IP_DMA) {
> + /* restore the bo_cpu to compare */
> + bo_cpu_origin = bo_cpu[0];
> + memset((void*)pm4, 0, pm4_dw *
> sizeof(uint32_t));
> + /* atomic opcode for 32b w/ RTN and
> ATOMIC_SWAPCMP_RTN
> + * loop, 1-loop_until_compare_satisfied.
> + * single_pass_atomic, 0-lru
> + */
> + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_ATOMIC,
> +0,
> +
> SDMA_ATOMIC_LOOP(1) |
> +
> SDMA_ATOMIC_TMZ(1) |
> +
> SDMA_ATOMIC_OPCODE(TC_OP_ATOMIC_CMPSWAP_RTN_32));
> + pm4[i++] = 0xfffc & bo_mc;
> + pm4[i++] = (0x & bo_mc) >> 32;
> + pm4[i++] = 0x12345678;
> + pm4[i++] = 0x0;
> + pm4[i++] = 0xdeadbeaf;
> + pm4[i++] = 0x0;
> +
Re: [PATCH 08/12] tests/amdgpu: expand secure param for exec_cs_helper
On Fri, Nov 15, 2019 at 11:34:51AM +0800, Liu, Aaron wrote:
> This patch expands secure param for amdgpu_test_exec_cs_helper_raw.
> The flag is transfered to kernel with cs.
>
> Signed-off-by: Aaron Liu
Acked-by: Huang Rui
> ---
> tests/amdgpu/basic_tests.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
> index 5154812..956be93 100644
> --- a/tests/amdgpu/basic_tests.c
> +++ b/tests/amdgpu/basic_tests.c
> @@ -1290,7 +1290,8 @@ amdgpu_test_exec_cs_helper_raw(amdgpu_device_handle
> device_handle,
> uint32_t *pm4_src, int res_cnt,
> amdgpu_bo_handle *resources,
> struct amdgpu_cs_ib_info *ib_info,
> -struct amdgpu_cs_request *ibs_request)
> +struct amdgpu_cs_request *ibs_request,
> +bool secure)
> {
> int r;
> uint32_t expired;
> @@ -1324,6 +1325,7 @@ amdgpu_test_exec_cs_helper_raw(amdgpu_device_handle
> device_handle,
> ib_info->size = pm4_dw;
>
> ibs_request->ip_type = ip_type;
> + ibs_request->flags = secure ? 1 : 0;
> ibs_request->ring = instance;
> ibs_request->number_of_ibs = 1;
> ibs_request->ibs = ib_info;
> @@ -1374,7 +1376,7 @@ amdgpu_test_exec_cs_helper(amdgpu_context_handle
> context_handle,
> amdgpu_test_exec_cs_helper_raw(device_handle, context_handle,
> ip_type, instance, pm4_dw, pm4_src,
> res_cnt, resources, ib_info,
> -ibs_request);
> +ibs_request, false);
> }
>
> void
> @@ -1466,7 +1468,7 @@
> amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle
> amdgpu_test_exec_cs_helper_raw(device, context_handle,
> ip_type, ring_id, i, pm4,
> 1, resources, ib_info,
> -ibs_request);
> +ibs_request, secure);
>
> /* verify if SDMA test result meets with expected */
> i = 0;
> --
> 2.7.4
>
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Re: [PATCH 08/12] tests/amdgpu: expand secure param for exec_cs_helper
On Fri, Nov 15, 2019 at 11:34:51AM +0800, Liu, Aaron wrote:
> This patch expands secure param for amdgpu_test_exec_cs_helper_raw.
> The flag is transfered to kernel with cs.
>
> Signed-off-by: Aaron Liu
Acked-by: Huang Rui
> ---
> tests/amdgpu/basic_tests.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
> index 5154812..956be93 100644
> --- a/tests/amdgpu/basic_tests.c
> +++ b/tests/amdgpu/basic_tests.c
> @@ -1290,7 +1290,8 @@ amdgpu_test_exec_cs_helper_raw(amdgpu_device_handle
> device_handle,
> uint32_t *pm4_src, int res_cnt,
> amdgpu_bo_handle *resources,
> struct amdgpu_cs_ib_info *ib_info,
> -struct amdgpu_cs_request *ibs_request)
> +struct amdgpu_cs_request *ibs_request,
> +bool secure)
> {
> int r;
> uint32_t expired;
> @@ -1324,6 +1325,7 @@ amdgpu_test_exec_cs_helper_raw(amdgpu_device_handle
> device_handle,
> ib_info->size = pm4_dw;
>
> ibs_request->ip_type = ip_type;
> + ibs_request->flags = secure ? 1 : 0;
> ibs_request->ring = instance;
> ibs_request->number_of_ibs = 1;
> ibs_request->ibs = ib_info;
> @@ -1374,7 +1376,7 @@ amdgpu_test_exec_cs_helper(amdgpu_context_handle
> context_handle,
> amdgpu_test_exec_cs_helper_raw(device_handle, context_handle,
> ip_type, instance, pm4_dw, pm4_src,
> res_cnt, resources, ib_info,
> -ibs_request);
> +ibs_request, false);
> }
>
> void
> @@ -1466,7 +1468,7 @@
> amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle
> amdgpu_test_exec_cs_helper_raw(device, context_handle,
> ip_type, ring_id, i, pm4,
> 1, resources, ib_info,
> -ibs_request);
> +ibs_request, secure);
>
> /* verify if SDMA test result meets with expected */
> i = 0;
> --
> 2.7.4
>
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Re: [PATCH 09/12] tests/amdgpu: add atomic_mem cp_packet to verify the secure buffer
On Fri, Nov 15, 2019 at 11:34:52AM +0800, Liu, Aaron wrote:
> Secure buffer is only able to be read with trusted ip block.
> So we need use GFX ip to read it back instead of CPU.
> Steps:
> 1. use write_data packet to write 0xdeadbeaf to secure buffer,
> 2. use atmoic_mem packet and ATOMIC_CMPSWAP_RTN_32 opcode to compare
> the cmp_data(0xdeadbeaf) to the written data which has been encrypted.
> If the result is equal, then overwrite the src_data(0x12345678) to the
> secure buffer and return directly. Otherwise loop again until gfx timeout
> and the secure buffer data unchanged.
>
> Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
> ---
> tests/amdgpu/basic_tests.c | 43 +--
> 1 file changed, 41 insertions(+), 2 deletions(-)
>
> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
> index 956be93..907237e 100644
> --- a/tests/amdgpu/basic_tests.c
> +++ b/tests/amdgpu/basic_tests.c
> @@ -160,6 +160,20 @@ CU_TestInfo basic_tests[] = {
>* 2 - ce
>*/
>
> +#define PACKET3_ATOMIC_MEM 0x1E
> +#define TC_OP_ATOMIC_CMPSWAP_RTN_32 0x0008
> +#define ATOMIC_MEM_COMMAND(x) ((x) << 8)
> +/* 0 - single_pass_atomic.
> + * 1 - loop_until_compare_satisfied.
> + */
> +#define ATOMIC_MEM_CACHEPOLICAY(x) ((x) << 25)
> +/* 0 - lru.
> + * 1 - stream.
> + */
> +#define ATOMIC_MEM_ENGINESEL(x) ((x) << 30)
> +/* 0 - micro_engine.
> + */
> +
> #define PACKET3_DMA_DATA0x50
> /* 1. header
> * 2. CONTROL
> @@ -1472,8 +1486,33 @@
> amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle
>
> /* verify if SDMA test result meets with expected */
> i = 0;
> - while(i < sdma_write_length) {
> - CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf);
> + if (!secure) {
> + while(i < sdma_write_length) {
> + CU_ASSERT_EQUAL(bo_cpu[i++],
> 0xdeadbeaf);
> + }
> + } else if (ip_type == AMDGPU_HW_IP_GFX) {
> + memset((void*)pm4, 0, pm4_dw *
> sizeof(uint32_t));
> + pm4[i++] = PACKET3(PACKET3_ATOMIC_MEM, 7);
> + /* atomic opcode for 32b w/ RTN and
> ATOMIC_SWAPCMP_RTN
> + * command, 1-loop_until_compare_satisfied.
> + * single_pass_atomic, 0-lru
> + * engine_sel, 0-micro_engine
> + */
> + pm4[i++] = (TC_OP_ATOMIC_CMPSWAP_RTN_32 |
> + ATOMIC_MEM_COMMAND(1) |
> +
> ATOMIC_MEM_CACHEPOLICAY(0) |
> +
> ATOMIC_MEM_ENGINESEL(0));
> + pm4[i++] = 0xfffc & bo_mc;
> + pm4[i++] = (0x & bo_mc) >> 32;
> + pm4[i++] = 0x12345678;
> + pm4[i++] = 0x0;
> + pm4[i++] = 0xdeadbeaf;
> + pm4[i++] = 0x0;
> + pm4[i++] = 0x100;
> + amdgpu_test_exec_cs_helper_raw(device,
> context_handle,
> + ip_type, ring_id, i,
> pm4,
> + 1, resources, ib_info,
> + ibs_request, true);
> }
>
> r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc,
> --
> 2.7.4
>
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Re: [PATCH 07/12] amdgpu: using IB flags for TMZ or non-TMZ
On Fri, Nov 15, 2019 at 11:34:50AM +0800, Liu, Aaron wrote:
> In kernel, cs->in.flags is used for TMZ. Hence libdrm should transfer
> the flag to kernel.
>
> Signed-off-by: Aaron Liu
> ---
> amdgpu/amdgpu.h| 4 +++-
> amdgpu/amdgpu_cs.c | 4
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index f45f9f7..aee3f3d
> 100644
> --- a/amdgpu/amdgpu.h
> +++ b/amdgpu/amdgpu.h
> @@ -342,7 +342,9 @@ struct amdgpu_cs_fence_info {
> * \sa amdgpu_cs_submit()
> */
> struct amdgpu_cs_request {
> - /** Specify flags with additional information */
> + /** Specify flags with additional information
> + * 0-normal, 1-tmz
> + */
> uint64_t flags;
>
> /** Specify HW IP block type to which to send the IB. */ diff --git
> a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 437c4a4..6f70771
> 100644
> --- a/amdgpu/amdgpu_cs.c
> +++ b/amdgpu/amdgpu_cs.c
> @@ -254,6 +254,10 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle
> context,
> memset(&cs, 0, sizeof(cs));
> cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
> cs.in.ctx_id = context->id;
> + /* in kernel, _pad is used as flags
> + * #define AMDGPU_CS_FLAGS_SECURE (1 << 0)
> + */
> + cs.in._pad = (uint32_t)ibs_request->flags;
_pad is not good here. Because it's used to pass the flags to input param.
It's better to rename "_pad" in drm_amdgpu_cs_in as "flags" here.
Thanks,
Ray
> if (ibs_request->resources)
> cs.in.bo_list_handle = ibs_request->resources->handle;
> cs.in.num_chunks = ibs_request->number_of_ibs;
> --
> 2.7.4
>
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RE: [PATCH] drm/amdgpu: allow direct upload save restore list for raven2
> -Original Message-
> From: Zhu, Changfeng
> Sent: Friday, November 08, 2019 9:55 AM
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Huang, Ray
> Cc: Zhu, Changfeng
> Subject: [PATCH] drm/amdgpu: allow direct upload save restore list for
> raven2
>
> From: changzhu
>
> It will cause modprobe atombios stuck problem in raven2 if it doesn't allow
> direct upload save restore list from gfx driver.
> So it needs to allow direct upload save restore list for raven2 temporarily.
>
> Change-Id: I1fece1b9c61f7a13eec948f34eb60a9120046bc2
> Signed-off-by: changzhu
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 4ed31e9a398c..dde9713c1d67 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2729,7 +2729,9 @@ static void gfx_v9_0_init_pg(struct amdgpu_device
> *adev)
>* And it's needed by gfxoff feature.
>*/
> if (adev->gfx.rlc.is_rlc_v2_1) {
> - if (adev->asic_type == CHIP_VEGA12)
> + if (adev->asic_type == CHIP_VEGA12 ||
> + (adev->asic_type == CHIP_RAVEN &&
> + adev->rev_id >= 8))
> gfx_v9_1_init_rlc_save_restore_list(adev);
> gfx_v9_0_enable_save_restore_machine(adev);
> }
> --
> 2.17.1
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Re: [PATCH] drm/amd/powerplay: Disable gfx CGPG when suspend smu
On Mon, Oct 28, 2019 at 10:34:54AM +0800, Gong, Curry wrote:
> Hi Ray:
>
> Because I found that enable CGPG for all APU in smu_resume at 0d2e9b10428a6
I see, thanks.
Patch is Reviewed-by: Huang Rui
>
> commit 0d2e9b10428a6c261c99f2d982be7745f35eef97
> Author: Prike Liang
> Date: Tue Oct 15 17:11:49 2019 +0800
>
> drm/amdgpu: fix S3 failed as RLC safe mode entry stucked in polloing gfx
> acq
>
> Fix gfx cgpg setting sequence for RLC deadlock at safe mode entry in
> polling gfx response.
> The patch can fix VCN IB test failed and DAL get dispaly count failed
> issue.
>
> Signed-off-by: Prike Liang
> Reviewed-by: Huang Rui
>
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index acec69b74734..e2a03f411d6b 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1350,6 +1351,9 @@ static int smu_resume(void *handle)
> if (ret)
> goto failed;
>
> + if (smu->is_apu)
> + smu_set_gfx_cgpg(&adev->smu, true);
> +
> mutex_unlock(&smu->mutex);
>
> pr_info("SMU is resumed successfully!\n");
>
> -Original Message-
> From: Huang, Ray
> Sent: Friday, October 25, 2019 9:26 PM
> To: Gong, Curry ; amd-gfx@lists.freedesktop.org
> Cc: Gong, Curry
> Subject: RE: [PATCH] drm/amd/powerplay: Disable gfx CGPG when suspend smu
>
> Why do you disable CGPG for all APU?
>
> Thanks,
> Ray
>
> -Original Message-
> From: amd-gfx On Behalf Of chen gong
> Sent: Friday, October 25, 2019 7:07 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Gong, Curry
> Subject: [PATCH] drm/amd/powerplay: Disable gfx CGPG when suspend smu
>
> if no disable gfx CGPG when suspend smu, enabling gfx CGPG will fail when
> resume smu.
>
> Platform: Renoir
> dmesg log information:
>
> [ 151.844110 ] amdgpu: [powerplay] SMU is resuming...
> [ 151.844116 ] amdgpu: [powerplay] dpm has been disabled [ 151.844604 ]
> amdgpu: [powerplay] Failed to send message 0x2f,response 0xfffb param 0x1
> [ 151.844605 ] amdgpu: [powerplay] SMU is resumed successfully!
>
> Signed-off-by: chen gong
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 26923aa..4e468b0 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1351,6 +1351,8 @@ static int smu_suspend(void *handle)
> if (adev->asic_type >= CHIP_NAVI10 &&
> adev->gfx.rlc.funcs->stop)
> adev->gfx.rlc.funcs->stop(adev);
> + if (smu->is_apu)
> + smu_set_gfx_cgpg(&adev->smu, false);
>
> return 0;
> }
> --
> 2.7.4
>
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RE: [PATCH] drm/amd/powerplay: Disable gfx CGPG when suspend smu
Why do you disable CGPG for all APU? Thanks, Ray -Original Message- From: amd-gfx On Behalf Of chen gong Sent: Friday, October 25, 2019 7:07 PM To: amd-gfx@lists.freedesktop.org Cc: Gong, Curry Subject: [PATCH] drm/amd/powerplay: Disable gfx CGPG when suspend smu if no disable gfx CGPG when suspend smu, enabling gfx CGPG will fail when resume smu. Platform: Renoir dmesg log information: [ 151.844110 ] amdgpu: [powerplay] SMU is resuming... [ 151.844116 ] amdgpu: [powerplay] dpm has been disabled [ 151.844604 ] amdgpu: [powerplay] Failed to send message 0x2f,response 0xfffb param 0x1 [ 151.844605 ] amdgpu: [powerplay] SMU is resumed successfully! Signed-off-by: chen gong --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 26923aa..4e468b0 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -1351,6 +1351,8 @@ static int smu_suspend(void *handle) if (adev->asic_type >= CHIP_NAVI10 && adev->gfx.rlc.funcs->stop) adev->gfx.rlc.funcs->stop(adev); + if (smu->is_apu) + smu_set_gfx_cgpg(&adev->smu, false); return 0; } -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: GFX9, GFX10: GRBM requires 1-cycle delay
On Thu, Oct 24, 2019 at 09:16:55PM +, Tuikov, Luben wrote:
> The GRBM interface is now capable of bursting 1-cycle op per register,
> a WRITE followed by another WRITE, or a WRITE followed by a READ--much
> faster than previous muti-cycle per completed-transaction interface.
> This causes a problem, whereby status registers requiring a read/write
> by hardware, have a 1-cycle delay, due to the register update having
> to go through GRBM interface.
>
> This patch adds this delay.
>
> A one cycle read op is added after updating the invalidate request and
> before reading the invalidate-ACK status.
>
> See also commit
> 534991731cb5fa94b5519957646cf849ca10d17d.
>
> Signed-off-by: Luben Tuikov
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 9 +
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
> 5 files changed, 22 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index ac43b1af69e3..0042868dbd53 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -5129,7 +5129,7 @@ static const struct amdgpu_ring_funcs
> gfx_v10_0_ring_funcs_gfx = {
> 5 + /* COND_EXEC */
> 7 + /* PIPELINE_SYNC */
> SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
> - SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
> + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 * 2 +
> 2 + /* VM_FLUSH */
> 8 + /* FENCE for VM_FLUSH */
> 20 + /* GDS switch */
> @@ -5182,7 +5182,7 @@ static const struct amdgpu_ring_funcs
> gfx_v10_0_ring_funcs_compute = {
> 5 + /* hdp invalidate */
> 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
> SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
> - SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
> + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 * 2 +
> 2 + /* gfx_v10_0_ring_emit_vm_flush */
> 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm
> fence */
> .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 9fe95e7693d5..9a7a717208de 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -6218,7 +6218,7 @@ static const struct amdgpu_ring_funcs
> gfx_v9_0_ring_funcs_gfx = {
> 5 + /* COND_EXEC */
> 7 + /* PIPELINE_SYNC */
> SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
> - SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
> + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 * 2 +
> 2 + /* VM_FLUSH */
> 8 + /* FENCE for VM_FLUSH */
> 20 + /* GDS switch */
> @@ -6271,7 +6271,7 @@ static const struct amdgpu_ring_funcs
> gfx_v9_0_ring_funcs_compute = {
> 5 + /* hdp invalidate */
> 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
> SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
> - SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
> + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 * 2 +
> 2 + /* gfx_v9_0_ring_emit_vm_flush */
> 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm
> fence */
> .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index 6e1b25bd1fe7..100d526e9a42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -346,6 +346,15 @@ static uint64_t
> gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>
> amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
>
> + /* Insert a dummy read to delay one cycle before the ACK
> + * inquiry.
> + */
> + if (ring->funcs->type == AMDGPU_RING_TYPE_SDMA ||
> + ring->funcs->type == AMDGPU_RING_TYPE_GFX ||
> + ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
> + amdgpu_ring_emit_reg_wait(ring,
> + hub->vm_inv_eng0_req + eng, 0, 0);
> +
> /* wait for the invalidate to complete */
> amdgpu_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng,
> 1 << vmid, 1 << vmid);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 9f2a893871ec..8f3097e45299 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -495,6 +495,14 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct
> amdgpu_ring *ring,
> amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
> upper_32_bits(pd_addr));
>
RE: [PATCH] drm/ttm: use the parent resv for ghost objects v3
Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Christian
König
Sent: Thursday, October 24, 2019 7:17 PM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Zhou,
David(ChunMing)
Subject: [PATCH] drm/ttm: use the parent resv for ghost objects v3
This way the TTM is destroyed with the correct dma_resv object locked and we
can even pipeline imported BO evictions.
v2: Limit this to only cases when the parent object uses a separate
reservation object as well. This fixes another OOM problem.
v3: fix init and try_lock on the wrong object
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 73a1b0186029..f7b57ca1a95b 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -516,9 +516,11 @@ static int ttm_buffer_object_transfer(struct
ttm_buffer_object *bo,
kref_init(&fbo->base.kref);
fbo->base.destroy = &ttm_transfered_destroy;
fbo->base.acc_size = 0;
- fbo->base.base.resv = &fbo->base.base._resv;
- dma_resv_init(fbo->base.base.resv);
- ret = dma_resv_trylock(fbo->base.base.resv);
+ if (bo->base.resv == &bo->base._resv)
+ fbo->base.base.resv = &fbo->base.base._resv;
+
+ dma_resv_init(&fbo->base.base._resv);
+ ret = dma_resv_trylock(&fbo->base.base._resv);
WARN_ON(!ret);
*new_obj = &fbo->base;
@@ -715,7 +717,7 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
if (ret)
return ret;
- dma_resv_add_excl_fence(ghost_obj->base.resv, fence);
+ dma_resv_add_excl_fence(&ghost_obj->base._resv, fence);
/**
* If we're not moving to fixed memory, the TTM object @@
-728,7 +730,7 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
else
bo->ttm = NULL;
- ttm_bo_unreserve(ghost_obj);
+ dma_resv_unlock(&ghost_obj->base._resv);
ttm_bo_put(ghost_obj);
}
@@ -771,7 +773,7 @@ int ttm_bo_pipeline_move(struct ttm_buffer_object *bo,
if (ret)
return ret;
- dma_resv_add_excl_fence(ghost_obj->base.resv, fence);
+ dma_resv_add_excl_fence(&ghost_obj->base._resv, fence);
/**
* If we're not moving to fixed memory, the TTM object @@
-784,7 +786,7 @@ int ttm_bo_pipeline_move(struct ttm_buffer_object *bo,
else
bo->ttm = NULL;
- ttm_bo_unreserve(ghost_obj);
+ dma_resv_unlock(&ghost_obj->base._resv);
ttm_bo_put(ghost_obj);
} else if (from->flags & TTM_MEMTYPE_FLAG_FIXED) { @@ -840,7 +842,7 @@
int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo)
if (ret)
return ret;
- ret = dma_resv_copy_fences(ghost->base.resv, bo->base.resv);
+ ret = dma_resv_copy_fences(&ghost->base._resv, bo->base.resv);
/* Last resort, wait for the BO to be idle when we are OOM */
if (ret)
ttm_bo_wait(bo, false, false);
@@ -849,7 +851,7 @@ int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo)
bo->mem.mem_type = TTM_PL_SYSTEM;
bo->ttm = NULL;
- ttm_bo_unreserve(ghost);
+ dma_resv_unlock(&ghost->base._resv);
ttm_bo_put(ghost);
return 0;
--
2.17.1
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RE: [PATCH 1/2] drm/amdgpu: add GFX_PIPELINE capacity check for updating gfx cgpg
Series are Reviewed-by: Huang Rui
-Original Message-
From: Liang, Prike
Sent: Tuesday, October 15, 2019 5:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan ; Feng, Kenneth ;
Huang, Ray ; Liang, Prike
Subject: [PATCH 1/2] drm/amdgpu: add GFX_PIPELINE capacity check for updating
gfx cgpg
Before disable gfx pipeline power gating need check the flag
AMD_PG_SUPPORT_GFX_PIPELINE.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index b577b69..de8f9d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4296,7 +4296,8 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct
amdgpu_device *adev,
gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
} else {
gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
- gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
+ if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
+ gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
}
amdgpu_gfx_rlc_exit_safe_mode(adev);
--
2.7.4
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RE: [PATCH 1/2] drm/amdgpu: improve MSI-X handling
Series are Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, October 3, 2019 10:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/2] drm/amdgpu: improve MSI-X handling
Check the number of supported vectors and fall back to MSI if we return or
error or 0 MSI-X vectors.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 50771b2757dc..98aa28edba6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -245,11 +245,19 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
adev->irq.msi_enabled = false;
if (amdgpu_msi_ok(adev)) {
- int nvec = pci_alloc_irq_vectors(adev->pdev, 1,
pci_msix_vec_count(adev->pdev),
- PCI_IRQ_MSI | PCI_IRQ_MSIX);
+ unsigned int flags;
+ int nvec = pci_msix_vec_count(adev->pdev);
+
+ if (nvec <= 0) {
+ flags = PCI_IRQ_MSI;
+ nvec = 1;
+ } else {
+ flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
+ }
+ nvec = pci_alloc_irq_vectors(adev->pdev, 1, nvec, flags);
if (nvec > 0) {
adev->irq.msi_enabled = true;
- dev_dbg(adev->dev, "amdgpu: using MSI.\n");
+ dev_dbg(adev->dev, "amdgpu: using MSI/MSI-X.\n");
}
}
--
2.20.1
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RE: [PATCH 2/2] drm/radeon: finally fix the racy VMA setup
Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Christian
König
Sent: Friday, September 27, 2019 8:34 AM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Subject: [PATCH 2/2] drm/radeon: finally fix the racy VMA setup
Finally clean up the VMA setup for radeon now that TTM exports the necessary
functions.
Not functional change, but only compile tested.
Signed-off-by: Christian König
---
drivers/gpu/drm/radeon/radeon_ttm.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c
b/drivers/gpu/drm/radeon/radeon_ttm.c
index a05e10724d46..f3ef304a67ee 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -880,9 +880,6 @@ void radeon_ttm_set_active_vram_size(struct radeon_device
*rdev, u64 size)
man->size = size >> PAGE_SHIFT;
}
-static struct vm_operations_struct radeon_ttm_vm_ops; -static const struct
vm_operations_struct *ttm_vm_ops = NULL;
-
static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf) {
struct ttm_buffer_object *bo;
@@ -890,34 +887,36 @@ static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf)
vm_fault_t ret;
bo = (struct ttm_buffer_object *)vmf->vma->vm_private_data;
- if (bo == NULL) {
+ if (bo == NULL)
return VM_FAULT_NOPAGE;
- }
+
rdev = radeon_get_rdev(bo->bdev);
down_read(&rdev->pm.mclk_lock);
- ret = ttm_vm_ops->fault(vmf);
+ ret = ttm_bo_vm_fault(vmf);
up_read(&rdev->pm.mclk_lock);
return ret;
}
+static struct vm_operations_struct radeon_ttm_vm_ops = {
+ .fault = radeon_ttm_fault,
+ .open = ttm_bo_vm_open,
+ .close = ttm_bo_vm_close,
+ .access = ttm_bo_vm_access
+};
+
int radeon_mmap(struct file *filp, struct vm_area_struct *vma) {
int r;
struct drm_file *file_priv = filp->private_data;
struct radeon_device *rdev = file_priv->minor->dev->dev_private;
- if (rdev == NULL) {
+ if (rdev == NULL)
return -EINVAL;
- }
+
r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
- if (unlikely(r != 0)) {
+ if (unlikely(r != 0))
return r;
- }
- if (unlikely(ttm_vm_ops == NULL)) {
- ttm_vm_ops = vma->vm_ops;
- radeon_ttm_vm_ops = *ttm_vm_ops;
- radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
- }
+
vma->vm_ops = &radeon_ttm_vm_ops;
return 0;
}
--
2.14.1
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RE: [PATCH] drm/amdgpu: don't increment vram lost if we are in hibernation
Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Tuesday, October 1, 2019 5:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: don't increment vram lost if we are in hibernation
We reset the GPU as part of our hibernation sequence so we need to make sure we
don't mark vram as lost in that case.
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111879
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c| 6 --
drivers/gpu/drm/amd/amdgpu/soc15.c | 6 --
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index b3e7756fcc4b..17dc054a4b6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -319,10 +319,12 @@ static int nv_asic_reset(struct amdgpu_device *adev)
struct smu_context *smu = &adev->smu;
if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
- amdgpu_inc_vram_lost(adev);
+ if (!adev->in_suspend)
+ amdgpu_inc_vram_lost(adev);
ret = smu_baco_reset(smu);
} else {
- amdgpu_inc_vram_lost(adev);
+ if (!adev->in_suspend)
+ amdgpu_inc_vram_lost(adev);
ret = nv_asic_mode1_reset(adev);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index b5240b5dbf7b..88a49a68c67f 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -564,12 +564,14 @@ static int soc15_asic_reset(struct amdgpu_device *adev) {
switch (soc15_asic_reset_method(adev)) {
case AMD_RESET_METHOD_BACO:
- amdgpu_inc_vram_lost(adev);
+ if (!adev->in_suspend)
+ amdgpu_inc_vram_lost(adev);
return soc15_asic_baco_reset(adev);
case AMD_RESET_METHOD_MODE2:
return soc15_mode2_reset(adev);
default:
- amdgpu_inc_vram_lost(adev);
+ if (!adev->in_suspend)
+ amdgpu_inc_vram_lost(adev);
return soc15_asic_mode1_reset(adev);
}
}
--
2.20.1
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RE: [PATCH 1/2] drm/ttm: also export ttm_bo_vm_fault
Ahh. 😊
Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Christian
König
Sent: Wednesday, October 2, 2019 4:38 AM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/ttm: also export ttm_bo_vm_fault
Just a gentle ping on this. Everybody on XDC, or can we get this comitted?
Am 27.09.19 um 14:34 schrieb Christian König:
> That is needed by at least a cleanup in radeon.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/ttm/ttm_bo_vm.c | 3 ++-
> include/drm/ttm/ttm_bo_api.h| 2 ++
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c
> b/drivers/gpu/drm/ttm/ttm_bo_vm.c index cb3120cd5aa1..525046bbcb6b
> 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
> @@ -316,7 +316,7 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf,
> }
> EXPORT_SYMBOL(ttm_bo_vm_fault_reserved);
>
> -static vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
> +vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
> {
> struct vm_area_struct *vma = vmf->vma;
> pgprot_t prot;
> @@ -336,6 +336,7 @@ static vm_fault_t ttm_bo_vm_fault(struct vm_fault
> *vmf)
>
> return ret;
> }
> +EXPORT_SYMBOL(ttm_bo_vm_fault);
>
> void ttm_bo_vm_open(struct vm_area_struct *vma)
> {
> diff --git a/include/drm/ttm/ttm_bo_api.h
> b/include/drm/ttm/ttm_bo_api.h index 851260cbbb2f..dad41cf5cd64 100644
> --- a/include/drm/ttm/ttm_bo_api.h
> +++ b/include/drm/ttm/ttm_bo_api.h
> @@ -796,6 +796,8 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf,
> pgprot_t prot,
> pgoff_t num_prefault);
>
> +vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf);
> +
> void ttm_bo_vm_open(struct vm_area_struct *vma);
>
> void ttm_bo_vm_close(struct vm_area_struct *vma);
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[PATCH v4 10/11] drm/amdgpu: job is secure iff CS is secure (v5)
Mark a job as secure, if and only if the command
submission flag has the secure flag set.
v2: fix the null job pointer while in vmid 0
submission.
v3: Context --> Command submission.
v4: filling cs parser with cs->in.flags
v5: move the job secure flag setting out of amdgpu_cs_submit()
Signed-off-by: Huang Rui
Co-developed-by: Luben Tuikov
Signed-off-by: Luben Tuikov
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 2 ++
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 49b767b..c18a153 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -231,6 +231,8 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p, union drm_amdgpu_cs
if (ret)
goto free_all_kdata;
+ p->job->secure = cs->in.flags & AMDGPU_CS_FLAGS_SECURE;
+
if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
ret = -ECANCELED;
goto free_all_kdata;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 9a6dbf3..6e0f97a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -213,7 +213,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
if (job && ring->funcs->emit_cntxcntl) {
status |= job->preamble_status;
status |= job->preemption_status;
- amdgpu_ring_emit_cntxcntl(ring, status, false);
+ amdgpu_ring_emit_cntxcntl(ring, status, job->secure);
}
for (i = 0; i < num_ibs; ++i) {
@@ -232,7 +232,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
}
if (ring->funcs->emit_tmz)
- amdgpu_ring_emit_tmz(ring, false, false);
+ amdgpu_ring_emit_tmz(ring, false, job ? job->secure : false);
#ifdef CONFIG_X86_64
if (!(adev->flags & AMD_IS_APU))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index dc7ee93..aa0e375 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -63,6 +63,8 @@ struct amdgpu_job {
uint64_tuf_addr;
uint64_tuf_sequence;
+ /* the job is due to a secure command submission */
+ boolsecure;
};
int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
--
2.7.4
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RE: [PATCH] Revert "drm/amdgpu: disable stutter mode for renoir"
> -Original Message- > From: Liu, Aaron > Sent: Friday, September 27, 2019 11:23 AM > To: amd-gfx@lists.freedesktop.org > Cc: Huang, Ray ; Liu, Aaron > Subject: [PATCH] Revert "drm/amdgpu: disable stutter mode for renoir" > > This reverts commit c512e6fdfd2da917b5b6792902e7224f58a77f94. > > Since SBIOS WCD9925N, NMI printing disappeared. Hence enable stutter > mode. > > Signed-off-by: Aaron Liu Try to do more tests with this SBIOS and make sure the result. After that, patch is Reviewed-by: Huang Rui > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index bdab3f7..9d8d7e8 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -2466,8 +2466,6 @@ static int amdgpu_dm_initialize_drm_device(struct > amdgpu_device *adev) > > if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != > CHIP_STONEY) > dm->dc->debug.disable_stutter = > amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; > - if (adev->asic_type == CHIP_RENOIR) > - dm->dc->debug.disable_stutter = true; > > return 0; > fail: > -- > 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: Add NAVI12 support from kfd side
> -Original Message-
> From: amd-gfx On Behalf Of Liu,
> Shaoyun
> Sent: Wednesday, September 25, 2019 6:14 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Shaoyun
> Subject: [PATCH] drm/amdgpu: Add NAVI12 support from kfd side
>
> Add device info for both navi12 PF and VF
>
> Change-Id: Ifb4035e65c12d153fc30e593fe109f9c7e0541f4
> Signed-off-by: shaoyunl
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> index f329b82..edfbae5c 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> @@ -387,6 +387,24 @@ static const struct kfd_device_info
> navi10_device_info = {
> .num_sdma_queues_per_engine = 8,
> };
>
> +static const struct kfd_device_info navi12_device_info = {
> + .asic_family = CHIP_NAVI12,
> + .asic_name = "navi12",
> + .max_pasid_bits = 16,
> + .max_no_of_hqd = 24,
> + .doorbell_size = 8,
> + .ih_ring_entry_size = 8 * sizeof(uint32_t),
> + .event_interrupt_class = &event_interrupt_class_v9,
> + .num_of_watch_points = 4,
> + .mqd_size_aligned = MQD_SIZE_ALIGNED,
> + .needs_iommu_device = false,
> + .supports_cwsr = true,
> + .needs_pci_atomics = false,
> + .num_sdma_engines = 2,
> + .num_xgmi_sdma_engines = 0,
> + .num_sdma_queues_per_engine = 8,
> +};
> +
> static const struct kfd_device_info navi14_device_info = {
> .asic_family = CHIP_NAVI14,
> .asic_name = "navi14",
> @@ -425,6 +443,7 @@ static const struct kfd_device_info
> *kfd_supported_devices[][2] = {
> [CHIP_RENOIR] = {&renoir_device_info, NULL},
> [CHIP_ARCTURUS] = {&arcturus_device_info,
> &arcturus_device_info},
> [CHIP_NAVI10] = {&navi10_device_info, NULL},
> + [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info},
> [CHIP_NAVI14] = {&navi14_device_info, NULL}, };
>
> --
> 2.7.4
>
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RE: [PATCH v3 10/11] drm/amdgpu: job is secure iff CS is secure (v4)
> -Original Message-
> From: Koenig, Christian
> Sent: Wednesday, September 25, 2019 10:47 PM
> To: Huang, Ray ; amd-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; Deucher, Alexander
>
> Cc: Tuikov, Luben ; Liu, Aaron
>
> Subject: Re: [PATCH v3 10/11] drm/amdgpu: job is secure iff CS is secure (v4)
>
> Am 25.09.19 um 16:38 schrieb Huang, Ray:
> > Mark a job as secure, if and only if the command submission flag has
> > the secure flag set.
> >
> > v2: fix the null job pointer while in vmid 0 submission.
> > v3: Context --> Command submission.
> > v4: filling cs parser with cs->in.flags
> >
> > Signed-off-by: Huang Rui
> > Co-developed-by: Luben Tuikov
> > Signed-off-by: Luben Tuikov
> > Reviewed-by: Alex Deucher
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 11 ++-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 ++--
> > drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 2 ++
> > 4 files changed, 17 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 697e8e5..fd60695 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -485,6 +485,9 @@ struct amdgpu_cs_parser {
> > uint64_tbytes_moved;
> > uint64_tbytes_moved_vis;
> >
> > + /* secure cs */
> > + boolis_secure;
> > +
> > /* user fence */
> > struct amdgpu_bo_list_entry uf_entry;
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> > index 51f3db0..9038dc1 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> > @@ -133,6 +133,14 @@ static int amdgpu_cs_parser_init(struct
> amdgpu_cs_parser *p, union drm_amdgpu_cs
> > goto free_chunk;
> > }
> >
> > + /**
> > +* The command submission (cs) is a union, so an assignment to
> > +* 'out' is destructive to the cs (at least the first 8
> > +* bytes). For this reason, inquire about the flags before the
> > +* assignment to 'out'.
> > +*/
> > + p->is_secure = cs->in.flags & AMDGPU_CS_FLAGS_SECURE;
> > +
> > /* get chunks */
> > chunk_array_user = u64_to_user_ptr(cs->in.chunks);
> > if (copy_from_user(chunk_array, chunk_array_user, @@ -1252,8
> > +1260,9 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
> > p->ctx->preamble_presented = true;
> > }
> >
> > - cs->out.handle = seq;
> > + job->secure = p->is_secure;
> > job->uf_sequence = seq;
> > + cs->out.handle = seq;
>
> At least it is no longer accessing cs->in, but that still looks like the
> wrong place
> to initialize the job.
>
> Why can't we fill that in directly after amdgpu_job_alloc() ?
There is not input member that is secure related in amdgpu_job_alloc() except
add an one:
amdgpu_job_alloc(adev, num_ibs, job, vm, secure)
It looks too much, isn't it?
Thanks,
Ray
>
> Regards,
> Christian.
>
> >
> > amdgpu_job_free_resources(job);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> > index e1dc229..cb9b650 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> > @@ -210,7 +210,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring,
> unsigned num_ibs,
> > if (job && ring->funcs->emit_cntxcntl) {
> > status |= job->preamble_status;
> > status |= job->preemption_status;
> > - amdgpu_ring_emit_cntxcntl(ring, status, false);
> > + amdgpu_ring_emit_cntxcntl(ring, status, job->secure);
> > }
> >
> > for (i = 0; i < num_ibs; ++i) {
> > @@ -229,7 +229,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring,
> unsigned num_ibs,
> > }
> >
> > if (ring->funcs->emit_tmz)
> > - amdgpu_ring_emit_tmz(ring, false, false);
> > + amdgpu_ring_emit_tmz(ring, false, job ? job->secure : false);
> >
> > #ifdef CONFIG_X86_64
> > if (!(adev->flags & AMD_IS_APU))
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
> > index dc7ee93..aa0e375 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
> > @@ -63,6 +63,8 @@ struct amdgpu_job {
> > uint64_tuf_addr;
> > uint64_tuf_sequence;
> >
> > + /* the job is due to a secure command submission */
> > + boolsecure;
> > };
> >
> > int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
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RE: [PATCH] drm/amdgpu: fix error handling in amdgpu_bo_list_create
> -Original Message-
> From: amd-gfx On Behalf Of
> Christian K?nig
> Sent: Thursday, September 19, 2019 1:43 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: fix error handling in amdgpu_bo_list_create
>
> We need to drop normal and userptr BOs separately.
>
> Signed-off-by: Christian König
Acked-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> index d497467b7fc6..94908bf269a6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> @@ -139,7 +139,12 @@ int amdgpu_bo_list_create(struct amdgpu_device
> *adev, struct drm_file *filp,
> return 0;
>
> error_free:
> - while (i--) {
> + for (i = 0; i < last_entry; ++i) {
> + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(array[i].tv.bo);
> +
> + amdgpu_bo_unref(&bo);
> + }
> + for (i = first_userptr; i < num_entries; ++i) {
> struct amdgpu_bo *bo = ttm_to_amdgpu_bo(array[i].tv.bo);
>
> amdgpu_bo_unref(&bo);
> --
> 2.17.1
>
> ___
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> amd-gfx@lists.freedesktop.org
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[PATCH v3 10/11] drm/amdgpu: job is secure iff CS is secure (v4)
Mark a job as secure, if and only if the command
submission flag has the secure flag set.
v2: fix the null job pointer while in vmid 0
submission.
v3: Context --> Command submission.
v4: filling cs parser with cs->in.flags
Signed-off-by: Huang Rui
Co-developed-by: Luben Tuikov
Signed-off-by: Luben Tuikov
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 11 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 2 ++
4 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 697e8e5..fd60695 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -485,6 +485,9 @@ struct amdgpu_cs_parser {
uint64_tbytes_moved;
uint64_tbytes_moved_vis;
+ /* secure cs */
+ boolis_secure;
+
/* user fence */
struct amdgpu_bo_list_entry uf_entry;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 51f3db0..9038dc1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -133,6 +133,14 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p, union drm_amdgpu_cs
goto free_chunk;
}
+ /**
+* The command submission (cs) is a union, so an assignment to
+* 'out' is destructive to the cs (at least the first 8
+* bytes). For this reason, inquire about the flags before the
+* assignment to 'out'.
+*/
+ p->is_secure = cs->in.flags & AMDGPU_CS_FLAGS_SECURE;
+
/* get chunks */
chunk_array_user = u64_to_user_ptr(cs->in.chunks);
if (copy_from_user(chunk_array, chunk_array_user,
@@ -1252,8 +1260,9 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
p->ctx->preamble_presented = true;
}
- cs->out.handle = seq;
+ job->secure = p->is_secure;
job->uf_sequence = seq;
+ cs->out.handle = seq;
amdgpu_job_free_resources(job);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index e1dc229..cb9b650 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -210,7 +210,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
if (job && ring->funcs->emit_cntxcntl) {
status |= job->preamble_status;
status |= job->preemption_status;
- amdgpu_ring_emit_cntxcntl(ring, status, false);
+ amdgpu_ring_emit_cntxcntl(ring, status, job->secure);
}
for (i = 0; i < num_ibs; ++i) {
@@ -229,7 +229,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
}
if (ring->funcs->emit_tmz)
- amdgpu_ring_emit_tmz(ring, false, false);
+ amdgpu_ring_emit_tmz(ring, false, job ? job->secure : false);
#ifdef CONFIG_X86_64
if (!(adev->flags & AMD_IS_APU))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index dc7ee93..aa0e375 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -63,6 +63,8 @@ struct amdgpu_job {
uint64_tuf_addr;
uint64_tuf_sequence;
+ /* the job is due to a secure command submission */
+ boolsecure;
};
int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
--
2.7.4
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[PATCH v2 09/11] drm/amdgpu: expand the context control interface with trust flag
This patch expands the context control function to support trusted flag while we
want to set command buffer in trusted mode.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 5 +++--
7 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 54741ba..e1dc229 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -210,7 +210,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
if (job && ring->funcs->emit_cntxcntl) {
status |= job->preamble_status;
status |= job->preemption_status;
- amdgpu_ring_emit_cntxcntl(ring, status);
+ amdgpu_ring_emit_cntxcntl(ring, status, false);
}
for (i = 0; i < num_ibs; ++i) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 34aa63a..5134d0d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -158,7 +158,8 @@ struct amdgpu_ring_funcs {
void (*begin_use)(struct amdgpu_ring *ring);
void (*end_use)(struct amdgpu_ring *ring);
void (*emit_switch_buffer) (struct amdgpu_ring *ring);
- void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
+ void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags,
+ bool trusted);
void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
@@ -242,7 +243,7 @@ struct amdgpu_ring {
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as)
(r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
-#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
+#define amdgpu_ring_emit_cntxcntl(r, d, s) (r)->funcs->emit_cntxcntl((r), (d),
(s))
#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r),
(d), (v), (m))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 18f741b..06698c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4514,7 +4514,9 @@ static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring
*ring)
amdgpu_ring_write(ring, 0);
}
-static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t
flags)
+static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
+uint32_t flags,
+bool trusted)
{
uint32_t dw2 = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 8c27c30..b4af1b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2972,7 +2972,8 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct
amdgpu_device *adev)
return clock;
}
-static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags,
+ bool trusted)
{
if (flags & AMDGPU_HAVE_CTX_SWITCH)
gfx_v6_0_ring_emit_vgt_flush(ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 48796b68..c08f5c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2309,7 +2309,8 @@ static void gfx_v7_0_ring_emit_ib_compute(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, control);
}
-static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags,
+ bool trusted)
{
uint32_t dw2 = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 98e5aa8..d3a23fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6393,7 +6393,8 @@ static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
amd
[PATCH v2 11/11] drm/amdgpu: set TMZ bits in PTEs for secure BO (v4)
From: Alex Deucher
If a buffer object is secure, i.e. created with
AMDGPU_GEM_CREATE_ENCRYPTED, then the TMZ bit of
the PTEs that belong the buffer object should be
set.
v1: design and draft the skeletion of TMZ bits setting on PTEs (Alex)
v2: return failure once create secure BO on non-TMZ platform (Ray)
v3: amdgpu_bo_encrypted() only checks the BO (Luben)
v4: move TMZ flag setting into amdgpu_vm_bo_update (Christian)
Signed-off-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Huang Rui
Signed-off-by: Luben Tuikov
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 12 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 11 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 22eab74..5332104 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -222,7 +222,8 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
AMDGPU_GEM_CREATE_CPU_GTT_USWC |
AMDGPU_GEM_CREATE_VRAM_CLEARED |
AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
- AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
+ AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
+ AMDGPU_GEM_CREATE_ENCRYPTED))
return -EINVAL;
@@ -230,6 +231,11 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
return -EINVAL;
+ if (!adev->tmz.enabled && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
+ DRM_ERROR("Cannot allocate secure buffer while tmz is
disabled\n");
+ return -EINVAL;
+ }
+
/* create a gem object to contain this object in */
if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
@@ -251,6 +257,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
resv = vm->root.base.bo->tbo.resv;
}
+ if (flags & AMDGPU_GEM_CREATE_ENCRYPTED) {
+ /* XXX: pad out alignment to meet TMZ requirements */
+ }
+
r = amdgpu_gem_object_create(adev, size, args->in.alignment,
(u32)(0x & args->in.domains),
flags, ttm_bo_type_device, resv, &gobj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 5a3c177..75c7392 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -224,6 +224,17 @@ static inline bool amdgpu_bo_explicit_sync(struct
amdgpu_bo *bo)
return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
}
+/**
+ * amdgpu_bo_encrypted - test if the BO is encrypted
+ * @bo: pointer to a buffer object
+ *
+ * Return true if the buffer object is encrypted, false otherwise.
+ */
+static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
+{
+ return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
+}
+
bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index b285ab2..8e13b1fd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1688,6 +1688,11 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
if (bo) {
flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
+
+ if (amdgpu_bo_encrypted(bo)) {
+ flags |= AMDGPU_PTE_TMZ;
+ }
+
bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
} else {
flags = 0x0;
--
2.7.4
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[PATCH v2 10/11] drm/amdgpu: job is secure iff CS is secure (v3)
Mark a job as secure, if and only if the command
submission flag has the secure flag set.
v2: fix the null job pointer while in vmid 0
submission.
v3: Context --> Command submission.
Signed-off-by: Huang Rui
Co-developed-by: Luben Tuikov
Signed-off-by: Luben Tuikov
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 8 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 2 ++
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 51f3db0..0077bb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1252,8 +1252,14 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
p->ctx->preamble_presented = true;
}
- cs->out.handle = seq;
+ /* The command submission (cs) is a union, so an assignment to
+* 'out' is destructive to the cs (at least the first 8
+* bytes). For this reason, inquire about the flags before the
+* assignment to 'out'.
+*/
+ job->secure = cs->in.flags & AMDGPU_CS_FLAGS_SECURE;
job->uf_sequence = seq;
+ cs->out.handle = seq;
amdgpu_job_free_resources(job);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index e1dc229..cb9b650 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -210,7 +210,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
if (job && ring->funcs->emit_cntxcntl) {
status |= job->preamble_status;
status |= job->preemption_status;
- amdgpu_ring_emit_cntxcntl(ring, status, false);
+ amdgpu_ring_emit_cntxcntl(ring, status, job->secure);
}
for (i = 0; i < num_ibs; ++i) {
@@ -229,7 +229,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
}
if (ring->funcs->emit_tmz)
- amdgpu_ring_emit_tmz(ring, false, false);
+ amdgpu_ring_emit_tmz(ring, false, job ? job->secure : false);
#ifdef CONFIG_X86_64
if (!(adev->flags & AMD_IS_APU))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index dc7ee93..aa0e375 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -63,6 +63,8 @@ struct amdgpu_job {
uint64_tuf_addr;
uint64_tuf_sequence;
+ /* the job is due to a secure command submission */
+ boolsecure;
};
int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
--
2.7.4
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[PATCH v2 07/11] drm/amdgpu: add tmz bit in frame control packet
This patch adds tmz bit in frame control pm4 packet, and it will used in future. Signed-off-by: Huang Rui Reviewed-by: Alex Deucher Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/nvd.h| 1 + drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nvd.h b/drivers/gpu/drm/amd/amdgpu/nvd.h index 1de9846..f3d8771 100644 --- a/drivers/gpu/drm/amd/amdgpu/nvd.h +++ b/drivers/gpu/drm/amd/amdgpu/nvd.h @@ -306,6 +306,7 @@ #definePACKET3_GET_LOD_STATS 0x8E #definePACKET3_DRAW_MULTI_PREAMBLE 0x8F #definePACKET3_FRAME_CONTROL 0x90 +# define FRAME_TMZ(1 << 0) # define FRAME_CMD(x) ((x) << 28) /* * x=0: tmz_begin diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h index edfe508..295d68c 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h @@ -286,6 +286,7 @@ #definePACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 #definePACKET3_SWITCH_BUFFER 0x8B #define PACKET3_FRAME_CONTROL 0x90 +# define FRAME_TMZ(1 << 0) # define FRAME_CMD(x) ((x) << 28) /* * x=0: tmz_begin -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2 08/11] drm/amdgpu: expand the emit tmz interface with trusted flag
This patch expands the emit_tmz function to support trusted flag while we want
to set command buffer in trusted mode.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 16
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 13 ++---
4 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 6882eeb..54741ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -229,7 +229,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
}
if (ring->funcs->emit_tmz)
- amdgpu_ring_emit_tmz(ring, false);
+ amdgpu_ring_emit_tmz(ring, false, false);
#ifdef CONFIG_X86_64
if (!(adev->flags & AMD_IS_APU))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 930316e..34aa63a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -166,7 +166,7 @@ struct amdgpu_ring_funcs {
void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
uint32_t reg0, uint32_t reg1,
uint32_t ref, uint32_t mask);
- void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
+ void (*emit_tmz)(struct amdgpu_ring *ring, bool start, bool trusted);
/* priority functions */
void (*set_priority) (struct amdgpu_ring *ring,
enum drm_sched_priority priority);
@@ -247,7 +247,7 @@ struct amdgpu_ring {
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r),
(d), (v), (m))
#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m)
(r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
-#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
+#define amdgpu_ring_emit_tmz(r, b, s) (r)->funcs->emit_tmz((r), (b), (s))
#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a2f4ff1..18f741b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -243,7 +243,8 @@ static int gfx_v10_0_rlc_backdoor_autoload_enable(struct
amdgpu_device *adev);
static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device
*adev);
static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
-static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start);
+static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start,
+ bool trusted);
static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t
queue_mask)
{
@@ -4521,7 +4522,7 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct
amdgpu_ring *ring, uint32_t flag
gfx_v10_0_ring_emit_ce_meta(ring,
flags & AMDGPU_IB_PREEMPTED ? true : false);
- gfx_v10_0_ring_emit_tmz(ring, true);
+ gfx_v10_0_ring_emit_tmz(ring, true, false);
dw2 |= 0x8000; /* set load_enable otherwise this package is just
NOPs */
if (flags & AMDGPU_HAVE_CTX_SWITCH) {
@@ -4679,10 +4680,17 @@ static void gfx_v10_0_ring_emit_de_meta(struct
amdgpu_ring *ring, bool resume)
sizeof(de_payload) >> 2);
}
-static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
+static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start,
+ bool trusted)
{
amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
- amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
+ /*
+* cmd = 0: frame begin
+* cmd = 1: frame end
+*/
+ amdgpu_ring_write(ring,
+ ((ring->adev->tmz.enabled && trusted) ? FRAME_TMZ : 0)
+ | FRAME_CMD(start ? 0 : 1));
}
static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 90348fb29..fa264d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5240,10 +5240,17 @@ static void gfx_v9_0_ring_emit_de_meta(struct
amdgpu_ring *ring)
amdgpu_ring_write_multiple(ring,
[PATCH v2 06/11] drm/amdgpu: add function to check tmz capability (v4)
Add a function to check tmz capability with kernel parameter and ASIC type.
v2: use a per device tmz variable instead of global amdgpu_tmz.
v3: refine the comments for the function. (Luben)
v4: add amdgpu_tmz.c/h for future use.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c| 49 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h| 3 ++
4 files changed, 56 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 91369c8..270ce82 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -55,7 +55,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o
amdgpu_vm_cpu.o \
amdgpu_vm_sdma.o amdgpu_pmu.o amdgpu_discovery.o amdgpu_ras_eeprom.o
amdgpu_nbio.o \
- amdgpu_umc.o smu_v11_0_i2c.o
+ amdgpu_umc.o smu_v11_0_i2c.o amdgpu_tmz.o
amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2535db2..e376fe5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -63,6 +63,7 @@
#include "amdgpu_xgmi.h"
#include "amdgpu_ras.h"
#include "amdgpu_pmu.h"
+#include "amdgpu_tmz.h"
#include
@@ -1032,6 +1033,8 @@ static int amdgpu_device_check_arguments(struct
amdgpu_device *adev)
adev->firmware.load_type = amdgpu_ucode_get_load_type(adev,
amdgpu_fw_load_type);
+ adev->tmz.enabled = amdgpu_is_tmz(adev);
+
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
new file mode 100644
index 000..14a5500
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include "amdgpu.h"
+#include "amdgpu_tmz.h"
+
+
+/**
+ * amdgpu_is_tmz - validate trust memory zone
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Return true if @dev supports trusted memory zones (TMZ), and return false if
+ * @dev does not support TMZ.
+ */
+bool amdgpu_is_tmz(struct amdgpu_device *adev)
+{
+ if (!amdgpu_tmz)
+ return false;
+
+ if (adev->asic_type < CHIP_RAVEN || adev->asic_type == CHIP_ARCTURUS) {
+ dev_warn(adev->dev, "doesn't support trusted memory zones
(TMZ)\n");
+ return false;
+ }
+
+ dev_info(adev->dev, "TMZ feature is enabled\n");
+
+ return true;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
index 24bbbc2..28e0517 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
@@ -33,4 +33,7 @@ struct amdgpu_tmz {
boolenabled;
};
+
+extern bool amdgpu_is_tmz(struct amdgpu_device *adev);
+
#endif
--
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[PATCH v2 04/11] drm/amdgpu: add tmz feature parameter (v2)
This patch adds tmz parameter to enable/disable the feature in the amdgpu kernel
module. Nomally, by default, it should be auto (rely on the hardware
capability).
But right now, it need to set "off" to avoid breaking other developers'
work because it's not totally completed.
Will set "auto" till the feature is stable and completely verified.
v2: add "auto" option for future use.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a1516a3..930643c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -172,6 +172,7 @@ extern int amdgpu_force_asic_type;
#ifdef CONFIG_HSA_AMD
extern int sched_policy;
#endif
+extern int amdgpu_tmz;
#ifdef CONFIG_DRM_AMDGPU_SI
extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 6978d17..606f1d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -145,6 +145,7 @@ int amdgpu_discovery = -1;
int amdgpu_mes = 0;
int amdgpu_noretry = 1;
int amdgpu_force_asic_type = -1;
+int amdgpu_tmz = 0;
struct amdgpu_mgpu_info mgpu_info = {
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@@ -752,6 +753,16 @@ uint amdgpu_dm_abm_level = 0;
MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight
reduction level) ");
module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
+/**
+ * DOC: tmz (int)
+ * Trust Memory Zone (TMZ) is a method to protect the contents being written to
+ * and read from memory.
+ *
+ * The default value: 0 (off). TODO: change to auto till it is completed.
+ */
+MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 =
on)");
+module_param_named(tmz, amdgpu_tmz, int, 0444);
+
static const struct pci_device_id pciidlist[] = {
#ifdef CONFIG_DRM_AMDGPU_SI
{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
--
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[PATCH v2 01/11] drm/amdgpu: add UAPI for creating encrypted buffers
From: Alex Deucher
Add a flag to the GEM_CREATE ioctl to create encrypted buffers.
Buffers with this flag set will be created with the TMZ bit set
in the PTEs or engines accessing them. This is required in order
to properly access the data from the engines.
Signed-off-by: Alex Deucher
Reviewed-by: Huang Rui
Reviewed-by: Christian König
---
include/uapi/drm/amdgpu_drm.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index f3ad429..f90b453 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -135,6 +135,11 @@ extern "C" {
* releasing the memory
*/
#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
+/* Flag that BO will be encrypted and that the TMZ bit should be
+ * set in the PTEs when mapping this buffer via GPUVM or
+ * accessing it with various hw blocks
+ */
+#define AMDGPU_GEM_CREATE_ENCRYPTED(1 << 10)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
--
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[PATCH v2 03/11] drm/amdgpu: define the TMZ bit for the PTE
From: Alex Deucher Define the TMZ (encryption) bit in the page table entry (PTE) for Raven and newer asics. Signed-off-by: Alex Deucher Reviewed-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 3352a87..4b5d283 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -53,6 +53,9 @@ struct amdgpu_bo_list_entry; #define AMDGPU_PTE_SYSTEM (1ULL << 1) #define AMDGPU_PTE_SNOOPED (1ULL << 2) +/* RV+ */ +#define AMDGPU_PTE_TMZ (1ULL << 3) + /* VI only */ #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2 02/11] drm/amdgpu: add UAPI to create secure commands (v3)
From: Luben Tuikov
Add a flag to the command submission IOCTL
structure which when present indicates that this
command submission should be treated as
secure. The kernel driver uses this flag to
determine whether the engine should be
transitioned to secure or unsecure, or the work
can be submitted to a secure queue depending on
the IP.
v3: the flag is now at command submission IOCTL
Signed-off-by: Luben Tuikov
Reviewed-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index f90b453..a101eea 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -207,6 +207,9 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_OP_QUERY_STATE 3
#define AMDGPU_CTX_OP_QUERY_STATE2 4
+/* Flag the command submission as secure */
+#define AMDGPU_CS_FLAGS_SECURE (1 << 0)
+
/* GPU reset status */
#define AMDGPU_CTX_NO_RESET0
/* this the context caused it */
@@ -562,7 +565,7 @@ struct drm_amdgpu_cs_in {
/** Handle of resource list associated with CS */
__u32 bo_list_handle;
__u32 num_chunks;
- __u32 _pad;
+ __u32 flags;
/** this points to __u64 * which point to cs chunks */
__u64 chunks;
};
--
2.7.4
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[PATCH v2 05/11] drm/amdgpu: add amdgpu_tmz data structure
This patch to add amdgpu_tmz structure which stores all tmz related fields.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h | 36 +
2 files changed, 41 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 930643c..697e8e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -89,6 +89,7 @@
#include "amdgpu_mes.h"
#include "amdgpu_umc.h"
#include "amdgpu_mmhub.h"
+#include "amdgpu_tmz.h"
#define MAX_GPU_INSTANCE 16
@@ -916,6 +917,9 @@ struct amdgpu_device {
boolenable_mes;
struct amdgpu_mes mes;
+ /* tmz */
+ struct amdgpu_tmz tmz;
+
struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
int num_ip_blocks;
struct mutexmn_lock;
@@ -927,7 +931,7 @@ struct amdgpu_device {
atomic64_t gart_pin_size;
/* soc15 register offset based on ip, instance and segment */
- uint32_t*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
+ uint32_t*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
const struct amdgpu_df_funcs*df_funcs;
const struct amdgpu_mmhub_funcs *mmhub_funcs;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
new file mode 100644
index 000..24bbbc2
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __AMDGPU_TMZ_H__
+#define __AMDGPU_TMZ_H__
+
+#include "amdgpu.h"
+
+/*
+ * Trust memory zone stuff
+ */
+struct amdgpu_tmz {
+ boolenabled;
+};
+
+#endif
--
2.7.4
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[PATCH v2 00/11] drm/amdgpu: introduce secure buffer object support (trusted memory zone)
Hi all, These series of patches introduce a feature to support secure buffer object. The Trusted Memory Zone (TMZ) is a method to protect the contents being written to and read from memory. We use TMZ hardware memory protection scheme to implement the secure buffer object support. TMZ is the page-level protection that hardware will detect the TMZ bit in the page table entry to set the current page is encrypted. With this hardware feature, we design a BO-level protection in kernel driver to provide a new flag AMDGPU_GEM_CREATE_ENCRYPTED to gem create ioctl to libdrm for the secure buffer allocation. And also provide the new AMDGPU_CS_FLAGS_SECURE to indicate the command submmission is trusted or not. If the BO is secure, then the data is encrypted, only the trusted IP blocks such as gfx, sdma, vcn are able to decrypt. CPU as the un-trusted IP are unable to read the secure buffer. We will submit the new secure command later for libdrm, and create a new test suite to verify the security feature in the libdrm unit tests. Suite id = 11: Name 'Security Tests status: ENABLED' Test id 1: Name: 'allocate secure buffer test status: ENABLED' Test id 2: Name: 'graphics secure command submission status: ENABLED' Changes from V1 -> V2: - Change the UAPI from secure context to secure command submission for display server and client usage. (Thanks Luben) - Remove ttm_mem_reg macro to get ttm_bo object. - Move the amdgpu_bo_encrypted into amdgpu_vm_bo_update(). Thanks, Ray Alex Deucher (3): drm/amdgpu: add UAPI for creating encrypted buffers drm/amdgpu: define the TMZ bit for the PTE drm/amdgpu: set TMZ bits in PTEs for secure BO (v4) Huang Rui (7): drm/amdgpu: add tmz feature parameter (v2) drm/amdgpu: add amdgpu_tmz data structure drm/amdgpu: add function to check tmz capability (v4) drm/amdgpu: add tmz bit in frame control packet drm/amdgpu: expand the emit tmz interface with trusted flag drm/amdgpu: expand the context control interface with trust flag drm/amdgpu: job is secure iff CS is secure (v3) Luben Tuikov (1): drm/amdgpu: add UAPI to create secure commands (v3) drivers/gpu/drm/amd/amdgpu/Makefile| 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7 - drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 8 - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 11 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 12 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_job.h| 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 11 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 9 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c| 49 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h| 39 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 20 +--- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 +++--- drivers/gpu/drm/amd/amdgpu/nvd.h | 1 + drivers/gpu/drm/amd/amdgpu/soc15d.h| 1 + include/uapi/drm/amdgpu_drm.h | 10 +- 22 files changed, 199 insertions(+), 23 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 14/14] drm/amdgpu: set TMZ bits in PTEs for secure bo (v2)
> -Original Message-
> From: Koenig, Christian
> Sent: Thursday, September 12, 2019 7:49 PM
> To: Huang, Ray
> Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
> Deucher, Alexander ; Tuikov, Luben
> ; Liu, Aaron
> Subject: Re: [PATCH 14/14] drm/amdgpu: set TMZ bits in PTEs for secure bo
> (v2)
>
> Am 12.09.19 um 12:27 schrieb Huang, Ray:
> > On Wed, Sep 11, 2019 at 08:13:19PM +0800, Koenig, Christian wrote:
> >> Am 11.09.19 um 13:50 schrieb Huang, Ray:
> >>> From: Alex Deucher
> >>>
> >>> If one bo is secure (created with AMDGPU_GEM_CREATE_ENCRYPTED),
> the
> >>> TMZ bits of PTEs that belongs that bo should be set. Then psp is
> >>> able to protect the pages of this bo to avoid the access from an "untrust"
> domain such as CPU.
> >>>
> >>> v1: design and draft the skeletion of tmz bits setting on PTEs
> >>> (Alex)
> >>> v2: return failure once create secure bo on no-tmz platform (Ray)
> >>>
> >>> Signed-off-by: Alex Deucher
> >>> Reviewed-by: Huang Rui
> >>> Signed-off-by: Huang Rui
> >>> ---
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 12 +++-
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 ++
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 5 +
> >>>3 files changed, 26 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> >>> index 22eab74..5332104 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> >>> @@ -222,7 +222,8 @@ int amdgpu_gem_create_ioctl(struct drm_device
> *dev, void *data,
> >>> AMDGPU_GEM_CREATE_CPU_GTT_USWC |
> >>> AMDGPU_GEM_CREATE_VRAM_CLEARED |
> >>> AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
> >>> - AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
> >>> + AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
> >>> + AMDGPU_GEM_CREATE_ENCRYPTED))
> >>>
> >>> return -EINVAL;
> >>>
> >>> @@ -230,6 +231,11 @@ int amdgpu_gem_create_ioctl(struct
> drm_device *dev, void *data,
> >>> if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
> >>> return -EINVAL;
> >>>
> >>> + if (!adev->tmz.enabled && (flags &
> AMDGPU_GEM_CREATE_ENCRYPTED)) {
> >>> + DRM_ERROR("Cannot allocate secure buffer while tmz is
> disabled\n");
> >>> + return -EINVAL;
> >>> + }
> >>> +
> >>> /* create a gem object to contain this object in */
> >>> if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
> >>> AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))
> { @@ -251,6
> >>> +257,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev,
> void *data,
> >>> resv = vm->root.base.bo->tbo.resv;
> >>> }
> >>>
> >>> + if (flags & AMDGPU_GEM_CREATE_ENCRYPTED) {
> >>> + /* XXX: pad out alignment to meet TMZ requirements */
> >>> + }
> >>> +
> >>> r = amdgpu_gem_object_create(adev, size, args->in.alignment,
> >>>(u32)(0x &
> >>> args->in.domains),
> >>>flags, ttm_bo_type_device, resv,
> >>> &gobj);
> diff --git
> >>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> >>> index 5a3c177..286e2e2 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> >>> @@ -224,6 +224,16 @@ static inline bool
> amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
> >>> return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
> >>>}
> >>>
> >>> +/**
> >>> + * amdgpu_bo_encrypted - return whether the bo is encrypted */
> >>> +static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo) {
> >>> + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> >>> +
> >>> + return adev->tmz.e
RE: [PATCH] drm/amdgpu: remove program of lbpw for renoir
> -Original Message-
> From: Liu, Aaron
> Sent: Monday, September 16, 2019 9:40 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Liu, Aaron
> Subject: [PATCH] drm/amdgpu: remove program of lbpw for renoir
>
> These is no LBPW on Renoir. So removing program of lbpw for renoir.
>
> Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index b75ef89..fe21ef8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1646,7 +1646,6 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device
> *adev)
>
> switch (adev->asic_type) {
> case CHIP_RAVEN:
> - case CHIP_RENOIR:
> gfx_v9_0_init_lbpw(adev);
> break;
> case CHIP_VEGA20:
> @@ -3013,7 +3012,6 @@ static int gfx_v9_0_rlc_resume(struct
> amdgpu_device *adev)
>
> switch (adev->asic_type) {
> case CHIP_RAVEN:
> - case CHIP_RENOIR:
> if (amdgpu_lbpw == 0)
> gfx_v9_0_enable_lbpw(adev, false);
> else
> --
> 2.7.4
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Re: [PATCH 14/14] drm/amdgpu: set TMZ bits in PTEs for secure bo (v2)
On Wed, Sep 11, 2019 at 08:13:19PM +0800, Koenig, Christian wrote:
> Am 11.09.19 um 13:50 schrieb Huang, Ray:
> > From: Alex Deucher
> >
> > If one bo is secure (created with AMDGPU_GEM_CREATE_ENCRYPTED), the TMZ
> > bits of
> > PTEs that belongs that bo should be set. Then psp is able to protect the
> > pages
> > of this bo to avoid the access from an "untrust" domain such as CPU.
> >
> > v1: design and draft the skeletion of tmz bits setting on PTEs (Alex)
> > v2: return failure once create secure bo on no-tmz platform (Ray)
> >
> > Signed-off-by: Alex Deucher
> > Reviewed-by: Huang Rui
> > Signed-off-by: Huang Rui
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 12 +++-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 ++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 5 +
> > 3 files changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> > index 22eab74..5332104 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> > @@ -222,7 +222,8 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev,
> > void *data,
> > AMDGPU_GEM_CREATE_CPU_GTT_USWC |
> > AMDGPU_GEM_CREATE_VRAM_CLEARED |
> > AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
> > - AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
> > + AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
> > + AMDGPU_GEM_CREATE_ENCRYPTED))
> >
> > return -EINVAL;
> >
> > @@ -230,6 +231,11 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev,
> > void *data,
> > if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
> > return -EINVAL;
> >
> > + if (!adev->tmz.enabled && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
> > + DRM_ERROR("Cannot allocate secure buffer while tmz is
> > disabled\n");
> > + return -EINVAL;
> > + }
> > +
> > /* create a gem object to contain this object in */
> > if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
> > AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
> > @@ -251,6 +257,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev,
> > void *data,
> > resv = vm->root.base.bo->tbo.resv;
> > }
> >
> > + if (flags & AMDGPU_GEM_CREATE_ENCRYPTED) {
> > + /* XXX: pad out alignment to meet TMZ requirements */
> > + }
> > +
> > r = amdgpu_gem_object_create(adev, size, args->in.alignment,
> > (u32)(0x & args->in.domains),
> > flags, ttm_bo_type_device, resv, &gobj);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> > index 5a3c177..286e2e2 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> > @@ -224,6 +224,16 @@ static inline bool amdgpu_bo_explicit_sync(struct
> > amdgpu_bo *bo)
> > return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
> > }
> >
> > +/**
> > + * amdgpu_bo_encrypted - return whether the bo is encrypted
> > + */
> > +static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
> > +{
> > + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> > +
> > + return adev->tmz.enabled && (bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED);
>
> Checking the adev->tmz.enabled flags should be dropped here.
>
That's fine. BO should be validated while it is created.
But if the BO is created by vmid 0, is this checking needed?
> > +}
> > +
> > bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
> > void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > index 3663655..8f00bb2 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > @@ -1434,6 +1434,8 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
> > uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg
> > *mem)
> > {
> > uint64_t flags = 0;
> > + struct ttm_buffer_object *tbo = ttm_mem_reg_to_bo(me
[PATCH 10/14] drm/amdgpu: expand the emit tmz interface with trusted flag
This patch expands the emit_tmz function to support trusted flag while we want
to set command buffer in trusted mode.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 16
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 13 ++---
4 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 6882eeb..54741ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -229,7 +229,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
}
if (ring->funcs->emit_tmz)
- amdgpu_ring_emit_tmz(ring, false);
+ amdgpu_ring_emit_tmz(ring, false, false);
#ifdef CONFIG_X86_64
if (!(adev->flags & AMD_IS_APU))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 930316e..34aa63a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -166,7 +166,7 @@ struct amdgpu_ring_funcs {
void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
uint32_t reg0, uint32_t reg1,
uint32_t ref, uint32_t mask);
- void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
+ void (*emit_tmz)(struct amdgpu_ring *ring, bool start, bool trusted);
/* priority functions */
void (*set_priority) (struct amdgpu_ring *ring,
enum drm_sched_priority priority);
@@ -247,7 +247,7 @@ struct amdgpu_ring {
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r),
(d), (v), (m))
#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m)
(r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
-#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
+#define amdgpu_ring_emit_tmz(r, b, s) (r)->funcs->emit_tmz((r), (b), (s))
#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a2f4ff1..18f741b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -243,7 +243,8 @@ static int gfx_v10_0_rlc_backdoor_autoload_enable(struct
amdgpu_device *adev);
static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device
*adev);
static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
-static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start);
+static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start,
+ bool trusted);
static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t
queue_mask)
{
@@ -4521,7 +4522,7 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct
amdgpu_ring *ring, uint32_t flag
gfx_v10_0_ring_emit_ce_meta(ring,
flags & AMDGPU_IB_PREEMPTED ? true : false);
- gfx_v10_0_ring_emit_tmz(ring, true);
+ gfx_v10_0_ring_emit_tmz(ring, true, false);
dw2 |= 0x8000; /* set load_enable otherwise this package is just
NOPs */
if (flags & AMDGPU_HAVE_CTX_SWITCH) {
@@ -4679,10 +4680,17 @@ static void gfx_v10_0_ring_emit_de_meta(struct
amdgpu_ring *ring, bool resume)
sizeof(de_payload) >> 2);
}
-static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
+static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start,
+ bool trusted)
{
amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
- amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
+ /*
+* cmd = 0: frame begin
+* cmd = 1: frame end
+*/
+ amdgpu_ring_write(ring,
+ ((ring->adev->tmz.enabled && trusted) ? FRAME_TMZ : 0)
+ | FRAME_CMD(start ? 0 : 1));
}
static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 90348fb29..fa264d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5240,10 +5240,17 @@ static void gfx_v9_0_ring_emit_de_meta(struct
amdgpu_ring *ring)
amdgpu_ring_write_multiple(ring, (void *)&de_payload,
size
[PATCH 02/14] drm/amdgpu: add UAPI for creating secure contexts (v2)
From: Alex Deucher
Add a flag for when allocating a context to flag it as
secure. The kernel driver will use this flag to determine
whether a rendering context is secure or not so that the
engine can be transitioned between secure or unsecure
or the work can be submitted to a secure queue depending
on the IP.
v2: the flag will be used for security, so remove the comment (Ray)
Signed-off-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Huang Rui
---
include/uapi/drm/amdgpu_drm.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index f90b453..7aab4e1 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -207,6 +207,9 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_OP_QUERY_STATE 3
#define AMDGPU_CTX_OP_QUERY_STATE2 4
+/* Flag the context as secure */
+#define AMDGPU_CTX_ALLOC_FLAGS_SECURE (1 << 0)
+
/* GPU reset status */
#define AMDGPU_CTX_NO_RESET0
/* this the context caused it */
@@ -241,7 +244,6 @@ union drm_amdgpu_bo_list {
struct drm_amdgpu_ctx_in {
/** AMDGPU_CTX_OP_* */
__u32 op;
- /** For future use, no flags defined so far */
__u32 flags;
__u32 ctx_id;
/** AMDGPU_CTX_PRIORITY_* */
--
2.7.4
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[PATCH 01/14] drm/amdgpu: add UAPI for creating encrypted buffers
From: Alex Deucher
Add a flag to the GEM_CREATE ioctl to create encrypted buffers.
Buffers with this flag set will be created with the TMZ bit set
in the PTEs or engines accessing them. This is required in order
to properly access the data from the engines.
Signed-off-by: Alex Deucher
Reviewed-by: Huang Rui
---
include/uapi/drm/amdgpu_drm.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index f3ad429..f90b453 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -135,6 +135,11 @@ extern "C" {
* releasing the memory
*/
#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
+/* Flag that BO will be encrypted and that the TMZ bit should be
+ * set in the PTEs when mapping this buffer via GPUVM or
+ * accessing it with various hw blocks
+ */
+#define AMDGPU_GEM_CREATE_ENCRYPTED(1 << 10)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
--
2.7.4
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[PATCH 14/14] drm/amdgpu: set TMZ bits in PTEs for secure bo (v2)
From: Alex Deucher
If one bo is secure (created with AMDGPU_GEM_CREATE_ENCRYPTED), the TMZ bits of
PTEs that belongs that bo should be set. Then psp is able to protect the pages
of this bo to avoid the access from an "untrust" domain such as CPU.
v1: design and draft the skeletion of tmz bits setting on PTEs (Alex)
v2: return failure once create secure bo on no-tmz platform (Ray)
Signed-off-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 12 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 5 +
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 22eab74..5332104 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -222,7 +222,8 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
AMDGPU_GEM_CREATE_CPU_GTT_USWC |
AMDGPU_GEM_CREATE_VRAM_CLEARED |
AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
- AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
+ AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
+ AMDGPU_GEM_CREATE_ENCRYPTED))
return -EINVAL;
@@ -230,6 +231,11 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
return -EINVAL;
+ if (!adev->tmz.enabled && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
+ DRM_ERROR("Cannot allocate secure buffer while tmz is
disabled\n");
+ return -EINVAL;
+ }
+
/* create a gem object to contain this object in */
if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
@@ -251,6 +257,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
resv = vm->root.base.bo->tbo.resv;
}
+ if (flags & AMDGPU_GEM_CREATE_ENCRYPTED) {
+ /* XXX: pad out alignment to meet TMZ requirements */
+ }
+
r = amdgpu_gem_object_create(adev, size, args->in.alignment,
(u32)(0x & args->in.domains),
flags, ttm_bo_type_device, resv, &gobj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 5a3c177..286e2e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -224,6 +224,16 @@ static inline bool amdgpu_bo_explicit_sync(struct
amdgpu_bo *bo)
return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
}
+/**
+ * amdgpu_bo_encrypted - return whether the bo is encrypted
+ */
+static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
+{
+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+
+ return adev->tmz.enabled && (bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED);
+}
+
bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 3663655..8f00bb2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1434,6 +1434,8 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
{
uint64_t flags = 0;
+ struct ttm_buffer_object *tbo = ttm_mem_reg_to_bo(mem);
+ struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
if (mem && mem->mem_type != TTM_PL_SYSTEM)
flags |= AMDGPU_PTE_VALID;
@@ -1444,6 +1446,9 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm,
struct ttm_mem_reg *mem)
if (ttm->caching_state == tt_cached)
flags |= AMDGPU_PTE_SNOOPED;
}
+ if (amdgpu_bo_encrypted(abo)) {
+ flags |= AMDGPU_PTE_TMZ;
+ }
return flags;
}
--
2.7.4
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[PATCH 00/14] drm/amdgpu: introduce secure buffer object support (trusted memory zone)
Hi all, These series of patches introduce a feature to support secure buffer object. The Trusted Memory Zone (TMZ) is a method to protect the contents being written to and read from memory. We use TMZ hardware memory protection scheme to implement the secure buffer object support. TMZ is the page-level protection that hardware will detect the TMZ bit in the page table entry to set the current page is encrypted. With this hardware feature, we design a BO-level protection in kernel driver to provide a new flag AMDGPU_GEM_CREATE_ENCRYPTED to gem create ioctl to libdrm for the secure buffer allocation. And also provide the AMDGPU_CTX_ALLOC_FLAGS_SECURE to indicate the context is trusted or not. If the BO is secure, then the data is encrypted, only the trusted IP blocks such as gfx, sdma, vcn are able to decrypt. CPU as the un-trusted IP are unable to read the secure buffer. We will submit the new secure context interface later for libdrm, and create a new test suite to verify the security feature in the libdrm unit tests. Suite id = 11: Name 'Security Tests status: ENABLED' Test id 1: Name: 'allocate secure buffer test status: ENABLED' Test id 2: Name: 'graphics command submission under secure context status: ENABLED' Thanks, Ray Alex Deucher (4): drm/amdgpu: add UAPI for creating encrypted buffers drm/amdgpu: add UAPI for creating secure contexts (v2) drm/amdgpu: define the TMZ bit for the PTE drm/amdgpu: set TMZ bits in PTEs for secure bo (v2) Huang Rui (10): drm/amdgpu: add tmz feature parameter (v2) drm/amdgpu: add amdgpu_tmz data structure drm/amdgpu: add function to check tmz capability (v4) drm/ttm: add helper to get buffer object with ttm_mem_reg drm/amdgpu: revise the function to allocate secure context (v2) drm/amdgpu: add tmz bit in frame control packet drm/amdgpu: expand the emit tmz interface with trusted flag drm/amdgpu: expand the context control interface with trust flag drm/amdgpu: set trusted mode while the job is under secure context (v2) drm/amdgpu: modify the method to use mem under buffer object for amdgpu_ttm_tt_pte_flags drivers/gpu/drm/amd/amdgpu/Makefile| 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7 - drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 19 +--- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 11 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 12 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_job.h| 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 9 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c| 49 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h| 39 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 23 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 20 +--- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 +++--- drivers/gpu/drm/amd/amdgpu/nvd.h | 1 + drivers/gpu/drm/amd/amdgpu/soc15d.h| 1 + include/drm/ttm/ttm_bo_driver.h| 13 include/uapi/drm/amdgpu_drm.h | 9 +- 25 files changed, 230 insertions(+), 34 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 09/14] drm/amdgpu: add tmz bit in frame control packet
This patch adds tmz bit in frame control pm4 packet, and it will used in future. Signed-off-by: Huang Rui Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nvd.h| 1 + drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nvd.h b/drivers/gpu/drm/amd/amdgpu/nvd.h index 1de9846..f3d8771 100644 --- a/drivers/gpu/drm/amd/amdgpu/nvd.h +++ b/drivers/gpu/drm/amd/amdgpu/nvd.h @@ -306,6 +306,7 @@ #definePACKET3_GET_LOD_STATS 0x8E #definePACKET3_DRAW_MULTI_PREAMBLE 0x8F #definePACKET3_FRAME_CONTROL 0x90 +# define FRAME_TMZ(1 << 0) # define FRAME_CMD(x) ((x) << 28) /* * x=0: tmz_begin diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h index edfe508..295d68c 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h @@ -286,6 +286,7 @@ #definePACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 #definePACKET3_SWITCH_BUFFER 0x8B #define PACKET3_FRAME_CONTROL 0x90 +# define FRAME_TMZ(1 << 0) # define FRAME_CMD(x) ((x) << 28) /* * x=0: tmz_begin -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/14] drm/amdgpu: modify the method to use mem under buffer object for amdgpu_ttm_tt_pte_flags
amdgpu_ttm_tt_pte_flags will be used for updating tmz bits while the bo is
secure, so we need pass the ttm_mem_reg under a buffer object.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c05638c..3663655 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1117,8 +1117,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
} else {
/* allocate GART space */
- tmp = bo->mem;
- tmp.mm_node = NULL;
+ tmp = bo->mem; /* cache bo->mem */
+ bo->mem.mm_node = NULL;
placement.num_placement = 1;
placement.placement = &placements;
placement.num_busy_placement = 1;
@@ -1128,23 +1128,25 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
TTM_PL_FLAG_TT;
- r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
- if (unlikely(r))
+ r = ttm_bo_mem_space(bo, &placement, &bo->mem, &ctx);
+ if (unlikely(r)) {
+ bo->mem = tmp;
return r;
+ }
/* compute PTE flags for this buffer object */
- flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
+ flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &bo->mem);
/* Bind pages */
- gtt->offset = (u64)tmp.start << PAGE_SHIFT;
+ gtt->offset = (u64)bo->mem.start << PAGE_SHIFT;
r = amdgpu_ttm_gart_bind(adev, bo, flags);
if (unlikely(r)) {
+ bo->mem = tmp;
ttm_bo_mem_put(bo, &tmp);
return r;
}
- ttm_bo_mem_put(bo, &bo->mem);
- bo->mem = tmp;
+ ttm_bo_mem_put(bo, &tmp);
}
bo->offset = (bo->mem.start << PAGE_SHIFT) +
--
2.7.4
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[PATCH 08/14] drm/amdgpu: revise the function to allocate secure context (v2)
The is_secure flag will indicate the current conext is protected or not.
v2: while user mode asks to create a context, but if tmz is disabled, it should
return failure.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 19 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 1 +
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 45a30aa..ae28aec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -72,7 +72,8 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp,
static int amdgpu_ctx_init(struct amdgpu_device *adev,
enum drm_sched_priority priority,
struct drm_file *filp,
- struct amdgpu_ctx *ctx)
+ struct amdgpu_ctx *ctx,
+ uint32_t flags)
{
unsigned num_entities = amdgpu_ctx_total_num_entities();
unsigned i, j, k;
@@ -121,6 +122,9 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
ctx->init_priority = priority;
ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;
+ if (flags & AMDGPU_CTX_ALLOC_FLAGS_SECURE)
+ ctx->is_secure = true;
+
for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
@@ -253,7 +257,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
struct amdgpu_fpriv *fpriv,
struct drm_file *filp,
enum drm_sched_priority priority,
- uint32_t *id)
+ uint32_t *id, uint32_t flags)
{
struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
struct amdgpu_ctx *ctx;
@@ -272,7 +276,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
}
*id = (uint32_t)r;
- r = amdgpu_ctx_init(adev, priority, filp, ctx);
+ r = amdgpu_ctx_init(adev, priority, filp, ctx, flags);
if (r) {
idr_remove(&mgr->ctx_handles, *id);
*id = 0;
@@ -407,6 +411,12 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_fpriv *fpriv = filp->driver_priv;
+ if (!adev->tmz.enabled &&
+ (args->in.flags & AMDGPU_CTX_ALLOC_FLAGS_SECURE)) {
+ DRM_ERROR("Cannot allocate secure context while tmz is
disabled\n");
+ return -EINVAL;
+ }
+
r = 0;
id = args->in.ctx_id;
priority = amdgpu_to_sched_priority(args->in.priority);
@@ -418,7 +428,8 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
switch (args->in.op) {
case AMDGPU_CTX_OP_ALLOC_CTX:
- r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id);
+ r = amdgpu_ctx_alloc(adev, fpriv, filp, priority,
+&id, args->in.flags);
args->out.alloc.ctx_id = id;
break;
case AMDGPU_CTX_OP_FREE_CTX:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index da80863..aa8642b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -45,6 +45,7 @@ struct amdgpu_ctx {
struct dma_fence**fences;
struct amdgpu_ctx_entity*entities[AMDGPU_HW_IP_NUM];
boolpreamble_presented;
+ boolis_secure;
enum drm_sched_priority init_priority;
enum drm_sched_priority override_priority;
struct mutexlock;
--
2.7.4
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[PATCH 12/14] drm/amdgpu: set trusted mode while the job is under secure context (v2)
While user mode submit a command with secure context, we should set the command
buffer with trusted mode.
v2: fix the null job pointer while in vmid 0 submission.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 2 ++
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 51f3db0..60e7b79 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1252,6 +1252,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
p->ctx->preamble_presented = true;
}
+ job->secure = p->ctx->is_secure;
cs->out.handle = seq;
job->uf_sequence = seq;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index e1dc229..cb9b650 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -210,7 +210,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
if (job && ring->funcs->emit_cntxcntl) {
status |= job->preamble_status;
status |= job->preemption_status;
- amdgpu_ring_emit_cntxcntl(ring, status, false);
+ amdgpu_ring_emit_cntxcntl(ring, status, job->secure);
}
for (i = 0; i < num_ibs; ++i) {
@@ -229,7 +229,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
}
if (ring->funcs->emit_tmz)
- amdgpu_ring_emit_tmz(ring, false, false);
+ amdgpu_ring_emit_tmz(ring, false, job ? job->secure : false);
#ifdef CONFIG_X86_64
if (!(adev->flags & AMD_IS_APU))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index dc7ee93..59f1dbc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -63,6 +63,8 @@ struct amdgpu_job {
uint64_tuf_addr;
uint64_tuf_sequence;
+ /* the job is under secure context */
+ boolsecure;
};
int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
--
2.7.4
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[PATCH 11/14] drm/amdgpu: expand the context control interface with trust flag
This patch expands the context control function to support trusted flag while we
want to set command buffer in trusted mode.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 5 +++--
7 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 54741ba..e1dc229 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -210,7 +210,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
if (job && ring->funcs->emit_cntxcntl) {
status |= job->preamble_status;
status |= job->preemption_status;
- amdgpu_ring_emit_cntxcntl(ring, status);
+ amdgpu_ring_emit_cntxcntl(ring, status, false);
}
for (i = 0; i < num_ibs; ++i) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 34aa63a..5134d0d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -158,7 +158,8 @@ struct amdgpu_ring_funcs {
void (*begin_use)(struct amdgpu_ring *ring);
void (*end_use)(struct amdgpu_ring *ring);
void (*emit_switch_buffer) (struct amdgpu_ring *ring);
- void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
+ void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags,
+ bool trusted);
void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
@@ -242,7 +243,7 @@ struct amdgpu_ring {
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as)
(r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
-#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
+#define amdgpu_ring_emit_cntxcntl(r, d, s) (r)->funcs->emit_cntxcntl((r), (d),
(s))
#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r),
(d), (v), (m))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 18f741b..06698c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4514,7 +4514,9 @@ static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring
*ring)
amdgpu_ring_write(ring, 0);
}
-static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t
flags)
+static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
+uint32_t flags,
+bool trusted)
{
uint32_t dw2 = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 8c27c30..b4af1b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2972,7 +2972,8 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct
amdgpu_device *adev)
return clock;
}
-static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags,
+ bool trusted)
{
if (flags & AMDGPU_HAVE_CTX_SWITCH)
gfx_v6_0_ring_emit_vgt_flush(ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 48796b68..c08f5c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2309,7 +2309,8 @@ static void gfx_v7_0_ring_emit_ib_compute(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, control);
}
-static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags,
+ bool trusted)
{
uint32_t dw2 = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 98e5aa8..d3a23fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6393,7 +6393,8 @@ static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
amdgpu_ring_write(ring, 0);
}
[PATCH 06/14] drm/amdgpu: add function to check tmz capability (v4)
Add a function to check tmz capability with kernel parameter and ASIC type.
v2: use a per device tmz variable instead of global amdgpu_tmz.
v3: refine the comments for the function. (Luben)
v4: add amdgpu_tmz.c/h for future use.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c| 49 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h| 3 ++
4 files changed, 56 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 91369c8..270ce82 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -55,7 +55,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o
amdgpu_vm_cpu.o \
amdgpu_vm_sdma.o amdgpu_pmu.o amdgpu_discovery.o amdgpu_ras_eeprom.o
amdgpu_nbio.o \
- amdgpu_umc.o smu_v11_0_i2c.o
+ amdgpu_umc.o smu_v11_0_i2c.o amdgpu_tmz.o
amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2535db2..e376fe5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -63,6 +63,7 @@
#include "amdgpu_xgmi.h"
#include "amdgpu_ras.h"
#include "amdgpu_pmu.h"
+#include "amdgpu_tmz.h"
#include
@@ -1032,6 +1033,8 @@ static int amdgpu_device_check_arguments(struct
amdgpu_device *adev)
adev->firmware.load_type = amdgpu_ucode_get_load_type(adev,
amdgpu_fw_load_type);
+ adev->tmz.enabled = amdgpu_is_tmz(adev);
+
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
new file mode 100644
index 000..14a5500
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include "amdgpu.h"
+#include "amdgpu_tmz.h"
+
+
+/**
+ * amdgpu_is_tmz - validate trust memory zone
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Return true if @dev supports trusted memory zones (TMZ), and return false if
+ * @dev does not support TMZ.
+ */
+bool amdgpu_is_tmz(struct amdgpu_device *adev)
+{
+ if (!amdgpu_tmz)
+ return false;
+
+ if (adev->asic_type < CHIP_RAVEN || adev->asic_type == CHIP_ARCTURUS) {
+ dev_warn(adev->dev, "doesn't support trusted memory zones
(TMZ)\n");
+ return false;
+ }
+
+ dev_info(adev->dev, "TMZ feature is enabled\n");
+
+ return true;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
index 24bbbc2..28e0517 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
@@ -33,4 +33,7 @@ struct amdgpu_tmz {
boolenabled;
};
+
+extern bool amdgpu_is_tmz(struct amdgpu_device *adev);
+
#endif
--
2.7.4
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[PATCH 04/14] drm/amdgpu: add tmz feature parameter (v2)
This patch adds tmz parameter to enable/disable the feature in the amdgpu kernel
module. Nomally, by default, it should be auto (rely on the hardware
capability).
But right now, it need to set "off" to avoid breaking other developers'
work because it's not totally completed.
Will set "auto" till the feature is stable and completely verified.
v2: add "auto" option for future use.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a1516a3..930643c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -172,6 +172,7 @@ extern int amdgpu_force_asic_type;
#ifdef CONFIG_HSA_AMD
extern int sched_policy;
#endif
+extern int amdgpu_tmz;
#ifdef CONFIG_DRM_AMDGPU_SI
extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 6978d17..606f1d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -145,6 +145,7 @@ int amdgpu_discovery = -1;
int amdgpu_mes = 0;
int amdgpu_noretry = 1;
int amdgpu_force_asic_type = -1;
+int amdgpu_tmz = 0;
struct amdgpu_mgpu_info mgpu_info = {
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@@ -752,6 +753,16 @@ uint amdgpu_dm_abm_level = 0;
MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight
reduction level) ");
module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
+/**
+ * DOC: tmz (int)
+ * Trust Memory Zone (TMZ) is a method to protect the contents being written to
+ * and read from memory.
+ *
+ * The default value: 0 (off). TODO: change to auto till it is completed.
+ */
+MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 =
on)");
+module_param_named(tmz, amdgpu_tmz, int, 0444);
+
static const struct pci_device_id pciidlist[] = {
#ifdef CONFIG_DRM_AMDGPU_SI
{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
--
2.7.4
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[PATCH 07/14] drm/ttm: add helper to get buffer object with ttm_mem_reg
This patch is to add a helper to get corresponding buffer object with a pointer
to a struct ttm_mem_reg.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
include/drm/ttm/ttm_bo_driver.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index d69121c..264e6c3 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -786,6 +786,19 @@ static inline void ttm_bo_unreserve(struct
ttm_buffer_object *bo)
reservation_object_unlock(bo->resv);
}
+/**
+ * ttm_mem_reg_to_bo
+ *
+ * @mem: A pointer to a struct ttm_mem_reg.
+ *
+ * Returns corresponding buffer object of the @mem.
+ */
+static inline
+struct ttm_buffer_object *ttm_mem_reg_to_bo(struct ttm_mem_reg *mem)
+{
+ return container_of(mem, struct ttm_buffer_object, mem);
+}
+
/*
* ttm_bo_util.c
*/
--
2.7.4
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[PATCH 05/14] drm/amdgpu: add amdgpu_tmz data structure
This patch to add amdgpu_tmz structure which stores all tmz related fields.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h | 36 +
2 files changed, 41 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 930643c..697e8e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -89,6 +89,7 @@
#include "amdgpu_mes.h"
#include "amdgpu_umc.h"
#include "amdgpu_mmhub.h"
+#include "amdgpu_tmz.h"
#define MAX_GPU_INSTANCE 16
@@ -916,6 +917,9 @@ struct amdgpu_device {
boolenable_mes;
struct amdgpu_mes mes;
+ /* tmz */
+ struct amdgpu_tmz tmz;
+
struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
int num_ip_blocks;
struct mutexmn_lock;
@@ -927,7 +931,7 @@ struct amdgpu_device {
atomic64_t gart_pin_size;
/* soc15 register offset based on ip, instance and segment */
- uint32_t*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
+ uint32_t*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
const struct amdgpu_df_funcs*df_funcs;
const struct amdgpu_mmhub_funcs *mmhub_funcs;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
new file mode 100644
index 000..24bbbc2
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __AMDGPU_TMZ_H__
+#define __AMDGPU_TMZ_H__
+
+#include "amdgpu.h"
+
+/*
+ * Trust memory zone stuff
+ */
+struct amdgpu_tmz {
+ boolenabled;
+};
+
+#endif
--
2.7.4
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[PATCH 03/14] drm/amdgpu: define the TMZ bit for the PTE
From: Alex Deucher Define the TMZ (encryption) bit in the page table entry (PTE) for Raven and newer asics. Signed-off-by: Alex Deucher Reviewed-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 3352a87..4b5d283 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -53,6 +53,9 @@ struct amdgpu_bo_list_entry; #define AMDGPU_PTE_SYSTEM (1ULL << 1) #define AMDGPU_PTE_SNOOPED (1ULL << 2) +/* RV+ */ +#define AMDGPU_PTE_TMZ (1ULL << 3) + /* VI only */ #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdkfd: fix the missed asic name while inited renoir_device_info
This patch fixes null pointer issue below, I missed to init the asic renior name
while I rebase the patches.
[ 106.004250] BUG: kernel NULL pointer dereference, address:
[ 106.004254] #PF: supervisor read access in kernel mode
[ 106.004256] #PF: error_code(0x) - not-present page
[ 106.004257] PGD 0 P4D 0
[ 106.004261] Oops: [#1] SMP NOPTI
[ 106.004264] CPU: 3 PID: 1422 Comm: modprobe Not tainted 5.2.0-rc1-custom #1
[ 106.004266] Hardware name: AMD Celadon-RN/Celadon-RN, BIOS
WCD9814N_Weekly_19_08_1 08/14/2019
[ 106.004272] RIP: 0010:strncpy+0x12/0x30
[ 106.004274] Code: c1 c0 11 48 c1 c6 15 48 31 d0 48 c1 c2 20 31 c2 89 d0 31 f0
41 5c 5d c3 55 48 85 d2 48 89 f8 48 89 e5 74 1e 48 01 fa 48 89 f9 <44> 0f b6 06
41 80 f8 01 44 88 01 48 83 de ff 48 83 c1 01 48 39 d1
[ 106.004278] RSP: 0018:c092c1fd37a8 EFLAGS: 00010286
[ 106.004281] RAX: 9e943466a28c RBX: 36ed RCX: 9e943466a28c
[ 106.004283] RDX: 9e943466a2ac RSI: RDI: 9e943466a28c
[ 106.004285] RBP: c092c1fd37a8 R08: 9e943d10 R09: 0228
[ 106.004287] R10: 9e94418dc5a8 R11: 9e944746c0d0 R12:
[ 106.004289] R13: 9e943fa1ec00 R14: 9e943466a200 R15: 9e943466a200
[ 106.004291] FS: 7f7a022c5540() GS:9e9447ac()
knlGS:
[ 106.004294] CS: 0010 DS: ES: CR0: 80050033
[ 106.004296] CR2: CR3: 0001ff0b CR4: 00340ee0
[ 106.004298] Call Trace:
[ 106.004382] kfd_topology_add_device+0x150/0x610 [amdgpu]
[ 106.004445] kgd2kfd_device_init+0x2e0/0x4f0 [amdgpu]
[ 106.004509] amdgpu_amdkfd_device_init+0x14c/0x1b0 [amdgpu]
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index a2fe0cb..f329b82 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -353,6 +353,7 @@ static const struct kfd_device_info arcturus_device_info = {
static const struct kfd_device_info renoir_device_info = {
.asic_family = CHIP_RENOIR,
+ .asic_name = "renoir",
.max_pasid_bits = 16,
.max_no_of_hqd = 24,
.doorbell_size = 8,
--
2.7.4
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RE: [PATCH] drm/amdgpu: fix build error without CONFIG_HSA_AMD
> -Original Message-
> From: S, Shirish
> Sent: Tuesday, September 10, 2019 3:54 PM
> To: Deucher, Alexander ; Koenig, Christian
> ; Huang, Ray
> Cc: amd-gfx@lists.freedesktop.org; S, Shirish
> Subject: [PATCH] drm/amdgpu: fix build error without CONFIG_HSA_AMD
>
> If CONFIG_HSA_AMD is not set, build fails:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.o: In function
> `amdgpu_device_ip_early_init':
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626: undefined
> reference to `sched_policy'
>
> Use CONFIG_HSA_AMD to guard this.
>
> Fixes: 1abb680ad371 ("drm/amdgpu: disable gfxoff while use no H/W
> scheduling policy")
>
> Signed-off-by: Shirish S
+ Felix for his awareness.
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 1030cb30720c..a1516a3ae9a8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -169,7 +169,9 @@ extern int amdgpu_discovery; extern int
> amdgpu_mes; extern int amdgpu_noretry; extern int
> amdgpu_force_asic_type;
> +#ifdef CONFIG_HSA_AMD
> extern int sched_policy;
> +#endif
>
> #ifdef CONFIG_DRM_AMDGPU_SI
> extern int amdgpu_si_support;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index bd423dd64e18..2535db27f821 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1623,7 +1623,11 @@ static int amdgpu_device_ip_early_init(struct
> amdgpu_device *adev)
> }
>
> adev->pm.pp_feature = amdgpu_pp_feature_mask;
> - if (amdgpu_sriov_vf(adev) || sched_policy ==
> KFD_SCHED_POLICY_NO_HWS)
> + if (amdgpu_sriov_vf(adev)
> + #ifdef CONFIG_HSA_AMD
> + || sched_policy == KFD_SCHED_POLICY_NO_HWS
> + #endif
> + )
> adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>
> for (i = 0; i < adev->num_ip_blocks; i++) {
> --
> 2.20.1
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[PATCH v2 01/10] drm/amdkfd: add renoir cache info for CRAT (v2)
Renoir's cache info should be the same with raven and carrizo's.
v2: fix missed "break"
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 66387ca..b115a01 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -138,6 +138,7 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
/* TODO - check & update Vega10 cache details */
#define vega10_cache_info carrizo_cache_info
#define raven_cache_info carrizo_cache_info
+#define renoir_cache_info carrizo_cache_info
/* TODO - check & update Navi10 cache details */
#define navi10_cache_info carrizo_cache_info
@@ -670,6 +671,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
pcache_info = raven_cache_info;
num_of_cache_types = ARRAY_SIZE(raven_cache_info);
break;
+ case CHIP_RENOIR:
+ pcache_info = renoir_cache_info;
+ num_of_cache_types = ARRAY_SIZE(renoir_cache_info);
+ break;
case CHIP_NAVI10:
pcache_info = navi10_cache_info;
num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
--
2.7.4
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[PATCH v2 02/10] drm/amdkfd: add renoir kfd device info (v2)
This patch inits renoir kfd device info, so we treat renoir as "dgpu"
(bypass iommu v2). Will enable needs_iommu_device till renoir iommu is ready.
v2: rebase and align the drm-next
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 267eb2e..c5120f3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -351,6 +351,23 @@ static const struct kfd_device_info arcturus_device_info =
{
.num_sdma_queues_per_engine = 8,
};
+static const struct kfd_device_info renoir_device_info = {
+ .asic_family = CHIP_RENOIR,
+ .max_pasid_bits = 16,
+ .max_no_of_hqd = 24,
+ .doorbell_size = 8,
+ .ih_ring_entry_size = 8 * sizeof(uint32_t),
+ .event_interrupt_class = &event_interrupt_class_v9,
+ .num_of_watch_points = 4,
+ .mqd_size_aligned = MQD_SIZE_ALIGNED,
+ .supports_cwsr = true,
+ .needs_iommu_device = false,
+ .needs_pci_atomics = false,
+ .num_sdma_engines = 1,
+ .num_xgmi_sdma_engines = 0,
+ .num_sdma_queues_per_engine = 2,
+};
+
static const struct kfd_device_info navi10_device_info = {
.asic_family = CHIP_NAVI10,
.asic_name = "navi10",
@@ -384,6 +401,7 @@ static const struct kfd_device_info
*kfd_supported_devices[][2] = {
[CHIP_VEGA12] = {&vega12_device_info, NULL},
[CHIP_VEGA20] = {&vega20_device_info, NULL},
[CHIP_RAVEN] = {&raven_device_info, NULL},
+ [CHIP_RENOIR] = {&renoir_device_info, NULL},
[CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
[CHIP_NAVI10] = {&navi10_device_info, NULL},
};
--
2.7.4
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Re: [PATCH 1/1] drm/amdgpu: Disable retry faults in VMID0
On Thu, Sep 05, 2019 at 07:31:11AM +0800, Kuehling, Felix wrote: > There is no point retrying page faults in VMID0. Those faults are > always fatal. > > Signed-off-by: Felix Kuehling Thanks! I have verified it in my platform. Reviewed-and-Tested-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 2 ++ > 5 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > index 6ce37ce77d14..9ec4297e61e5 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > @@ -178,6 +178,8 @@ static void gfxhub_v1_0_enable_system_domain(struct > amdgpu_device *adev) > tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, > + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); > WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); > } > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > index 8b789f750b72..a9238735d361 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > @@ -166,6 +166,8 @@ static void gfxhub_v2_0_enable_system_domain(struct > amdgpu_device *adev) > tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); > tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); > + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, > + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); > WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); > } > > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > index b9d6c0bfa594..4c7e8c64a94e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > @@ -207,6 +207,8 @@ static void mmhub_v1_0_enable_system_domain(struct > amdgpu_device *adev) > tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); > + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, > + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); > WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp); > } > > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c > b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c > index 3542c203c3c8..86ed8cb915a8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c > @@ -152,6 +152,8 @@ static void mmhub_v2_0_enable_system_domain(struct > amdgpu_device *adev) > tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); > + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, > + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); > WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); > } > > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c > b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c > index 0cf7ef44b4b5..657970f9ebfb 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c > @@ -240,6 +240,8 @@ static void mmhub_v9_4_enable_system_domain(struct > amdgpu_device *adev, > hubid * MMHUB_INSTANCE_REGISTER_OFFSET); > tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); > + tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, > + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); > WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL, > hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); > } > -- > 2.17.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
