RE: [PATCH] drm/amd/pm: wait for completion of the EnableGfxImu command
[AMD Official Use Only - General]
Hi Yifan,
-Original Message-
From: Zhang, Yifan
Sent: Tuesday, October 10, 2023 1:31 PM
To: Huang, Tim ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: RE: [PATCH] drm/amd/pm: wait for completion of the EnableGfxImu command
[AMD Official Use Only - General]
> I'm wondering why it is "without waiting" in the first place ? It doesn't
> make sense to continue driver loading if power up GFX fails. Can we apply the
> change regardless of load types ?
The "without waiting" is only for ASIC bringing up. Because of some reason, the
SMU can't response to driver in the GFX powerup stage if use FW backdoor
loading,
It may hang the system if driver try to read the status of the SMU. So, drive
will wait a regular time to let SMU powerup the GFX but not by polling the
response of the command.
Keep this "without waiting" for FW backdoor loading, maybe new ASICs bringing
up need it as well. It will never be used for the normal case
(AMDGPU_FW_LOAD_PSP).
Best Regards,
Tim Huang
-Original Message-
From: Huang, Tim
Sent: Tuesday, October 10, 2023 12:47 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim
Subject: [PATCH] drm/amd/pm: wait for completion of the EnableGfxImu command
Wait for completion of sending the EnableGfxImu message when using the PSP FW
loading.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 8dc683c02a7d..bcb7ab9d2221 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -82,6 +82,8 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000 #define
PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
+#define ENABLE_IMU_ARG_GFXOFF_ENABLE 1
+
static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5}; @@ -2301,11 +2303,17
@@ int smu_v13_0_baco_exit(struct smu_context *smu) int
smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu) {
uint16_t index;
+ struct amdgpu_device *adev = smu->adev;
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ return smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_EnableGfxImu,
+
ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL);
+ }
index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
SMU_MSG_EnableGfxImu);
- /* Param 1 to tell PMFW to enable GFXOFF feature */
- return smu_cmn_send_msg_without_waiting(smu, index, 1);
+ return smu_cmn_send_msg_without_waiting(smu, index,
+ ENABLE_IMU_ARG_GFXOFF_ENABLE);
}
int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
--
2.39.2
RE: [PATCH] drm/amdgpu: add clockgating support for NBIO v7.7.1
[Public]
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
-Original Message-
From: Ma, Li
Sent: Tuesday, October 17, 2023 6:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Yifan ; Huang, Tim ; Ma, Li
Subject: [PATCH] drm/amdgpu: add clockgating support for NBIO v7.7.1
add clockgating support for NBIO ip 7.7.1 and modify if condition.
Signed-off-by: Li Ma
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
index def89379b51a..4df1055e640a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
@@ -254,7 +254,7 @@ static void
nbio_v7_7_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t def, data;
- if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
+ if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
return;
def = data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL); @@ -283,7
+283,7 @@ static void nbio_v7_7_update_medium_grain_light_sleep(struct
amdgpu_device *adev {
uint32_t def, data;
- if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
+ if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
return;
def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2); diff --git
a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index df7462cec6ab..3ab188067d84 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -863,6 +863,7 @@ static int soc21_common_set_clockgating_state(void *handle,
case IP_VERSION(4, 3, 0):
case IP_VERSION(4, 3, 1):
case IP_VERSION(7, 7, 0):
+ case IP_VERSION(7, 7, 1):
adev->nbio.funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
adev->nbio.funcs->update_medium_grain_light_sleep(adev,
--
2.25.1
RE: [PATCH v2] drm/amd: Add a workaround for GFX11 systems that fail to flush TLB
[Public]
Hi Mario,
-Original Message-
From: Limonciello, Mario
Sent: Thursday, December 14, 2023 4:31 AM
To: amd-gfx@lists.freedesktop.org
Cc: Limonciello, Mario ; sta...@vger.kernel.org;
Huang, Tim
Subject: [PATCH v2] drm/amd: Add a workaround for GFX11 systems that fail to
flush TLB
Some systems with MP1 13.0.4 or 13.0.11 have a firmware bug that causes the
first MES packet after resume to fail. Typically this packet is used to flush
the TLB when GART is enabled.
This issue is fixed in newer firmware, but as OEMs may not roll this out to the
field, introduce a workaround that will add an extra dummy read on resume that
the result is discarded.
Cc: sta...@vger.kernel.org # 6.1+
Cc: Tim Huang
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3045
Signed-off-by: Mario Limonciello
---
v1->v2:
* Add a dummy read callback instead and use that.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 19 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 3 +++
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 11 +++
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 8 ++--
4 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 9ddbf1494326..cd5e1a027bdf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -868,6 +868,25 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev,
uint32_t reg,
return r;
}
+void amdgpu_mes_reg_dummy_read(struct amdgpu_device *adev) {
+ struct mes_misc_op_input op_input = {
+ .op = MES_MISC_OP_READ_REG,
+ .read_reg.reg_offset = 0,
+ .read_reg.buffer_addr = adev->mes.read_val_gpu_addr,
+ };
+
+ if (!adev->mes.funcs->misc_op) {
+ DRM_ERROR("mes misc op is not supported!\n");
+ return;
+ }
+
+ adev->mes.silent_errors = true;
+ if (adev->mes.funcs->misc_op(&adev->mes, &op_input))
+ DRM_DEBUG("failed to amdgpu_mes_reg_dummy_read\n");
+ adev->mes.silent_errors = false;
+}
+
int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
uint64_t process_context_addr,
uint32_t spi_gdbg_per_vmid_cntl,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index a27b424ffe00..d208e60c1d99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -135,6 +135,8 @@ struct amdgpu_mes {
/* ip specific functions */
const struct amdgpu_mes_funcs *funcs;
+
+ boolsilent_errors;
};
struct amdgpu_mes_process {
@@ -356,6 +358,7 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device
*adev,
u64 gpu_addr, u64 seq);
uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
+void amdgpu_mes_reg_dummy_read(struct amdgpu_device *adev);
int amdgpu_mes_wreg(struct amdgpu_device *adev,
uint32_t reg, uint32_t val);
int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, diff --git
a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 23d7b548d13f..a2ba45f859ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -960,6 +960,17 @@ static int gmc_v11_0_resume(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
+ case IP_VERSION(13, 0, 4):
+ case IP_VERSION(13, 0, 11):
+ /* avoid a lost packet @ first GFXOFF exit after resume */
+ if ((adev->pm.fw_version & 0x00FF) < 0x004c4900 &&
adev->in_s0ix)
+ amdgpu_mes_reg_dummy_read(adev);
+ break;
+ default:
+ break;
+ }
+
I tried this patch on my device, but it not working. The situation is this
dummy reading not hit the MES timeout error but after that still hit the same
error in the amdgpu_virt_kiq_reg_write_reg_wait. Maybe the failed case is not
just the first GFXOFF exit.
r = gmc_v11_0_hw_init(adev);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 4dfec56e1b7f..71df5cb65485 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -137,8 +137,12 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct
amdgpu_mes *mes,
r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq,
timeout);
if (r < 1) {
- DRM_ERROR("MES failed to response msg=%d\n",
- x_pkt->header.op
RE: [PATCH 18/22 V3] drm/amd/pm: check negtive return for table entries
[AMD Official Use Only - AMD Internal Distribution Only]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: Jesse Zhang
> Sent: Monday, May 13, 2024 4:06 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 18/22 V3] drm/amd/pm: check negtive return for table
> entries
>
> Function hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr)
> returns a negative number
>
> Signed-off-by: Jesse Zhang
> Suggested-by: Tim Huang
> ---
> drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c | 13 -
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
> index f4bd8e9357e2..18f00038d844 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
> @@ -30,9 +30,8 @@ int psm_init_power_state_table(struct pp_hwmgr
> *hwmgr) {
> int result;
> unsigned int i;
> - unsigned int table_entries;
> struct pp_power_state *state;
> - int size;
> + int size, table_entries;
>
> if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
> return 0;
> @@ -40,15 +39,19 @@ int psm_init_power_state_table(struct pp_hwmgr
> *hwmgr)
> if (hwmgr->hwmgr_func->get_power_state_size == NULL)
> return 0;
>
> - hwmgr->num_ps = table_entries =
> hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
> + table_entries =
> hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
>
> - hwmgr->ps_size = size =
> hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
> + size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
> sizeof(struct pp_power_state);
>
> - if (table_entries == 0 || size == 0) {
> + if (table_entries <= 0 || size == 0) {
> pr_warn("Please check whether power state management is
> supported on this asic\n");
> + hwmgr->num_ps = 0;
> + hwmgr->ps_size = 0;
> return 0;
> }
> + hwmgr->num_ps = table_entries;
> + hwmgr->ps_size = size;
>
> hwmgr->ps = kcalloc(table_entries, size, GFP_KERNEL);
> if (hwmgr->ps == NULL)
> --
> 2.25.1
RE: [PATCH 4/4] drm/admgpu: fix dereferencing null pointer context
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Jesse,
> -Original Message-
> From: amd-gfx On Behalf Of Jesse
> Zhang
> Sent: Tuesday, May 21, 2024 11:26 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 4/4] drm/admgpu: fix dereferencing null pointer context
>
> When user space sets an invalid ta type, the pointer context will be empty.
> So it need to check the pointer context before using it
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
> index ca5c86e5f7cd..ac1f423dd28f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
> @@ -334,7 +334,7 @@ static ssize_t ta_if_invoke_debugfs_write(struct file
> *fp, const char *buf, size
>
> set_ta_context_funcs(psp, ta_type, &context);
>
> - if (!context->initialized) {
> + if (context && !context->initialized) {
This can help to avoid using the empty pointer context but still needs to
handle the context == NULL case and return an error.
Tim
> dev_err(adev->dev, "TA is not initialized\n");
> ret = -EINVAL;
> goto err_free_shared_buf;
> --
> 2.25.1
RE: [PATCH 4/4 V2] drm/admgpu: fix dereferencing null pointer context
[AMD Official Use Only - AMD Internal Distribution Only]
Series is,
Reviewed-by: Tim Huang
> -Original Message-
> From: Jesse Zhang
> Sent: Tuesday, May 21, 2024 3:18 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 4/4 V2] drm/admgpu: fix dereferencing null pointer context
>
> When user space sets an invalid ta type, the pointer context will be empty.
> So it need to check the pointer context before using it
>
> Signed-off-by: Jesse Zhang
> Suggested-by: Tim Huang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
> index ca5c86e5f7cd..8e8afbd237bc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c
> @@ -334,7 +334,7 @@ static ssize_t ta_if_invoke_debugfs_write(struct file
> *fp, const char *buf, size
>
> set_ta_context_funcs(psp, ta_type, &context);
>
> - if (!context->initialized) {
> + if (!context || !context->initialized) {
> dev_err(adev->dev, "TA is not initialized\n");
> ret = -EINVAL;
> goto err_free_shared_buf;
> --
> 2.25.1
RE: \'--?J;/. [ [PATCH] drm/amd: Fix shutdown (again) on some SMU v13.0.4/11 platforms
[Public]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: amd-gfx On Behalf Of Mario
> Limonciello
> Sent: Sunday, May 26, 2024 8:59 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Limonciello, Mario ; lectrode
> ; sta...@vger.kernel.org;
> regressi...@lists.linux.dev
> Subject: \'--?J;/. [ [PATCH] drm/amd: Fix shutdown (again) on some SMU
> v13.0.4/11 platforms
>
> commit cd94d1b182d2 ("dm/amd/pm: Fix problems with reboot/shutdown
> for some SMU 13.0.4/13.0.11 users") attempted to fix shutdown issues that
> were reported since commit 31729e8c21ec ("drm/amd/pm: fixes a random
> hang in S4 for SMU v13.0.4/11") but caused issues for some people.
>
> Adjust the workaround flow to properly only apply in the S4 case:
> -> For shutdown go through SMU_MSG_PrepareMp1ForUnload For S4 go
> through
> -> SMU_MSG_GfxDeviceDriverReset and
>SMU_MSG_PrepareMp1ForUnload
>
> Reported-and-tested-by: lectrode
> Closes: https://github.com/void-linux/void-packages/issues/50417
> Cc: sta...@vger.kernel.org
> Fixes: cd94d1b182d2 ("dm/amd/pm: Fix problems with reboot/shutdown for
> some SMU 13.0.4/13.0.11 users")
> Signed-off-by: Mario Limonciello
> ---
> Cc: regressi...@lists.linux.dev
> ---
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 20 ++
> -
> 1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
> index 4abfcd32747d..c7ab0d7027d9 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
> @@ -226,15 +226,17 @@ static int
> smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
> struct amdgpu_device *adev = smu->adev;
> int ret = 0;
>
> - if (!en && adev->in_s4) {
> - /* Adds a GFX reset as workaround just before sending the
> - * MP1_UNLOAD message to prevent GC/RLC/PMFW from
> entering
> - * an invalid state.
> - */
> - ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_GfxDeviceDriverReset,
> - SMU_RESET_MODE_2,
> NULL);
> - if (ret)
> - return ret;
> + if (!en && !adev->in_s0ix) {
> + if (adev->in_s4) {
> + /* Adds a GFX reset as workaround just before
> sending the
> + * MP1_UNLOAD message to prevent GC/RLC/PMFW
> from entering
> + * an invalid state.
> + */
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_GfxDeviceDriverReset,
> +
> SMU_RESET_MODE_2, NULL);
> + if (ret)
> + return ret;
> + }
>
> ret = smu_cmn_send_smc_msg(smu,
> SMU_MSG_PrepareMp1ForUnload, NULL);
> }
> --
> 2.43.0
RE: [PATCH] drm/amd/pm: Fix the null pointer dereference for vega10_hwmgr
[Public]
Hi Bob,
> -Original Message-
> From: Bob Zhou
> Sent: Wednesday, May 29, 2024 4:30 PM
> To: amd-gfx@lists.freedesktop.org; Huang, Tim ; Zhang,
> Jesse(Jie)
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Zhou, Bob
> Subject: [PATCH] drm/amd/pm: Fix the null pointer dereference for
> vega10_hwmgr
>
> Check return value and conduct null pointer handling to avoid null pointer
> dereference.
>
> Signed-off-by: Bob Zhou
> ---
> .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 38
> +++
> 1 file changed, 30 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> index 6524d99e5cab..0f94564b4adf 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> @@ -3436,16 +3436,20 @@ static int
> vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
> struct vega10_hwmgr *data = hwmgr->backend;
> const struct phm_set_power_state_input *states =
> (const struct phm_set_power_state_input *)input;
> - const struct vega10_power_state *vega10_ps =
> - cast_const_phw_vega10_power_state(states->pnew_state);
> + const struct vega10_power_state *vega10_ps;
Not revert xmas tree notation if change this.
> struct vega10_single_dpm_table *sclk_table =
> &(data->dpm_table.gfx_table);
> - uint32_t sclk = vega10_ps->performance_levels
> - [vega10_ps->performance_level_count - 1].gfx_clock;
> struct vega10_single_dpm_table *mclk_table =
> &(data->dpm_table.mem_table);
> - uint32_t mclk = vega10_ps->performance_levels
> - [vega10_ps->performance_level_count - 1].mem_clock;
> + uint32_t sclk, mclk;
> uint32_t i;
>
> + vega10_ps = cast_const_phw_vega10_power_state(states->pnew_state);
Why need to change the definition of vega10_ps to two parts? It may be enough
to only add below check and change the sclk and mclk.
> + if (vega10_ps == NULL)
> + return -EINVAL;
> + sclk = vega10_ps->performance_levels
> + [vega10_ps->performance_level_count - 1].gfx_clock;
> + mclk = vega10_ps->performance_levels
> + [vega10_ps->performance_level_count - 1].mem_clock;
> +
> for (i = 0; i < sclk_table->count; i++) {
> if (sclk == sclk_table->dpm_levels[i].value)
> break;
> @@ -3748,10 +3752,13 @@ static int
> vega10_generate_dpm_level_enable_mask(
> struct vega10_hwmgr *data = hwmgr->backend;
> const struct phm_set_power_state_input *states =
> (const struct phm_set_power_state_input *)input;
> - const struct vega10_power_state *vega10_ps =
> - cast_const_phw_vega10_power_state(states->pnew_state);
> + const struct vega10_power_state *vega10_ps;
> int i;
>
> + vega10_ps = cast_const_phw_vega10_power_state(states->pnew_state);
Same question as above, maybe it is enough to only add below check.
Tim Huang
> + if (vega10_ps == NULL)
> + return -EINVAL;
> +
> PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
> "Attempt to Trim DPM States Failed!",
> return -1);
> @@ -5036,6 +5043,9 @@ static int vega10_check_states_equal(struct
> pp_hwmgr *hwmgr,
> vega10_psa = cast_const_phw_vega10_power_state(pstate1);
> vega10_psb = cast_const_phw_vega10_power_state(pstate2);
>
> + if (vega10_psa == NULL || vega10_psb == NULL)
> + return -EINVAL;
> +
> /* If the two states don't even have the same number of performance
> levels
>* they cannot be the same state.
>*/
> @@ -5168,6 +5178,8 @@ static int vega10_set_sclk_od(struct pp_hwmgr
> *hwmgr, uint32_t value)
> return -EINVAL;
>
> vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
> + if (vega10_ps == NULL)
> + return -EINVAL;
>
> vega10_ps->performance_levels
> [vega10_ps->performance_level_count - 1].gfx_clock = @@ -5219,6
> +5231,8 @@ static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t
> value)
> return -EINVAL;
>
> vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
> + if (vega10_ps == NULL)
> + return -EINVAL;
>
> vega10_ps->performance_levels
> [vega10_ps->performance_level_count - 1].mem_clock = @@ -5460,6
> +5474,9 @@
RE: [PATCH v2] drm/amd/pm: Fix the null pointer dereference for vega10_hwmgr
[AMD Official Use Only - AMD Internal Distribution Only] Hi Bob, > -Original Message- > From: Bob Zhou > Sent: Friday, May 31, 2024 2:43 PM > To: amd-gfx@lists.freedesktop.org; Huang, Tim ; Zhang, > Jesse(Jie) > Cc: Deucher, Alexander ; Koenig, Christian > ; Zhou, Bob > Subject: [PATCH v2] drm/amd/pm: Fix the null pointer dereference for > vega10_hwmgr > > Check return value and conduct null pointer handling to avoid null pointer > dereference. > > Signed-off-by: Bob Zhou > --- > .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 19 > +++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > index 6524d99e5cab..68b93a0c16e4 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > @@ -3438,6 +3438,8 @@ static int > vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co > (const struct phm_set_power_state_input *)input; > const struct vega10_power_state *vega10_ps = > cast_const_phw_vega10_power_state(states->pnew_state); > + if (vega10_ps == NULL) > + return -EINVAL; Can't add the check here, your changes for the sclk and mclk in previous versions are still needed. Tim Huang > struct vega10_single_dpm_table *sclk_table = > &(data->dpm_table.gfx_table); > uint32_t sclk = vega10_ps->performance_levels > [vega10_ps->performance_level_count - 1].gfx_clock; @@ > -3752,6 +3754,9 @@ static int vega10_generate_dpm_level_enable_mask( > cast_const_phw_vega10_power_state(states->pnew_state); > int i; > > + if (vega10_ps == NULL) > + return -EINVAL; > + > PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps), > "Attempt to Trim DPM States Failed!", > return -1); > @@ -5035,6 +5040,8 @@ static int vega10_check_states_equal(struct > pp_hwmgr *hwmgr, > > vega10_psa = cast_const_phw_vega10_power_state(pstate1); > vega10_psb = cast_const_phw_vega10_power_state(pstate2); > + if (vega10_psa == NULL || vega10_psb == NULL) > + return -EINVAL; > > /* If the two states don't even have the same number of performance > levels >* they cannot be the same state. > @@ -5168,6 +5175,8 @@ static int vega10_set_sclk_od(struct pp_hwmgr > *hwmgr, uint32_t value) > return -EINVAL; > > vega10_ps = cast_phw_vega10_power_state(&ps->hardware); > + if (vega10_ps == NULL) > + return -EINVAL; > > vega10_ps->performance_levels > [vega10_ps->performance_level_count - 1].gfx_clock = @@ -5219,6 > +5228,8 @@ static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t > value) > return -EINVAL; > > vega10_ps = cast_phw_vega10_power_state(&ps->hardware); > + if (vega10_ps == NULL) > + return -EINVAL; > > vega10_ps->performance_levels > [vega10_ps->performance_level_count - 1].mem_clock = @@ -5460,6 > +5471,9 @@ static void vega10_odn_update_power_state(struct pp_hwmgr > *hwmgr) > return; > > vega10_ps = cast_phw_vega10_power_state(&ps->hardware); > + if (vega10_ps == NULL) > + return; > + > max_level = vega10_ps->performance_level_count - 1; > > if (vega10_ps->performance_levels[max_level].gfx_clock != @@ -5482,6 > +5496,9 @@ static void vega10_odn_update_power_state(struct pp_hwmgr > *hwmgr) > > ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + > hwmgr->ps_size * (hwmgr->num_ps - 1)); > vega10_ps = cast_phw_vega10_power_state(&ps->hardware); > + if (vega10_ps == NULL) > + return; > + > max_level = vega10_ps->performance_level_count - 1; > > if (vega10_ps->performance_levels[max_level].gfx_clock != @@ -5672,6 > +5689,8 @@ static int vega10_get_performance_level(struct pp_hwmgr > *hwmgr, const struct pp_ > return -EINVAL; > > vega10_ps = cast_const_phw_vega10_power_state(state); > + if (vega10_ps == NULL) > + return -EINVAL; > > i = index > vega10_ps->performance_level_count - 1 ? > vega10_ps->performance_level_count - 1 : index; > -- > 2.34.1
RE: [PATCH v3] drm/amd/pm: Fix the null pointer dereference for vega10_hwmgr
[Public]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: Bob Zhou
> Sent: Friday, May 31, 2024 3:01 PM
> To: amd-gfx@lists.freedesktop.org; Huang, Tim ; Zhang,
> Jesse(Jie)
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Zhou, Bob
> Subject: [PATCH v3] drm/amd/pm: Fix the null pointer dereference for
> vega10_hwmgr
>
> Check return value and conduct null pointer handling to avoid null pointer
> dereference.
>
> Signed-off-by: Bob Zhou
> ---
> .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 29
> ---
> 1 file changed, 25 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> index 6524d99e5cab..6e717ddbb029 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> @@ -3439,13 +3439,17 @@ static int
> vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
> const struct vega10_power_state *vega10_ps =
> cast_const_phw_vega10_power_state(states->pnew_state);
> struct vega10_single_dpm_table *sclk_table =
> &(data->dpm_table.gfx_table);
> - uint32_t sclk = vega10_ps->performance_levels
> - [vega10_ps->performance_level_count - 1].gfx_clock;
> struct vega10_single_dpm_table *mclk_table =
> &(data->dpm_table.mem_table);
> - uint32_t mclk = vega10_ps->performance_levels
> - [vega10_ps->performance_level_count - 1].mem_clock;
> + uint32_t sclk, mclk;
> uint32_t i;
>
> + if (vega10_ps == NULL)
> + return -EINVAL;
> + sclk = vega10_ps->performance_levels
> + [vega10_ps->performance_level_count - 1].gfx_clock;
> + mclk = vega10_ps->performance_levels
> + [vega10_ps->performance_level_count - 1].mem_clock;
> +
> for (i = 0; i < sclk_table->count; i++) {
> if (sclk == sclk_table->dpm_levels[i].value)
> break;
> @@ -3752,6 +3756,9 @@ static int vega10_generate_dpm_level_enable_mask(
> cast_const_phw_vega10_power_state(states->pnew_state);
> int i;
>
> + if (vega10_ps == NULL)
> + return -EINVAL;
> +
> PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
> "Attempt to Trim DPM States Failed!",
> return -1);
> @@ -5035,6 +5042,8 @@ static int vega10_check_states_equal(struct
> pp_hwmgr *hwmgr,
>
> vega10_psa = cast_const_phw_vega10_power_state(pstate1);
> vega10_psb = cast_const_phw_vega10_power_state(pstate2);
> + if (vega10_psa == NULL || vega10_psb == NULL)
> + return -EINVAL;
>
> /* If the two states don't even have the same number of performance
> levels
>* they cannot be the same state.
> @@ -5168,6 +5177,8 @@ static int vega10_set_sclk_od(struct pp_hwmgr
> *hwmgr, uint32_t value)
> return -EINVAL;
>
> vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
> + if (vega10_ps == NULL)
> + return -EINVAL;
>
> vega10_ps->performance_levels
> [vega10_ps->performance_level_count - 1].gfx_clock = @@ -5219,6
> +5230,8 @@ static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t
> value)
> return -EINVAL;
>
> vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
> + if (vega10_ps == NULL)
> + return -EINVAL;
>
> vega10_ps->performance_levels
> [vega10_ps->performance_level_count - 1].mem_clock = @@ -5460,6
> +5473,9 @@ static void vega10_odn_update_power_state(struct pp_hwmgr
> *hwmgr)
> return;
>
> vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
> + if (vega10_ps == NULL)
> + return;
> +
> max_level = vega10_ps->performance_level_count - 1;
>
> if (vega10_ps->performance_levels[max_level].gfx_clock != @@ -5482,6
> +5498,9 @@ static void vega10_odn_update_power_state(struct pp_hwmgr
> *hwmgr)
>
> ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) +
> hwmgr->ps_size * (hwmgr->num_ps - 1));
> vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
> + if (vega10_ps == NULL)
> + return;
> +
> max_level = vega10_ps->performance_level_count - 1;
>
> if (vega10_ps->performance_levels[max_level].gfx_clock != @@ -5672,6
> +5691,8 @@ static int vega10_get_performance_level(struct pp_hwmgr
> *hwmgr, const struct pp_
> return -EINVAL;
>
> vega10_ps = cast_const_phw_vega10_power_state(state);
> + if (vega10_ps == NULL)
> + return -EINVAL;
>
> i = index > vega10_ps->performance_level_count - 1 ?
> vega10_ps->performance_level_count - 1 : index;
> --
> 2.34.1
RE: [PATCH 01/12] drm/amd/pm: remove dead code in si_convert_power_level_to_smc
[Public]
Hi Jesse,
> -Original Message-
> From: Jesse Zhang
> Sent: Monday, June 3, 2024 4:46 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Kuehling, Felix ;
> Huang, Tim ; Zhang, Jesse(Jie)
> ; Zhang, Jesse(Jie)
> Subject: [PATCH 01/12] drm/amd/pm: remove dead code in
> si_convert_power_level_to_smc
>
> Since gmc_pg is false, setting mcFlags with SISLANDS_SMC_MC_PG_EN
> cannot be reach.
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> index 68ac01a8bc3a..a18f75a6d480 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> @@ -5487,9 +5487,6 @@ static int si_convert_power_level_to_smc(struct
> amdgpu_device *adev,
> (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
> (adev->pm.dpm.new_active_crtc_count <= 2)) {
> level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
> -
> - if (gmc_pg)
> - level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
If remove this, the pmc_pg should never be used, maybe remove the definition of
"bool gmc_pg = false" as well?
Tim Huang
> }
>
> if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
> --
> 2.25.1
RE: [PATCH 04/12] drm/amdgpu: remove dead code in atom_get_src_int
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Jesse,
> -Original Message-
> From: Jesse Zhang
> Sent: Monday, June 3, 2024 4:47 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Kuehling, Felix ;
> Huang, Tim ; Zhang, Jesse(Jie)
> ; Zhang, Jesse(Jie)
> Subject: [PATCH 04/12] drm/amdgpu: remove dead code in atom_get_src_int
>
> Since the range of align is 0~7, the expression is: align = (attr >> 3) & 7.
> In the case of ATOM_ARG_IMM, the code cannot reach the default case.
> So there is no need for "break".
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/atom.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c
> b/drivers/gpu/drm/amd/amdgpu/atom.c
> index d552e013354c..c660e4a663ef 100644
> --- a/drivers/gpu/drm/amd/amdgpu/atom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/atom.c
> @@ -320,7 +320,6 @@ static uint32_t atom_get_src_int(atom_exec_context
> *ctx, uint8_t attr,
> DEBUG("IMM 0x%02X\n", val);
> return val;
> }
> - break;
This should have new statement may fall through warning if remove the break
here?
Tim Huang
> case ATOM_ARG_PLL:
> idx = U8(*ptr);
> (*ptr)++;
> --
> 2.25.1
RE: [PATCH 05/12] drm/amd/pm: remove dead code in navi10_emit_clk_levels and navi10_print_clk_levels
[Public] This patch is, Reviewed-by: Tim Huang > -Original Message- > From: Jesse Zhang > Sent: Monday, June 3, 2024 4:48 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Kuehling, Felix ; > Huang, Tim ; Zhang, Jesse(Jie) > ; Zhang, Jesse(Jie) > Subject: [PATCH 05/12] drm/amd/pm: remove dead code in > navi10_emit_clk_levels and navi10_print_clk_levels > > Since the range of the varibable i is 0 - 3. > So execution cannot reach this statement: default. > > Signed-off-by: Jesse Zhang > --- > drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 > 1 file changed, 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > index cf556f1b5ed1..076620fa3ef5 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > @@ -1389,8 +1389,6 @@ static int navi10_emit_clk_levels(struct > smu_context *smu, > case 2: > curve_settings = &od_table->GfxclkFreq3; > break; > - default: > - break; > } > *offset += sysfs_emit_at(buf, *offset, > "%d: %uMHz %umV\n", > i, curve_settings[0], > @@ -1594,8 +1592,6 @@ static int navi10_print_clk_levels(struct > smu_context *smu, > case 2: > curve_settings = &od_table->GfxclkFreq3; > break; > - default: > - break; > } > size += sysfs_emit_at(buf, size, > "%d: %uMHz %umV\n", > i, curve_settings[0], > -- > 2.25.1
RE: [PATCH 4/12 V2] drm/amdgpu: remove dead code in atom_get_src_int
[Public]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: Jesse Zhang
> Sent: Wednesday, June 5, 2024 4:34 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 4/12 V2] drm/amdgpu: remove dead code in
> atom_get_src_int
>
> Since the range of align is 0~7, the expression is: align = (attr >> 3) & 7.
> In the case of ATOM_ARG_IMM, the code cannot reach the default case.
> So there is no need for "break".
>
> Signed-off-by: Jesse Zhang
> Suggested-by: Tim Huang
> ---
> drivers/gpu/drm/amd/amdgpu/atom.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c
> b/drivers/gpu/drm/amd/amdgpu/atom.c
> index d552e013354c..09715b506468 100644
> --- a/drivers/gpu/drm/amd/amdgpu/atom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/atom.c
> @@ -301,7 +301,7 @@ static uint32_t atom_get_src_int(atom_exec_context
> *ctx, uint8_t attr,
> (*ptr) += 4;
> if (print)
> DEBUG("IMM 0x%08X\n", val);
> - return val;
> + break;
> case ATOM_SRC_WORD0:
> case ATOM_SRC_WORD8:
> case ATOM_SRC_WORD16:
> @@ -309,7 +309,7 @@ static uint32_t atom_get_src_int(atom_exec_context
> *ctx, uint8_t attr,
> (*ptr) += 2;
> if (print)
> DEBUG("IMM 0x%04X\n", val);
> - return val;
> + break;
> case ATOM_SRC_BYTE0:
> case ATOM_SRC_BYTE8:
> case ATOM_SRC_BYTE16:
> @@ -318,9 +318,9 @@ static uint32_t atom_get_src_int(atom_exec_context
> *ctx, uint8_t attr,
> (*ptr)++;
> if (print)
> DEBUG("IMM 0x%02X\n", val);
> - return val;
> + break;
> }
> - break;
> + return val;
> case ATOM_ARG_PLL:
> idx = U8(*ptr);
> (*ptr)++;
> --
> 2.25.1
RE: [PATCH 1/12 V2] drm/amd/pm: remove dead code in si_convert_power_level_to_smc
[Public]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: Jesse Zhang
> Sent: Wednesday, June 5, 2024 4:34 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 1/12 V2] drm/amd/pm: remove dead code in
> si_convert_power_level_to_smc
>
> Since gmc_pg is false, setting mcFlags with SISLANDS_SMC_MC_PG_EN
> cannot be reach.
>
> Signed-off-by: Jesse Zhang
> Suggested-by: Tim Huang
> ---
> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> index 68ac01a8bc3a..f324a8ef8032 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> @@ -5467,7 +5467,6 @@ static int si_convert_power_level_to_smc(struct
> amdgpu_device *adev,
> int ret;
> bool dll_state_on;
> u16 std_vddc;
> - bool gmc_pg = false;
>
> if (eg_pi->pcie_performance_request &&
> (si_pi->force_pcie_gen != SI_PCIE_GEN_INVALID)) @@ -5487,9
> +5486,6 @@ static int si_convert_power_level_to_smc(struct amdgpu_device
> *adev,
> (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
> (adev->pm.dpm.new_active_crtc_count <= 2)) {
> level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
> -
> - if (gmc_pg)
> - level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
> }
>
> if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
> --
> 2.25.1
RE: [PATCH] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Li,
> -Original Message-
> From: Ma, Li
> Sent: Monday, July 1, 2024 4:23 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
> ; Huang, Tim ; Ma, Li
>
> Subject: [PATCH] drm/amd/swsmu: enable more Pstates profile levels for SMU
> v14.0.0 and v14.0.1
>
> This patch enables following UMD stable Pstates profile levels for
> power_dpm_force_performance_level interface.
>
> - profile_peak
> - profile_min_mclk
> - profile_min_sclk
> - profile_standard
>
> Signed-off-by: Li Ma
> ---
> .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 150
> --
> 1 file changed, 137 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> index 18abfbd6d059..d999e3b23173 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> @@ -65,6 +65,10 @@
>
> #define SMU_MALL_PG_CONFIG_DEFAULT
> SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
>
> +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
> +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
> +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
> +
> #define FEATURE_MASK(feature) (1ULL << feature) #define
> SMC_DPM_FEATURE ( \
> FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -723,10 +727,10 @@
> static int smu_v14_0_common_get_dpm_freq_by_index(struct smu_context
> *smu,
> uint32_t dpm_level,
> uint32_t *freq)
> {
> - if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> 0))
> - smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> freq);
> - else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14,
> 0, 1))
> + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> 1))
> smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> freq);
> + else
> + smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> freq);
>
> return 0;
> }
Does this conflict with the ongoing commit drm/amd/pm: smu v14.0.4 reuse smu
v14.0.0 dpmtable ?
Tim
> @@ -818,9 +822,11 @@ static int
> smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -855,7 +861,7 @@ static int
> smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -936,9 +942,11 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -969,7 +977,7 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -999,10 +1007,10 @@ static int
> smu_v14_0_common_get_dpm_ultimate_freq(struct smu_context *smu,
> uint32_t *min,
>
RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Li,
> -Original Message-
> From: Ma, Li
> Sent: Monday, July 1, 2024 6:44 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
> ; Huang, Tim ; Ma, Li
>
> Subject: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for
> SMU v14.0.0 and v14.0.1
>
> This patch enables following UMD stable Pstates profile levels for
> power_dpm_force_performance_level interface.
>
> - profile_peak
> - profile_min_mclk
> - profile_min_sclk
> - profile_standard
>
> Signed-off-by: Li Ma
> ---
> .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 138
> +-
> 1 file changed, 131 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> index 3a9d58c036ea..72fca481dec1 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> @@ -65,6 +65,10 @@
>
> #define SMU_MALL_PG_CONFIG_DEFAULT
> SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
>
> +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
> +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
> +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
> +
> #define FEATURE_MASK(feature) (1ULL << feature) #define
> SMC_DPM_FEATURE ( \
> FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -818,9 +822,11 @@
> static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -855,7 +861,7 @@ static int
> smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -936,9 +942,11 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -969,7 +977,7 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -1268,13 +1276,67 @@ static int smu_v14_0_0_force_clk_levels(struct
> smu_context *smu,
> return ret;
> }
>
> -static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
> +static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context
> *smu,
> + enum amd_dpm_forced_level level,
> + enum smu_clk_type clk_type,
> + uint32_t *min_clk,
> + uint32_t *max_clk)
> +{
> + uint32_t clk_limit = 0;
> + int ret = 0;
> +
> + switch (clk_type) {
> + case SMU_GFXCLK:
> + case SMU_SCLK:
> + clk_limit = SMU_14_0_0_UMD_PSTATE_GFXCLK;
> + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> + smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK,
> NULL, &clk_limit);
> + else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
> + smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK,
> &clk_limit, NULL);
> + break;
> + case SMU_SOCCLK:
&
RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only] Hi Li, > -Original Message- > From: Ma, Li > Sent: Monday, July 1, 2024 9:14 PM > To: Huang, Tim ; amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Zhang, Yifan > > Subject: RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels > for SMU v14.0.0 and v14.0.1 > > [AMD Official Use Only - AMD Internal Distribution Only] > > Hi Tim, > > > -----Original Message- > > From: Huang, Tim > > Sent: Monday, July 1, 2024 7:32 PM > > To: Ma, Li ; amd-gfx@lists.freedesktop.org > > Cc: Deucher, Alexander ; Zhang, Yifan > > > > Subject: RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile > > levels for SMU v14.0.0 and v14.0.1 > > > > [AMD Official Use Only - AMD Internal Distribution Only] > > > > Hi Li, > > > > > -Original Message- > > > From: Ma, Li > > > Sent: Monday, July 1, 2024 6:44 PM > > > To: amd-gfx@lists.freedesktop.org > > > Cc: Deucher, Alexander ; Zhang, Yifan > > > ; Huang, Tim ; Ma, Li > > > > > > Subject: [PATCH v2] drm/amd/swsmu: enable more Pstates profile > > > levels for SMU v14.0.0 and v14.0.1 > > > > > > This patch enables following UMD stable Pstates profile levels for > > > power_dpm_force_performance_level interface. > > > > > > - profile_peak > > > - profile_min_mclk > > > - profile_min_sclk > > > - profile_standard > > > > > > Signed-off-by: Li Ma > > > --- > > > .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 138 > > > +- > > > 1 file changed, 131 insertions(+), 7 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > > b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > > index 3a9d58c036ea..72fca481dec1 100644 > > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > > @@ -65,6 +65,10 @@ > > > > > > #define SMU_MALL_PG_CONFIG_DEFAULT > > > SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON > > > > > > +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700 > > > +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678 > > > +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800 > > > + > > > #define FEATURE_MASK(feature) (1ULL << feature) #define > > > SMC_DPM_FEATURE ( \ > > > FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -818,9 +822,11 > @@ > > > static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu, > > > break; > > > case SMU_MCLK: > > > case SMU_UCLK: > > > - case SMU_FCLK: > > > max_dpm_level = 0; > > > break; > > > + case SMU_FCLK: > > > + max_dpm_level = > clk_table->NumFclkLevelsEnabled - 1; > > > + break; > > > case SMU_SOCCLK: > > > max_dpm_level = > clk_table->NumSocClkLevelsEnabled - 1; > > > break; > > > @@ -855,7 +861,7 @@ static int > > > smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu, > > > min_dpm_level = > clk_table->NumMemPstatesEnabled - 1; > > > break; > > > case SMU_FCLK: > > > - min_dpm_level = > clk_table->NumFclkLevelsEnabled - 1; > > > + min_dpm_level = 0; > > > break; > > > case SMU_SOCCLK: > > > min_dpm_level = 0; @@ -936,9 +942,11 @@ > static > > > int smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu, > > > break; > > > case SMU_MCLK: > > > case SMU_UCLK: > > > - case SMU_FCLK: > > > max_dpm_level = 0; > > > break; > > > + case SMU_FCLK: > > > + max_dpm_level = > clk_table->NumFclkLevelsEnabled - 1; > > > + break; > > > case SMU_SOCCLK: > > > max_dpm_level = > clk_table->NumSocClkLevelsEnabled - 1; > > > break; > > > @@ -969,7 +977,7 @@
RE: [PATCH v3] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: Ma, Li
> Sent: Tuesday, July 2, 2024 2:20 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, Tim ; Deucher, Alexander
> ; Zhang, Yifan ; Ma,
> Li
> Subject: [PATCH v3] drm/amd/swsmu: enable more Pstates profile levels for
> SMU v14.0.0 and v14.0.1
>
> V1: This patch enables following UMD stable Pstates profile
> levels for power_dpm_force_performance_level interface.
>
> - profile_peak
> - profile_min_mclk
> - profile_min_sclk
> - profile_standard
>
> V2: Fix conflict with commit "drm/amd/pm: smu v14.0.4 reuse smu v14.0.0
> dpmtable "
>
> V3: Add VCLK1 and DCLK1 support for SMU V14.0.1
> And avoid to set VCLK1 and DCLK1 for SMU v14.0.0
>
> Signed-off-by: Li Ma
> ---
> .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 152
> --
> 1 file changed, 142 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> index 3a9d58c036ea..5d47d58944f6 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> @@ -65,6 +65,10 @@
>
> #define SMU_MALL_PG_CONFIG_DEFAULT
> SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
>
> +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
> +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
> +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
> +
> #define FEATURE_MASK(feature) (1ULL << feature) #define
> SMC_DPM_FEATURE ( \
> FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -725,7 +729,7 @@
> static int smu_v14_0_common_get_dpm_freq_by_index(struct smu_context
> *smu, {
> if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> 1))
> smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> freq);
> - else
> + else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
> smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> freq);
>
> return 0;
> @@ -818,9 +822,11 @@ static int
> smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -855,7 +861,7 @@ static int
> smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -936,9 +942,11 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -969,7 +977,7 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -1001,7 +1009,7 @@ static int
> smu_v14_0_common_get_dpm_ultimate_freq(struct smu_context *smu, {
> if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> 1))
> smu_v14_0_1_get_dpm_ultimate_freq(smu, clk_type, min, max);
> - else
> + else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
>
Re: [PATCH] drm/amdgpu: enable dpg for vcn and jpeg on GC 11_5_2
[AMD Official Use Only - AMD Internal Distribution Only] This patch is, Reviewed-by: Tim Huang mailto:tim.hu...@amd.com>> Tim From: amd-gfx on behalf of Saleemkhan Jamadar Sent: Thursday, July 4, 2024 6:14:36 PM To: amd-gfx@lists.freedesktop.org ; Jamadar, Saleemkhan ; Liu, Leo ; Sundararaju, Sathishkumar ; Gopalakrishnan, Veerabadhran (Veera) ; Deucher, Alexander Subject: [PATCH] drm/amdgpu: enable dpg for vcn and jpeg on GC 11_5_2 DPG mode is enabled for vcn and jpeg on VCN v4_0_5 Signed-off-by: Saleemkhan Jamadar --- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 6cc86d13f32a..d30ad7d56def 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -774,7 +774,9 @@ static int soc21_common_early_init(void *handle) AMD_CG_SUPPORT_IH_CG | AMD_CG_SUPPORT_BIF_MGCG | AMD_CG_SUPPORT_BIF_LS; - adev->pg_flags = AMD_PG_SUPPORT_VCN | + adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | + AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_JPEG_DPG | AMD_PG_SUPPORT_JPEG | AMD_PG_SUPPORT_GFX_PG; adev->external_rev_id = adev->rev_id + 0x40; -- 2.25.1
RE: [PATCH] drm/amd/swsmu: enable Pstates profile levels for SMU v14.0.4
[Public]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: Alex Deucher
> Sent: Wednesday, July 10, 2024 9:48 PM
> To: Ma, Li
> Cc: amd-gfx@lists.freedesktop.org; Huang, Tim ;
> Deucher, Alexander ; Zhang, Yifan
>
> Subject: Re: [PATCH] drm/amd/swsmu: enable Pstates profile levels for SMU
> v14.0.4
>
> On Wed, Jul 10, 2024 at 5:50 AM Li Ma wrote:
> >
> > Enables following UMD stable Pstates profile levels of
> > power_dpm_force_performance_level for SMU v14.0.4.
> >
> > - profile_peak
> > - profile_min_mclk
> > - profile_min_sclk
> > - profile_standard
> >
> > Signed-off-by: Li Ma
>
> Acked-by: Alex Deucher
>
> > ---
> > .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 18
> +++---
> > 1 file changed, 15 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > index 5d47d58944f6..8798ebfcea83 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > @@ -69,6 +69,9 @@
> > #define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
> > #define SMU_14_0_0_UMD_PSTATE_FCLK 1800
> >
> > +#define SMU_14_0_4_UMD_PSTATE_GFXCLK 938
> > +#define SMU_14_0_4_UMD_PSTATE_SOCCLK 938
> > +
> > #define FEATURE_MASK(feature) (1ULL << feature) #define
> > SMC_DPM_FEATURE ( \
> > FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -1296,19
> +1299,28 @@
> > static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context
> *smu,
> > switch (clk_type) {
> > case SMU_GFXCLK:
> > case SMU_SCLK:
> > - clk_limit = SMU_14_0_0_UMD_PSTATE_GFXCLK;
> > + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
> IP_VERSION(14, 0, 4))
> > + clk_limit = SMU_14_0_4_UMD_PSTATE_GFXCLK;
> > + else
> > + clk_limit = SMU_14_0_0_UMD_PSTATE_GFXCLK;
> > if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> >
> smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
> &clk_limit);
> > else if (level ==
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
> >
> smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit,
> NULL);
> > break;
> > case SMU_SOCCLK:
> > - clk_limit = SMU_14_0_0_UMD_PSTATE_SOCCLK;
> > + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
> IP_VERSION(14, 0, 4))
> > + clk_limit = SMU_14_0_4_UMD_PSTATE_SOCCLK;
> > + else
> > + clk_limit = SMU_14_0_0_UMD_PSTATE_SOCCLK;
> > if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> >
> smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL,
> &clk_limit);
> > break;
> > case SMU_FCLK:
> > - clk_limit = SMU_14_0_0_UMD_PSTATE_FCLK;
> > + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
> IP_VERSION(14, 0, 4))
> > +
> smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
> &clk_limit);
> > + else
> > + clk_limit = SMU_14_0_0_UMD_PSTATE_FCLK;
> > if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> >
> smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
> &clk_limit);
> > else if (level ==
> > AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
> > --
> > 2.25.1
> >
RE: [PATCH] drm/amdgpu: fix potential probe issue for VCN IP v4.0.6
[Public]
Please ignore this one, will send out a new one to apply the same check to more
VCN versions. Thanks.
> -Original Message-
> From: Huang, Tim
> Sent: Tuesday, July 23, 2024 5:59 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
> ; Jamadar, Saleemkhan
> ; Ma, Li ; Huang, Tim
>
> Subject: [PATCH] drm/amdgpu: fix potential probe issue for VCN IP v4.0.6
>
> To prevent below probe failure, add a check for models with VCN IP v4.0.6
> where VCN1 may be harvested.
>
> [ 54.070117] RIP: 0010:vcn_v4_0_5_start_dpg_mode+0x9be/0x36b0
> [amdgpu]
> [ 54.071055] Code: 80 fb ff 8d 82 00 80 fe ff 81 fe 00 06 00 00 0f 43
> c2 49 69 d5 38 0d 00 00 48 8d 71 04 c1 e8 02 4c 01 f2 48 89 b2 50 f6 02
> 00 <89> 01 48 8b 82 50 f6 02 00 48 8d 48 04 48 89 8a 50 f6 02 00 c7 00
> [ 54.072408] RSP: 0018:b17985f736f8 EFLAGS: 00010286
> [ 54.072793] RAX: 00d6 RBX: 99a82f68 RCX:
>
> [ 54.073315] RDX: 99a82f68 RSI: 0004 RDI:
> 99a82f68
> [ 54.073835] RBP: b17985f73730 R08: 0001 R09:
>
> [ 54.074353] R10: 0008 R11: b17983c05000 R12:
>
> [ 54.074879] R13: R14: 99a82f68 R15:
> 0001
> [ 54.075400] FS: 7f8d9c79a000() GS:99ab2f14()
> knlGS:
> [ 54.075988] CS: 0010 DS: ES: CR0: 80050033
> [ 54.076408] CR2: CR3: 000140c3a000 CR4:
> 00750ef0
> [ 54.076927] PKRU: 5554
> [ 54.077132] Call Trace:
> [ 54.077319]
> [ 54.077484] ? show_regs+0x69/0x80
> [ 54.077747] ? __die+0x28/0x70
> [ 54.077979] ? page_fault_oops+0x180/0x4b0
> [ 54.078286] ? do_user_addr_fault+0x2d2/0x680
> [ 54.078610] ? exc_page_fault+0x84/0x190
> [ 54.078910] ? asm_exc_page_fault+0x2b/0x30
> [ 54.079224] ? vcn_v4_0_5_start_dpg_mode+0x9be/0x36b0 [amdgpu]
> [ 54.079941] ? vcn_v4_0_5_start_dpg_mode+0xe6/0x36b0 [amdgpu]
> [ 54.080617] vcn_v4_0_5_set_powergating_state+0x82/0x19b0 [amdgpu]
> [ 54.081316] amdgpu_device_ip_set_powergating_state+0x64/0xc0
> [amdgpu]
> [ 54.082057] amdgpu_vcn_ring_begin_use+0x6f/0x1d0 [amdgpu]
> [ 54.082727] amdgpu_ring_alloc+0x44/0x70 [amdgpu]
> [ 54.083351] amdgpu_vcn_dec_sw_ring_test_ring+0x40/0x110 [amdgpu]
> [ 54.084054] amdgpu_ring_test_helper+0x22/0x90 [amdgpu]
> [ 54.084698] vcn_v4_0_5_hw_init+0x87/0xc0 [amdgpu]
> [ 54.085307] amdgpu_device_init+0x1f96/0x2780 [amdgpu]
> [ 54.085951] amdgpu_driver_load_kms+0x1e/0xc0 [amdgpu]
> [ 54.086591] amdgpu_pci_probe+0x19f/0x550 [amdgpu]
> [ 54.087215] local_pci_probe+0x48/0xa0
> [ 54.087509] pci_device_probe+0xc9/0x250
> [ 54.087812] really_probe+0x1a4/0x3f0
> [ 54.088101] __driver_probe_device+0x7d/0x170
> [ 54.088443] driver_probe_device+0x24/0xa0
> [ 54.088765] __driver_attach+0xdd/0x1d0
> [ 54.089068] ? __pfx___driver_attach+0x10/0x10
> [ 54.089417] bus_for_each_dev+0x8e/0xe0
> [ 54.089718] driver_attach+0x22/0x30
> [ 54.09] bus_add_driver+0x120/0x220
> [ 54.090303] driver_register+0x62/0x120
> [ 54.090606] ? __pfx_amdgpu_init+0x10/0x10 [amdgpu]
> [ 54.091255] __pci_register_driver+0x62/0x70
> [ 54.091593] amdgpu_init+0x67/0xff0 [amdgpu]
> [ 54.092190] do_one_initcall+0x5f/0x330
> [ 54.092495] do_init_module+0x68/0x240
> [ 54.092794] load_module+0x201c/0x2110
> [ 54.093093] init_module_from_file+0x97/0xd0
> [ 54.093428] ? init_module_from_file+0x97/0xd0
> [ 54.093777] idempotent_init_module+0x11c/0x2a0
> [ 54.094134] __x64_sys_finit_module+0x64/0xc0
> [ 54.094476] do_syscall_64+0x58/0x120
> [ 54.094767] entry_SYSCALL_64_after_hwframe+0x6e/0x76
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index f45495de6875..8d75061f9f38 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -958,6 +958,9 @@ static int vcn_v4_0_5_start(struct amdgpu_device
> *adev)
> amdgpu_dpm_enable_uvd(adev, true);
>
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + if (adev->vcn.harvest_config & (1 << i))
> + continue;
> +
> fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
>
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { @@ -1162,6
> +1165,9 @@ static int vcn_v4_0_5_stop(struct amdgpu_device *adev)
> int i, r = 0;
>
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + if (adev->vcn.harvest_config & (1 << i))
> + continue;
> +
> fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
> fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
>
> --
> 2.43.0
RE: [PATCH] drm/amdgpu: fix Coverity explicit null dereferenced warnings
[Public]
Hi Christian,
> -Original Message-
> From: Christian König
> Sent: Wednesday, July 24, 2024 3:35 PM
> To: Huang, Tim ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
>
> Subject: Re: [PATCH] drm/amdgpu: fix Coverity explicit null dereferenced
> warnings
>
> Am 24.07.24 um 09:06 schrieb Tim Huang:
> > This is to address the Coverity explicit null dereferenced warnings by
> > NULL returns from amdgpu_mes_ctx_get_offs* but without follow-up
> > Checks. Meanwhile refactor the code to keep only one *_get_gpu/cpu_addr.
>
> Well nice that you are looking into that, but the short term plan is to remove
> the in kernel MES tests again.
>
> That should also fix the Coverity warnings. Arun already created a patch for
> that which will probably be merged in the next weeks.
Thanks for letting me know.
Will hold and not upstream this patch.
Best Regards,
Tim Huang
>
> Regards,
> Christian.
>
> >
> > Signed-off-by: Tim Huang
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 14 ++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 17 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 2 +-
> > drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 14 +++---
> > drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 8
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 14 +++---
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 12 ++--
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 12 ++--
> > drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 12 ++--
> > drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 12 ++--
> > 11 files changed, 55 insertions(+), 64 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > index e499d6ba306b..fb708b695db8 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > @@ -1082,7 +1082,7 @@ int amdgpu_mes_add_ring(struct amdgpu_device
> *adev, int gang_id,
> > int offset = offsetof(struct amdgpu_mes_ctx_meta_data,
> > compute[ring->idx].mec_hpd);
> > ring->eop_gpu_addr =
> > - amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
> > + amdgpu_ring_get_gpu_addr(ring, offset);
> > }
> >
> > switch (queue_type) {
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > index ad49cecb20b8..01dd7b30ba74 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > @@ -169,16 +169,6 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring)
> > ring->funcs->end_use(ring);
> > }
> >
> > -#define amdgpu_ring_get_gpu_addr(ring, offset)
> > \
> > - (ring->is_mes_queue ? \
> > -(ring->mes_ctx->meta_data_gpu_addr + offset) : \
> > -(ring->adev->wb.gpu_addr + offset * 4))
> > -
> > -#define amdgpu_ring_get_cpu_addr(ring, offset)
> > \
> > - (ring->is_mes_queue ? \
> > -(void *)((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : \
> > -(&ring->adev->wb.wb[offset]))
> > -
> > /**
> >* amdgpu_ring_init - init driver ring struct.
> >*
> > @@ -332,8 +322,8 @@ int amdgpu_ring_init(struct amdgpu_device *adev,
> > struct amdgpu_ring *ring,
> >
> > offset = amdgpu_mes_ctx_get_offs(ring,
> > AMDGPU_MES_CTX_RING_OFFS);
> > - ring->gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
> > - ring->ring = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
> > + ring->gpu_addr = amdgpu_ring_get_gpu_addr(ring, offset);
> > + ring->ring = amdgpu_ring_get_cpu_addr(ring, offset);
> > amdgpu_ring_clear_ring(ring);
> >
> > } else if (ring->ring_obj == NULL) { diff --git
> > a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > index 582053f1cd56..f65f13d147b4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > @@ -436,14 +436,15 @@ static inline void
> amdgpu_ring_patch_co
RE: [PATCH] drm/amdgpu: differentiate exteranl rev id for gfx 11.5.0
[Public] Hi Yifan, -Original Message- From: Zhang, Yifan Sent: Sunday, April 7, 2024 10:10 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Huang, Tim ; Ma, Li ; Zhang, Yifan Subject: [PATCH] drm/amdgpu: differentiate exteranl rev id for gfx 11.5.0 > This patch to differentiate exteranl rev id for gfx 11.5.0. With the typo " exteranl " fixed, this patch is Reviewed-by: Tim Huang Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/soc21.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index abe319b0f063..43ca63fe85ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -720,7 +720,10 @@ static int soc21_common_early_init(void *handle) AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_JPEG | AMD_PG_SUPPORT_GFX_PG; - adev->external_rev_id = adev->rev_id + 0x1; + if (adev->rev_id == 0) + adev->external_rev_id = 0x1; + else + adev->external_rev_id = adev->rev_id + 0x10; break; case IP_VERSION(11, 5, 1): adev->cg_flags = -- 2.37.3
RE: [PATCH] drm/amdgpu: fix uninitialized scalar variable warning
[AMD Official Use Only - General]
Hi Christian,
-Original Message-
From: Koenig, Christian
Sent: Tuesday, April 23, 2024 3:43 PM
To: Huang, Tim ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
Subject: Re: [PATCH] drm/amdgpu: fix uninitialized scalar variable warning
Am 23.04.24 um 08:28 schrieb Tim Huang:
> Clear warning that uses uninitialized value fw_size.
> In which case is the fw_size uninitialized and why setting it to zero helps
> in that case?
It's a warning that reported by the Coverity scan. When the switch case "
switch (ucode_id) " got to default and Condition "adev->firmware.load_type ==
AMDGPU_FW_LOAD_PSP", taking true branch,
it reports " uses uninitialized value fw_size " by this line.
"adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE);“
It may not happen if we call this function correctly, but it just clears the
warning and looks harmless.
Regards,
Christian.
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index d9dc5485..6b8a58f501d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -1084,7 +1084,7 @@ void amdgpu_gfx_cp_init_microcode(struct amdgpu_device
> *adev,
> const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
> struct amdgpu_firmware_info *info = NULL;
> const struct firmware *ucode_fw;
> - unsigned int fw_size;
> + unsigned int fw_size = 0;
>
> switch (ucode_id) {
> case AMDGPU_UCODE_ID_CP_PFP:
RE: [PATCH] drm/amdgpu: fix uninitialized scalar variable warning
[AMD Official Use Only - General]
-Original Message-
From: amd-gfx On Behalf Of Huang, Tim
Sent: Tuesday, April 23, 2024 4:01 PM
To: Koenig, Christian ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: RE: [PATCH] drm/amdgpu: fix uninitialized scalar variable warning
[AMD Official Use Only - General]
[AMD Official Use Only - General]
Hi Christian,
-Original Message-
From: Koenig, Christian
Sent: Tuesday, April 23, 2024 3:43 PM
To: Huang, Tim ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
Subject: Re: [PATCH] drm/amdgpu: fix uninitialized scalar variable warning
Am 23.04.24 um 08:28 schrieb Tim Huang:
> Clear warning that uses uninitialized value fw_size.
> In which case is the fw_size uninitialized and why setting it to zero helps
> in that case?
> It's a warning that reported by the Coverity scan. When the switch case "
> switch (ucode_id) " got to default and Condition "adev->firmware.load_type ==
> AMDGPU_FW_LOAD_PSP", taking true branch, it reports " uses uninitialized
> value fw_size " by this line.
> "adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE);“
> It may not happen if we call this function correctly, but it just clears the
> warning and looks harmless.
Hi Christian,
I think it more to fix this warning, maybe I need to print an error and just
return when go to the default case of "switch (ucode_id)" , will send out a v2
patch. Thanks.
> Regards,
> Christian.
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index d9dc5485..6b8a58f501d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -1084,7 +1084,7 @@ void amdgpu_gfx_cp_init_microcode(struct amdgpu_device
> *adev,
> const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
> struct amdgpu_firmware_info *info = NULL;
> const struct firmware *ucode_fw;
> - unsigned int fw_size;
> + unsigned int fw_size = 0;
>
> switch (ucode_id) {
> case AMDGPU_UCODE_ID_CP_PFP:
RE: [PATCH v2] drm/amdgpu: fix uninitialized scalar variable warning
[AMD Official Use Only - General]
-Original Message-
From: Koenig, Christian
Sent: Tuesday, April 23, 2024 7:30 PM
To: Huang, Tim ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH v2] drm/amdgpu: fix uninitialized scalar variable warning
Am 23.04.24 um 10:43 schrieb Tim Huang:
> From: Tim Huang
>
> Clear warning that uses uninitialized value fw_size.
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index d9dc5485..8d5cdbb99d8d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -1084,7 +1084,7 @@ void amdgpu_gfx_cp_init_microcode(struct amdgpu_device
> *adev,
> const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
> struct amdgpu_firmware_info *info = NULL;
> const struct firmware *ucode_fw;
> - unsigned int fw_size;
> + unsigned int fw_size = 0;
>
> You don't need that any more when the default case returns.
Yes, will not set this default and send out new patch. Thanks.
Tim
> Regards,
> Christian.
>
> switch (ucode_id) {
> case AMDGPU_UCODE_ID_CP_PFP:
> @@ -1205,7 +1205,8 @@ void amdgpu_gfx_cp_init_microcode(struct amdgpu_device
> *adev,
> fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
> break;
> default:
> - break;
> + dev_err(adev->dev, "Invalid ucode id %u\n", ucode_id);
> + return;
> }
>
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
RE: [PATCH] drm/amdgpu: fix overflowed array index read warning
[AMD Official Use Only - General]
-Original Message-
From: Koenig, Christian
Sent: Thursday, April 25, 2024 2:45 PM
To: Huang, Tim ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu: fix overflowed array index read warning
Am 25.04.24 um 07:27 schrieb Tim Huang:
> From: Tim Huang
>
> Clear warning that cast operation might have overflowed.
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> index 06f0a6534a94..6dfcd62e83ae 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> @@ -473,7 +473,7 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f,
> char __user *buf,
> size_t size, loff_t *pos)
> {
> struct amdgpu_ring *ring = file_inode(f)->i_private;
> - int r, i;
> + int r;
> uint32_t value, result, early[3];
> While at it please declare "int r;" last, e.g. keep reverse xmas tree order
> here.
Yes, it is better. Will adjust the order and send out v2, thanks.
Tim.
>Apart from that looks good to me.
>Regards,
>Christian.
>
> if (*pos & 3 || size & 3)
> @@ -485,7 +485,7 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f,
> char __user *buf,
> early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
> early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
> early[2] = ring->wptr & ring->buf_mask;
> - for (i = *pos / 4; i < 3 && size; i++) {
> + for (loff_t i = *pos / 4; i < 3 && size; i++) {
> r = put_user(early[i], (uint32_t *)buf);
> if (r)
> return r;
RE: [PATCH v2] drm/amdgpu: fix overflowed array index read warning
[AMD Official Use Only - General]
-Original Message-
From: Koenig, Christian
Sent: Thursday, April 25, 2024 9:31 PM
To: Alex Deucher ; Huang, Tim
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
Subject: Re: [PATCH v2] drm/amdgpu: fix overflowed array index read warning
Am 25.04.24 um 15:28 schrieb Alex Deucher:
> On Thu, Apr 25, 2024 at 3:22 AM Tim Huang wrote:
>> From: Tim Huang
>>
>> Clear warning that cast operation might have overflowed.
>>
>> v2: keep reverse xmas tree order to declare "int r;" (Christian)
>>
>> Signed-off-by: Tim Huang
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
>> index 06f0a6534a94..8cf60acb2970 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
>> @@ -473,8 +473,8 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f,
>> char __user *buf,
>> size_t size, loff_t *pos)
>> {
>> struct amdgpu_ring *ring = file_inode(f)->i_private;
>> - int r, i;
>> uint32_t value, result, early[3];
>> + int r;
>>
>> if (*pos & 3 || size & 3)
>> return -EINVAL;
>> @@ -485,7 +485,7 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f,
>> char __user *buf,
>> early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
>> early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
>> early[2] = ring->wptr & ring->buf_mask;
>> - for (i = *pos / 4; i < 3 && size; i++) {
>> + for (loff_t i = *pos / 4; i < 3 && size; i++) {
> Some older compilers complain about declarations mixed with code like
> this. Not sure how big a deal that would be.
>Good point, we would like to be able to backport this.
>Somebody from Alivins team needs to comment, but IIRC we agreed that this
>would be legal and we take care of it by using appropriate compiler flags on
>older kernels.
>Christian.
Thanks for pointing out. Will avoid doing this.
>
> Alex
>
>> r = put_user(early[i], (uint32_t *)buf);
>> if (r)
>> return r;
>> --
>> 2.39.2
>>
RE: [PATCH] drm/amd/pm: fix uninitialized variable warning for smu8_hwmgr
[AMD Official Use Only - General] -Original Message- From: Christian König Sent: Friday, April 26, 2024 7:39 PM To: Huang, Tim ; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Koenig, Christian Subject: Re: [PATCH] drm/amd/pm: fix uninitialized variable warning for smu8_hwmgr Am 26.04.24 um 11:29 schrieb Tim Huang: > Clear warnings that using uninitialized value level when fails to get > the value from SMU. > > Signed-off-by: Tim Huang > Maybe drop the blank line before the "if (ret)", apart from that Yes, will drop it. Thanks. Tim > Reviewed-by: Christian König > --- > .../drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c| 18 +++--- > 1 file changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c > index b015a601b385..4e4146ce71c1 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c > @@ -584,6 +584,7 @@ static int smu8_init_uvd_limit(struct pp_hwmgr *hwmgr) > > hwmgr->dyn_state.uvd_clock_voltage_dependency_table; > unsigned long clock = 0; > uint32_t level; > + int ret; > > if (NULL == table || table->count <= 0) > return -EINVAL; > @@ -591,7 +592,10 @@ static int smu8_init_uvd_limit(struct pp_hwmgr *hwmgr) > data->uvd_dpm.soft_min_clk = 0; > data->uvd_dpm.hard_min_clk = 0; > > - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel, &level); > + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel, &level); > + > + if (ret) > + return ret; > > if (level < table->count) > clock = table->entries[level].vclk; @@ -611,6 +615,7 @@ static > int > smu8_init_vce_limit(struct pp_hwmgr *hwmgr) > > hwmgr->dyn_state.vce_clock_voltage_dependency_table; > unsigned long clock = 0; > uint32_t level; > + int ret; > > if (NULL == table || table->count <= 0) > return -EINVAL; > @@ -618,7 +623,10 @@ static int smu8_init_vce_limit(struct pp_hwmgr *hwmgr) > data->vce_dpm.soft_min_clk = 0; > data->vce_dpm.hard_min_clk = 0; > > - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel, &level); > + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel, > +&level); > + > + if (ret) > + return ret; > > if (level < table->count) > clock = table->entries[level].ecclk; @@ -638,6 +646,7 @@ static > int smu8_init_acp_limit(struct pp_hwmgr *hwmgr) > > hwmgr->dyn_state.acp_clock_voltage_dependency_table; > unsigned long clock = 0; > uint32_t level; > + int ret; > > if (NULL == table || table->count <= 0) > return -EINVAL; > @@ -645,7 +654,10 @@ static int smu8_init_acp_limit(struct pp_hwmgr *hwmgr) > data->acp_dpm.soft_min_clk = 0; > data->acp_dpm.hard_min_clk = 0; > > - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel, &level); > + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel, > +&level); > + > + if (ret) > + return ret; > > if (level < table->count) > clock = table->entries[level].acpclk;
RE: [PATCH] drm/amdgpu/pm: Check the return value of smum_send_msg_to_smc
[Public]
This patch is,
Reviewed-by: Tim Huang
-Original Message-
From: amd-gfx On Behalf Of Ma Jun
Sent: Friday, April 26, 2024 5:37 PM
To: amd-gfx@lists.freedesktop.org; Koenig, Christian
; Deucher, Alexander
Cc: Ma, Jun
Subject: [PATCH] drm/amdgpu/pm: Check the return value of smum_send_msg_to_smc
Check the return value of smum_send_msg_to_smc, otherwise we might use an
uninitialized variable "now"
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 02ba68d7c654..0b181bc8931c 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -1036,7 +1036,9 @@ static int smu10_print_clock_levels(struct pp_hwmgr
*hwmgr,
switch (type) {
case PP_SCLK:
- smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now);
+ ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency,
&now);
+ if (ret)
+ return ret;
/* driver only know min/max gfx_clk, Add level 1 for all other gfx clks
*/
if (now == data->gfx_max_freq_limit/100) @@ -1057,7 +1059,9 @@
static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
i == 2 ? "*" : "");
break;
case PP_MCLK:
- smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now);
+ ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency,
&now);
+ if (ret)
+ return ret;
for (i = 0; i < mclk_table->count; i++)
size += sprintf(buf + size, "%d: %uMhz %s\n",
--
2.34.1
RE: [PATCH 2/2] drm/amd/pm: fix uninitialized variable warning
[AMD Official Use Only - General]
> -Original Message-
> From: Jesse Zhang
> Sent: Friday, April 26, 2024 5:53 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 2/2] drm/amd/pm: fix uninitialized variable warning
>
> Check the return of function smum_send_msg_to_smc as it may fail to
> initialize the variable.
>
> Signed-off-by: Jesse Zhang
> ---
> .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 8 +--
> .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 21 -
> --
> .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 19 +++--
> .../amd/pm/powerplay/smumgr/smu10_smumgr.c| 5 -
> 4 files changed, 37 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> index 02ba68d7c654..f9f016cb60ce 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1310,13 +1310,17 @@ static int smu10_read_sensor(struct pp_hwmgr
> *hwmgr, int idx,
>
> switch (idx) {
> case AMDGPU_PP_SENSOR_GFX_SCLK:
> - smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_GetGfxclkFrequency, &sclk);
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_GetGfxclkFrequency, &sclk);
> + if (ret)
> + break;
> /* in units of 10KHZ */
> *((uint32_t *)value) = sclk * 100;
> *size = 4;
> break;
> case AMDGPU_PP_SENSOR_GFX_MCLK:
> - smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_GetFclkFrequency, &mclk);
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_GetFclkFrequency, &mclk);
> + if (ret)
> + break;
> /* in units of 10KHZ */
> *((uint32_t *)value) = mclk * 100;
> *size = 4;
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> index 1fcd4451001f..5c95eda6cbd2 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4000,6 +4000,7 @@ static int smu7_read_sensor(struct pp_hwmgr
> *hwmgr, int idx,
> uint32_t offset, val_vid;
> struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr-
> >backend);
> struct amdgpu_device *adev = hwmgr->adev;
> + int ret = 0;
>
> /* size must be at least 4 bytes for all sensors */
> if (*size < 4)
> @@ -4007,12 +4008,16 @@ static int smu7_read_sensor(struct pp_hwmgr
> *hwmgr, int idx,
>
> switch (idx) {
> case AMDGPU_PP_SENSOR_GFX_SCLK:
> - smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_API_GetSclkFrequency, &sclk);
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_API_GetSclkFrequency, &sclk);
> + if (ret)
> + return ret;
> *((uint32_t *)value) = sclk;
> *size = 4;
> return 0;
> case AMDGPU_PP_SENSOR_GFX_MCLK:
> - smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_API_GetMclkFrequency, &mclk);
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_API_GetMclkFrequency, &mclk);
> + if (ret)
> + return ret;
> *((uint32_t *)value) = mclk;
> *size = 4;
> return 0;
> @@ -4965,13 +4970,14 @@ static int smu7_print_clock_levels(struct
> pp_hwmgr *hwmgr,
> struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
> struct phm_odn_clock_levels *odn_sclk_table = &(odn_table-
> >odn_core_clock_dpm_levels);
> struct phm_odn_clock_levels *odn_mclk_table = &(odn_table-
> >odn_memory_clock_dpm_levels);
> - int size = 0;
> + int size = 0, ret = 0;
> uint32_t i, now, clock, pcie_speed;
>
> switch (type) {
> case PP_SCLK:
> - smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_API_GetSclkFrequency, &clock);
> -
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_API_GetSclkFrequency, &clock);
> + if (ret)
> + return ret;
> for (i = 0; i < sclk_table->count; i++) {
> if (clock > sclk_table->dpm_levels[i].value)
> continue;
> @@ -4985,8 +4991,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr
> *hwmgr,
>
RE: [PATCH 2/2 V2] drm/amd/pm: fix uninitialized variable warning
[Public]
This patch is,
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
> -Original Message-
> From: Jesse Zhang
> Sent: Sunday, April 28, 2024 2:02 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 2/2 V2] drm/amd/pm: fix uninitialized variable warning
>
> Check the return of function smum_send_msg_to_smc as it may fail to
> initialize the variable.
>
> Signed-off-by: Jesse Zhang
> ---
> .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 8 +--
> .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 21 -
> --
> .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 19 +++--
> .../amd/pm/powerplay/smumgr/smu10_smumgr.c| 5 -
> 4 files changed, 37 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> index 02ba68d7c654..f9f016cb60ce 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1310,13 +1310,17 @@ static int smu10_read_sensor(struct pp_hwmgr
> *hwmgr, int idx,
>
> switch (idx) {
> case AMDGPU_PP_SENSOR_GFX_SCLK:
> - smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_GetGfxclkFrequency, &sclk);
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_GetGfxclkFrequency, &sclk);
> + if (ret)
> + break;
> /* in units of 10KHZ */
> *((uint32_t *)value) = sclk * 100;
> *size = 4;
> break;
> case AMDGPU_PP_SENSOR_GFX_MCLK:
> - smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_GetFclkFrequency, &mclk);
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_GetFclkFrequency, &mclk);
> + if (ret)
> + break;
> /* in units of 10KHZ */
> *((uint32_t *)value) = mclk * 100;
> *size = 4;
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> index 1fcd4451001f..5c95eda6cbd2 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4000,6 +4000,7 @@ static int smu7_read_sensor(struct pp_hwmgr
> *hwmgr, int idx,
> uint32_t offset, val_vid;
> struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr-
> >backend);
> struct amdgpu_device *adev = hwmgr->adev;
> + int ret = 0;
>
> /* size must be at least 4 bytes for all sensors */
> if (*size < 4)
> @@ -4007,12 +4008,16 @@ static int smu7_read_sensor(struct pp_hwmgr
> *hwmgr, int idx,
>
> switch (idx) {
> case AMDGPU_PP_SENSOR_GFX_SCLK:
> - smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_API_GetSclkFrequency, &sclk);
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_API_GetSclkFrequency, &sclk);
> + if (ret)
> + return ret;
> *((uint32_t *)value) = sclk;
> *size = 4;
> return 0;
> case AMDGPU_PP_SENSOR_GFX_MCLK:
> - smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_API_GetMclkFrequency, &mclk);
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_API_GetMclkFrequency, &mclk);
> + if (ret)
> + return ret;
> *((uint32_t *)value) = mclk;
> *size = 4;
> return 0;
> @@ -4965,13 +4970,14 @@ static int smu7_print_clock_levels(struct
> pp_hwmgr *hwmgr,
> struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
> struct phm_odn_clock_levels *odn_sclk_table = &(odn_table-
> >odn_core_clock_dpm_levels);
> struct phm_odn_clock_levels *odn_mclk_table = &(odn_table-
> >odn_memory_clock_dpm_levels);
> - int size = 0;
> + int size = 0, ret = 0;
> uint32_t i, now, clock, pcie_speed;
>
> switch (type) {
> case PP_SCLK:
> - smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_API_GetSclkFrequency, &clock);
> -
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_API_GetSclkFrequency, &clock);
> + if (ret)
> + return ret;
> for (i = 0; i < sclk_table->count; i++) {
> if (clock > sclk_table->dpm_levels[i].value)
> continue;
> @@ -4985,8 +4991,9 @@ static int smu7_print_clock_levels(struc
RE: [PATCH 1/2] drm/amd/pm: fix the uninitialized scalar variable waring
[AMD Official Use Only - General] This patch is, Reviewed-by: Tim Huang Best Regards, Tim Huang > -Original Message- > From: Jesse Zhang > Sent: Friday, April 26, 2024 5:52 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Huang, Tim ; Zhang, > Jesse(Jie) ; Zhang, Jesse(Jie) > > Subject: [PATCH 1/2] drm/amd/pm: fix the uninitialized scalar variable waring > > Initialize variable size before calling > hwmgr->hwmgr_func->iread_sensor, such as smu7_read_sensor. > > Signed-off-by: Jesse Zhang > --- > drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c > b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c > index 5fb21a0508cd..ec2b6d0674ed 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c > @@ -102,6 +102,7 @@ static void pp_swctf_delayed_work_handler(struct > work_struct *work) > uint32_t gpu_temperature, size; > int ret; > > + size = sizeof(gpu_temperature); > /* >* If the hotspot/edge temperature is confirmed as below SW CTF > setting point >* after the delay enforced, nothing will be done. > -- > 2.25.1
RE: [PATCH 1/3] drm/amd/pm: Fix negative array index read warning for pptable->DpmDescriptor
[AMD Official Use Only - General]
> -Original Message-
> From: Jesse Zhang
> Sent: Friday, April 26, 2024 3:28 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 1/3] drm/amd/pm: Fix negative array index read warning for
> pptable->DpmDescriptor
>
> Avoid using the negative values
> for clk_idex as an index into an array pptable->DpmDescriptor.
>
> Signed-off-by: Jesse Zhang
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 25 +++---
> -
> 1 file changed, 20 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 5a68d365967f..cd88d2c3841a 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -1219,15 +1219,18 @@ static int
> navi10_get_current_clk_freq_by_table(struct smu_context *smu,
> value);
> }
>
> -static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu,
> enum smu_clk_type clk_type)
> +static int navi10_is_support_fine_grained_dpm(struct smu_context *smu,
> +enum smu_clk_type clk_type)
> {
> PPTable_t *pptable = smu->smu_table.driver_pptable;
> DpmDescriptor_t *dpm_desc = NULL;
> - uint32_t clk_index = 0;
> + int clk_index = 0;
>
> clk_index = smu_cmn_to_asic_specific_index(smu,
> CMN2ASIC_MAPPING_CLK,
> clk_type);
> + if(clk_index)
Hi jesse,
If should only be "if(clk_index < 0)" to return an error.
Tim
> + return clk_index;
> +
> dpm_desc = &pptable->DpmDescriptor[clk_index];
>
> /* 0 - Fine grained DPM, 1 - Discrete DPM */ @@ -1287,7 +1290,11
> @@ static int navi10_emit_clk_levels(struct smu_context *smu,
> if (ret)
> return ret;
>
> - if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
> + ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
> + if (ret < 0)
> + return ret;
> +
> + if (!ret) {
> for (i = 0; i < count; i++) {
> ret =
> smu_v11_0_get_dpm_freq_by_index(smu,
> clk_type,
> i,
> &value);
> @@ -1496,7 +1503,11 @@ static int navi10_print_clk_levels(struct
> smu_context *smu,
> if (ret)
> return size;
>
> - if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
> + ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
> + if (ret < 0)
> + return ret;
> +
> + if (!ret) {
> for (i = 0; i < count; i++) {
> ret =
> smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
> if (ret)
> @@ -1665,7 +1676,11 @@ static int navi10_force_clk_levels(struct
> smu_context *smu,
> case SMU_UCLK:
> case SMU_FCLK:
> /* There is only 2 levels for fine grained DPM */
> - if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
> + ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
> + if (ret < 0)
> + return ret;
> +
> + if (ret) {
> soft_max_level = (soft_max_level >= 1 ? 1 : 0);
> soft_min_level = (soft_min_level >= 1 ? 1 : 0);
> }
> --
> 2.25.1
RE: [PATCH 3/3] drm/amd/pm: fix the uninitialized scalar variable warning
[AMD Official Use Only - General]
> -Original Message-
> From: Jesse Zhang
> Sent: Friday, April 26, 2024 3:29 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 3/3] drm/amd/pm: fix the uninitialized scalar variable
> warning
>
> Fix warning for using uninitialized values sclk_mask, mck_mask and
> soc_mask.
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> index 8908bbb3ff1f..10f673b651a0 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> @@ -932,7 +932,7 @@ static int renoir_set_performance_level(struct
> smu_context *smu,
> enum amd_dpm_forced_level level)
> {
> int ret = 0;
> - uint32_t sclk_mask, mclk_mask, soc_mask;
> + uint32_t sclk_mask, mclk_mask, soc_mask = 0;
Hi Jesse,
We should not need to set default here. How about set the correct mask in the
renoir_get_profiling_clk_mask according to the profile.
Tim
>
> switch (level) {
> case AMD_DPM_FORCED_LEVEL_HIGH:
> @@ -1018,8 +1018,10 @@ static int renoir_set_performance_level(struct
> smu_context *smu,
> &soc_mask);
> if (ret)
> return ret;
> - renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
> - renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
> + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
> + renoir_force_clk_levels(smu, SMU_SCLK, 1 <<
> sclk_mask);
> + else
> + renoir_force_clk_levels(smu, SMU_MCLK, 1 <<
> mclk_mask);
We should need to set both the clock levels here, just need to get the correct
mask before setting them.
Tim
> renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> --
> 2.25.1
RE: [PATCH] drm/amd/pm: fix warning using uninitialized value of max_vid_step
[AMD Official Use Only - General] > -Original Message- > From: Jesse Zhang > Sent: Monday, April 29, 2024 10:29 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Huang, Tim ; Zhang, > Jesse(Jie) ; Zhang, Jesse(Jie) > Subject: [PATCH] drm/amd/pm: fix warning using uninitialized value of > max_vid_step > > Check the return of pp_atomfwctrl_get_Voltage_table_v4 > as it may fail to initialize max_vid_step > > Signed-off-by: Jesse Zhang > --- > drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > index b602059436a8..70c711cec897 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > @@ -2573,8 +2573,12 @@ static int vega10_init_smc_table(struct pp_hwmgr > *hwmgr) > } > } > > - pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC, > + result = pp_atomfwctrl_get_voltage_table_v4(hwmgr, > VOLTAGE_TYPE_VDDC, > VOLTAGE_OBJ_SVID2, &voltage_table); > + PP_ASSERT_WITH_CODE(result < 0, Hi jesse, It should be PP_ASSERT_WITH_CODE(!result, right? Tim > + "Failed to get voltage tables!", > + return result); > + > pp_table->MaxVidStep = voltage_table.max_vid_step; > > pp_table->GfxDpmVoltageMode = > -- > 2.25.1
RE: [PATCH V2] drm/amd/pm: fix warning using uninitialized value of max_vid_step
[Public] Reviewed-by: Tim Huang Best Regards, Tim Huang > -Original Message- > From: Jesse Zhang > Sent: Monday, April 29, 2024 3:29 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Huang, Tim ; Zhang, > Jesse(Jie) ; Zhang, Jesse(Jie) > Subject: [PATCH V2] drm/amd/pm: fix warning using uninitialized value of > max_vid_step > > Check the return of pp_atomfwctrl_get_Voltage_table_v4 > as it may fail to initialize max_vid_step > V2: change the check condition (Tim Huang) > > Signed-off-by: Jesse Zhang > --- > drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > index b602059436a8..d004cdbe97b4 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > @@ -2573,8 +2573,11 @@ static int vega10_init_smc_table(struct pp_hwmgr > *hwmgr) > } > } > > - pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC, > + result = pp_atomfwctrl_get_voltage_table_v4(hwmgr, > VOLTAGE_TYPE_VDDC, > VOLTAGE_OBJ_SVID2, &voltage_table); > + PP_ASSERT_WITH_CODE(!result, > + "Failed to get voltage table!", > + return result); > pp_table->MaxVidStep = voltage_table.max_vid_step; > > pp_table->GfxDpmVoltageMode = > -- > 2.25.1
RE: [PATCH 3/3 V2] drm/amd/pm: fix the uninitialized scalar variable warning
[AMD Official Use Only - General]
> -Original Message-
> From: Jesse Zhang
> Sent: Monday, April 29, 2024 10:10 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
> Subject: [PATCH 3/3 V2] drm/amd/pm: fix the uninitialized scalar variable
> warning
>
> Fix warning for using uninitialized values sclk_mask, mck_mask and soc_mask.
> v2: Init the variables in the renoir_get_profiling_clk_mask(Tim Huang)
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> index 8908bbb3ff1f..546a2268823a 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> @@ -253,6 +253,10 @@ static int renoir_get_profiling_clk_mask(struct
> smu_context *smu,
>uint32_t *mclk_mask,
>uint32_t *soc_mask)
> {
> + *sclk_mask = 0;
> + /* mclk levels are in reverse order */
> + *mclk_maks = NUM_MEMCLK_DPM_LEVELS - 1;
> + *sock_mask = 0;
>
This is risky because the function may be called with an empty parameter
pointer, like in the renoir_get_dpm_ultimate_freq.
Besides, for some profile mode, like the AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,
the default mask for sclk_mask and soc_mask maybe not 0.
IIRC, the smu13 use the default UMD_PSTATE frequency. Not sure whether Renoir
apply this as well.
> if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
> if (sclk_mask)
> --
> 2.25.1
RE: [PATCH 1/3 V2] drm/amd/pm: Fix negative array index read warning for pptable->DpmDescriptor
[Public]
This patch is,
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
> -Original Message-
> From: Jesse Zhang
> Sent: Sunday, April 28, 2024 5:38 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
> Subject: [PATCH 1/3 V2] drm/amd/pm: Fix negative array index read warning for
> pptable->DpmDescriptor
>
> Avoid using the negative values
> for clk_idex as an index into an array pptable->DpmDescriptor.
>
> V2: fix clk_index return check (Tim Huang)
>
> Signed-off-by: Jesse Zhang
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 27 ++-
> 1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 5a68d365967f..c06e0d6e3017 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -1219,19 +1219,22 @@ static int
> navi10_get_current_clk_freq_by_table(struct smu_context *smu,
> value);
> }
>
> -static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu,
> enum smu_clk_type clk_type)
> +static int navi10_is_support_fine_grained_dpm(struct smu_context *smu,
> +enum smu_clk_type clk_type)
> {
> PPTable_t *pptable = smu->smu_table.driver_pptable;
> DpmDescriptor_t *dpm_desc = NULL;
> - uint32_t clk_index = 0;
> + int clk_index = 0;
>
> clk_index = smu_cmn_to_asic_specific_index(smu,
> CMN2ASIC_MAPPING_CLK,
> clk_type);
> + if (clk_index < 0)
> + return clk_index;
> +
> dpm_desc = &pptable->DpmDescriptor[clk_index];
>
> /* 0 - Fine grained DPM, 1 - Discrete DPM */
> - return dpm_desc->SnapToDiscrete == 0;
> + return dpm_desc->SnapToDiscrete == 0 ? 1 : 0;
> }
>
> static inline bool navi10_od_feature_is_supported(struct
> smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
> @@ -1287,7 +1290,11 @@ static int navi10_emit_clk_levels(struct smu_context
> *smu,
> if (ret)
> return ret;
>
> - if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
> + ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
> + if (ret < 0)
> + return ret;
> +
> + if (!ret) {
> for (i = 0; i < count; i++) {
> ret = smu_v11_0_get_dpm_freq_by_index(smu,
> clk_type,
> i,
> &value);
> @@ -1496,7 +1503,11 @@ static int navi10_print_clk_levels(struct smu_context
> *smu,
> if (ret)
> return size;
>
> - if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
> + ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
> + if (ret < 0)
> + return ret;
> +
> + if (!ret) {
> for (i = 0; i < count; i++) {
> ret = smu_v11_0_get_dpm_freq_by_index(smu,
> clk_type, i, &value);
> if (ret)
> @@ -1665,7 +1676,11 @@ static int navi10_force_clk_levels(struct smu_context
> *smu,
> case SMU_UCLK:
> case SMU_FCLK:
> /* There is only 2 levels for fine grained DPM */
> - if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
> + ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
> + if (ret < 0)
> + return ret;
> +
> + if (ret) {
> soft_max_level = (soft_max_level >= 1 ? 1 : 0);
> soft_min_level = (soft_min_level >= 1 ? 1 : 0);
> }
> --
> 2.25.1
RE: [PATCH 2/3] drm/amd/pm: fix the Out-of-bounds read warning
[Public]
This patch is,
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
> -Original Message-
> From: Jesse Zhang
> Sent: Friday, April 26, 2024 3:29 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
> Subject: [PATCH 2/3] drm/amd/pm: fix the Out-of-bounds read warning
>
> using index i - 1U may beyond element index for mc_data[] when i = 0.
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
> index b1b4c09c3467..b56298d9da98 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
> @@ -73,8 +73,9 @@ static int atomctrl_retrieve_ac_timing(
> j++;
> } else if ((table-
> >mc_reg_address[i].uc_pre_reg_data &
> LOW_NIBBLE_MASK)
> == DATA_EQU_PREV) {
> - table-
> >mc_reg_table_entry[num_ranges].mc_data[i] =
> - table-
> >mc_reg_table_entry[num_ranges].mc_data[i-1];
> + if (i)
> + table-
> >mc_reg_table_entry[num_ranges].mc_data[i] =
> + table-
> >mc_reg_table_entry[num_ranges].mc_data[i-1];
> }
> }
> num_ranges++;
> --
> 2.25.1
RE: [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for vega10_hwmgr
[AMD Official Use Only - General]
Ping ...
> -Original Message-
> From: Huang, Tim
> Sent: Sunday, April 28, 2024 4:45 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim
> Subject: [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for
> vega10_hwmgr
>
> Clear warnings that using uninitialized variable when fails to get the valid
> value
> from SMU.
>
> Signed-off-by: Tim Huang
> ---
> .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 46 ++-
> .../amd/pm/powerplay/smumgr/vega10_smumgr.c | 6 ++-
> 2 files changed, 39 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> index 9f5bd998c6bf..488ad9de4694 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> @@ -354,13 +354,13 @@ static int vega10_odn_initial_default_setting(struct
> pp_hwmgr *hwmgr)
> return 0;
> }
>
> -static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
> +static int vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
> {
> struct vega10_hwmgr *data = hwmgr->backend;
> - int i;
> uint32_t sub_vendor_id, hw_revision;
> uint32_t top32, bottom32;
> struct amdgpu_device *adev = hwmgr->adev;
> + int ret, i;
>
> vega10_initialize_power_tune_defaults(hwmgr);
>
> @@ -485,9 +485,12 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr
> *hwmgr)
> if (data->registry_data.vr0hot_enabled)
> data->smu_features[GNLD_VR0HOT].supported = true;
>
> - smum_send_msg_to_smc(hwmgr,
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_GetSmuVersion,
> &hwmgr->smu_version);
> + if (ret)
> + return ret;
> +
> /* ACG firmware has major version 5 */
> if ((hwmgr->smu_version & 0xff00) == 0x500)
> data->smu_features[GNLD_ACG].supported = true; @@ -505,10
> +508,16 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
> data->smu_features[GNLD_PCC_LIMIT].supported = true;
>
> /* Get the SN to turn into a Unique ID */
> - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32,
> &top32);
> - smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_ReadSerialNumTop32, &top32);
> + if (ret)
> + return ret;
> +
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
> + if (ret)
> + return ret;
>
> adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
> + return 0;
> }
>
> #ifdef PPLIB_VEGA10_EVV_SUPPORT
> @@ -882,7 +891,9 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr
> *hwmgr)
>
> vega10_set_features_platform_caps(hwmgr);
>
> - vega10_init_dpm_defaults(hwmgr);
> + result = vega10_init_dpm_defaults(hwmgr);
> + if (result)
> + return result;
>
> #ifdef PPLIB_VEGA10_EVV_SUPPORT
> /* Get leakage voltage based on leakage ID. */ @@ -3900,11 +3911,14
> @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
> uint32_t *query)
> {
> uint32_t value;
> + int ret;
>
> if (!query)
> return -EINVAL;
>
> - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr,
> &value);
> + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr,
> &value);
> + if (ret)
> + return ret;
>
> /* SMC returning actual watts, keep consistent with legacy asics, low 8
> bit as 8 fractional bits */
> *query = value << 8;
> @@ -4800,14 +4814,16 @@ static int vega10_print_clock_levels(struct
> pp_hwmgr *hwmgr,
> uint32_t gen_speed, lane_width, current_gen_speed,
> current_lane_width;
> PPTable_t *pptable = &(data->smc_state_table.pp_table);
>
> - int i, now, size = 0, count = 0;
> + int i, ret, now, size = 0, count = 0;
>
> switch (type) {
> case PP_SCLK:
> if (data->registry_data.sclk_dpm_key_disabled)
> break;
>
> - smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_GetCurrentGfxclkIndex, &now);
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_GetCurrentGfxclkIndex, &now);
> + if (ret)
> + break;
>
> if (hwmgr->pp_one_vf &
RE: [PATCH] drm/amdgpu: fix uninitialized scalar variable warning
[Public]
Ping ...
> -Original Message-
> From: Huang, Tim
> Sent: Friday, April 26, 2024 9:14 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim
> Subject: [PATCH] drm/amdgpu: fix uninitialized scalar variable warning
>
> Clear warning that field bp is uninitialized when calling
> amdgpu_virt_ras_add_bps.
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index 54ab51a4ada7..a2f15edfe812 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -395,6 +395,8 @@ static void amdgpu_virt_add_bad_page(struct
> amdgpu_device *adev,
> else
> vram_usage_va = adev->mman.drv_vram_usage_va;
>
> + memset(&bp, 0, sizeof(struct eeprom_table_record));
> +
> if (bp_block_size) {
> bp_cnt = bp_block_size / sizeof(uint64_t);
> for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) {
> --
> 2.39.2
RE: [PATCH] drm/amdgpu: fix uninitialized scalar variable warning
[Public]
> -Original Message-
> From: Wang, Yang(Kevin)
> Sent: Tuesday, April 30, 2024 12:14 PM
> To: Huang, Tim ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
>
> Subject: RE: [PATCH] drm/amdgpu: fix uninitialized scalar variable warning
>
> [Public]
>
> -Original Message-----
> From: amd-gfx On Behalf Of Huang,
> Tim
> Sent: Tuesday, April 30, 2024 11:32 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
>
> Subject: RE: [PATCH] drm/amdgpu: fix uninitialized scalar variable warning
>
> [Public]
>
> [Public]
>
> Ping ...
> > -Original Message-
> > From: Huang, Tim
> > Sent: Friday, April 26, 2024 9:14 AM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Koenig, Christian
> > ; Huang, Tim
> > Subject: [PATCH] drm/amdgpu: fix uninitialized scalar variable warning
> >
> > Clear warning that field bp is uninitialized when calling
> > amdgpu_virt_ras_add_bps.
> >
> > Signed-off-by: Tim Huang
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > index 54ab51a4ada7..a2f15edfe812 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > @@ -395,6 +395,8 @@ static void amdgpu_virt_add_bad_page(struct
> > amdgpu_device *adev,
> > else
> > vram_usage_va = adev->mman.drv_vram_usage_va;
> >
> > + memset(&bp, 0, sizeof(struct eeprom_table_record));
> [Kevin]:
>
> It is better to change code to "sizeof (bp)".
Yes, agree, will change to this. Thanks.
Tim
>
> Reviewed-by: Yang Wang
>
> Best Regards,
> Kevin
> > +
> > if (bp_block_size) {
> > bp_cnt = bp_block_size / sizeof(uint64_t);
> > for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) {
> > --
> > 2.39.2
>
RE: [PATCH v2] drm/amdgpu: Fix out-of-bounds write warning
[Public]
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
> -Original Message-
> From: amd-gfx On Behalf Of Ma Jun
> Sent: Monday, May 6, 2024 1:59 PM
> To: amd-gfx@lists.freedesktop.org; Koenig, Christian
> ; Deucher, Alexander
>
> Cc: Ma, Jun
> Subject: [PATCH v2] drm/amdgpu: Fix out-of-bounds write warning
>
> Check the ring type value to fix the out-of-bounds write warning
>
> Signed-off-by: Ma Jun
> Suggested-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> index 15c240656470..ad49cecb20b8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> @@ -352,7 +352,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct
> amdgpu_ring *ring,
> ring->max_dw = max_dw;
> ring->hw_prio = hw_prio;
>
> - if (!ring->no_scheduler) {
> + if (!ring->no_scheduler && ring->funcs->type < AMDGPU_HW_IP_NUM)
> {
> hw_ip = ring->funcs->type;
> num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds;
> adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] =
> --
> 2.34.1
RE: [PATCH] drm/amd/pm: fix the uninitialized scalar variable warning
[AMD Official Use Only - General] Hi Jesse, > -Original Message- > From: Zhang, Jesse(Jie) > Sent: Monday, May 6, 2024 2:21 PM > To: Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Huang, Tim > Subject: RE: [PATCH] drm/amd/pm: fix the uninitialized scalar variable warning > > [AMD Official Use Only - General] > > Ping ... > > -Original Message- > From: Jesse Zhang > Sent: Tuesday, April 30, 2024 3:14 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Huang, Tim ; Zhang, > Jesse(Jie) ; Zhang, Jesse(Jie) > Subject: [PATCH] drm/amd/pm: fix the uninitialized scalar variable warning > > Fix warning for using uninitialized values sclk_mask, mclk_mask and soc_mask. > v2:Set default variable to UMD PSTATE(Tim Huang) > > Signed-off-by: Jesse Zhang > --- > .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 32 --- > 1 file changed, 27 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c > index 8908bbb3ff1f..36a49cfc22e4 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c > @@ -835,10 +835,20 @@ static int renoir_force_clk_levels(struct smu_context > *smu, > ret = renoir_get_dpm_clk_limited(smu, clk_type, > soft_max_level, > &max_freq); > if (ret) > return ret; > - ret = smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); > +/* = 0: min_freq > + * = 1: UMD_PSTATE_CLK > + * >= 2: max_freq > + */ > + ret = smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetSoftMaxSocclkByFreq, > + soft_max_level == 0 ? > min_freq : > + soft_max_level == 1 ? > RENOIR_UMD_PSTATE_SOCCLK : max_freq, > + NULL); > if (ret) > return ret; > - ret = smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); > + ret = smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetHardMinSocclkByFreq, > + soft_min_level == 0 ? > min_freq : > + soft_min_level == 1 ? > RENOIR_UMD_PSTATE_SOCCLK : max_freq, > + NULL); > if (ret) > return ret; > break; > @@ -850,10 +860,21 @@ static int renoir_force_clk_levels(struct smu_context > *smu, > ret = renoir_get_dpm_clk_limited(smu, clk_type, > soft_max_level, > &max_freq); > if (ret) > return ret; > - ret = smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); > + /* mclk levels are in reverse order > +* = 0: max_freq > +* = 1: UMD_PSTATE_CLK > +* >= 2: min_freq > +*/ > + ret = smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetSoftMaxFclkByFreq, > + soft_max_level >= 2 ? > min_freq : > + soft_max_level == 1 ? > RENOIR_UMD_PSTATE_FCLK : max_freq, > + NULL); > if (ret) > return ret; > - ret = smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); > + ret = smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetHardMinFclkByFreq, > + soft_min_level >= 2 > ? min_freq : > + soft_min_level == 1 ? > RENOIR_UMD_PSTATE_SOCCLK : max_freq, > + NULL); It's not the fault of your patch. The original implementation may not set the correct min frequency for MCLK when set to the performance level PROFILE_MIN_MCLK, For the case, we should make the min_freq = max_freq = clk_table->FClocks[NUM_FCLK_DPM_LEVELS-1].Freq. Tim > if (ret) > return ret; > break; > @@ -932,7 +953,8 @@ static int ren
RE: [PATCH] drm/amdgpu: Fix out-of-bounds read of df_v1_7_channel_number
[Public] Reviewed-by: Tim Huang Best Regards, Tim Huang > -Original Message- > From: amd-gfx On Behalf Of Ma Jun > Sent: Tuesday, May 7, 2024 11:19 AM > To: amd-gfx@lists.freedesktop.org; Koenig, Christian > ; Deucher, Alexander > > Cc: Ma, Jun > Subject: [PATCH] drm/amdgpu: Fix out-of-bounds read of > df_v1_7_channel_number > > Check the fb_channel_number range to avoid the array out-of-bounds read error > > Signed-off-by: Ma Jun > --- > drivers/gpu/drm/amd/amdgpu/df_v1_7.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c > b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c > index 5dfab802..cd298556f7a6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c > +++ b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c > @@ -70,6 +70,8 @@ static u32 df_v1_7_get_hbm_channel_number(struct > amdgpu_device *adev) > int fb_channel_number; > > fb_channel_number = adev->df.funcs->get_fb_channel_number(adev); > + if (fb_channel_number >= ARRAY_SIZE(df_v1_7_channel_number)) > + fb_channel_number = 0; > > return df_v1_7_channel_number[fb_channel_number]; > } > -- > 2.34.1
RE: [PATCH 2/2] drm/amd/pm: enable UMD Pstate profile level for renoir
[AMD Official Use Only - General]
> -Original Message-
> From: Jesse Zhang
> Sent: Tuesday, May 7, 2024 11:43 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
> Subject: [PATCH 2/2] drm/amd/pm: enable UMD Pstate profile level for renoir
>
> This patch enable UMD Pstates profile
> level for the renoir_set_performance_level interface.
>
> -profile_min_sclk
> -profile_min_fclk
>
> Signed-off-by: Jesse Zhang
> Suggested-by: Tim Huang
> ---
> .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 58 +++
> 1 file changed, 48 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> index 8908bbb3ff1f..e56b7afb5b78 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> @@ -928,11 +928,55 @@ static int renoir_set_peak_clock_by_device(struct
> smu_context *smu)
> return ret;
> }
>
> +static int renior_set_dpm_profile_freq(struct smu_context *smu,
> + enum amd_dpm_forced_level level,
> + enum smu_clk_type clk_type) {
> + int ret = 0;
> + uint32_t sclk = 0, socclk = 0, fclk = 0;
> +
> + switch (clk_type) {
> + case SMU_GFXCLK:
> + case SMU_SCLK:
> + sclk = RENOIR_UMD_PSTATE_GFXCLK;
> + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> + renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
> &sclk);
> + else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
> + renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk,
> NULL);
> + break;
> + case SMU_SOCCLK:
> + socclk = RENOIR_UMD_PSTATE_SOCCLK;
> + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> + renoir_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL,
> &socclk);
> + break;
> + case SMU_FCLK:
We should add case SMU_MCLK here. With this fixed, you can add my FB.
Reviewed-by: Tim Huang
> + fclk = RENOIR_UMD_PSTATE_FCLK;
> + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> + renoir_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
> &fclk);
> + else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
> + renoir_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk,
> NULL);
> + break;
> + default:
> + ret = -EINVAL;
> + break;
> + }
> +
> + if (sclk)
> + ret = smu_v12_0_set_soft_freq_limited_range(smu,
> + SMU_SCLK, sclk, sclk);
> +
> + if (socclk)
> + ret = smu_v12_0_set_soft_freq_limited_range(smu,
> + SMU_SOCCLK, socclk, socclk);
> +
> + if (fclk)
> + ret = smu_v12_0_set_soft_freq_limited_range(smu,
> + SMU_FCLK, fclk, fclk);
> +
> + return ret;
> +}
> +
> static int renoir_set_performance_level(struct smu_context *smu,
> enum amd_dpm_forced_level level)
> {
> int ret = 0;
> - uint32_t sclk_mask, mclk_mask, soc_mask;
>
> switch (level) {
> case AMD_DPM_FORCED_LEVEL_HIGH:
> @@ -1012,15 +1056,9 @@ static int renoir_set_performance_level(struct
> smu_context *smu,
> smu->gfx_actual_hard_min_freq = smu-
> >gfx_default_hard_min_freq;
> smu->gfx_actual_soft_max_freq = smu-
> >gfx_default_soft_max_freq;
>
> - ret = renoir_get_profiling_clk_mask(smu, level,
> - &sclk_mask,
> - &mclk_mask,
> - &soc_mask);
> - if (ret)
> - return ret;
> - renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
> - renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
> - renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
> + renior_set_dpm_profile_freq(smu, level, SMU_SCLK);
> + renior_set_dpm_profile_freq(smu, level, SMU_MCLK);
> + renior_set_dpm_profile_freq(smu, level, SMU_SOCCLK);
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> smu->gfx_actual_hard_min_freq = smu-
> >gfx_default_hard_min_freq;
> --
> 2.25.1
RE: [PATCH 01/22] drm/amdgpu: fix dereference after null check
[AMD Official Use Only - General]
Reviewed-by: Tim Huang
> -Original Message-
> From: amd-gfx On Behalf Of Jesse
> Zhang
> Sent: Friday, May 10, 2024 10:50 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 01/22] drm/amdgpu: fix dereference after null check
>
> check the pointer hive before use.
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 77f6fd50002a..00fe3c2d5431 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -5725,7 +5725,7 @@ int amdgpu_device_gpu_recover(struct
> amdgpu_device *adev,
>* to put adev in the 1st position.
>*/
> INIT_LIST_HEAD(&device_list);
> - if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes >
> 1)) {
> + if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes >
> 1) && hive) {
> list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head)
> {
> list_add_tail(&tmp_adev->reset_list, &device_list);
> if (adev->shutdown)
> --
> 2.25.1
RE: [PATCH 03/22] drm/amdgpu: fix the waring dereferencing hive
[AMD Official Use Only - General]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: amd-gfx On Behalf Of Jesse
> Zhang
> Sent: Friday, May 10, 2024 10:50 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 03/22] drm/amdgpu: fix the waring dereferencing hive
>
> Check the amdgpu_hive_info *hive that maybe is NULL.
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 37820dd03cab..5a648a657dc6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -1362,6 +1362,9 @@ static void psp_xgmi_reflect_topology_info(struct
> psp_context *psp,
> uint8_t dst_num_links = node_info.num_links;
>
> hive = amdgpu_get_xgmi_hive(psp->adev);
> + if (WARN_ON(!hive))
> + return;
> +
> list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
> struct psp_xgmi_topology_info *mirror_top_info;
> int j;
> --
> 2.25.1
RE: [PATCH 04/22] drm/amd: fix the warning unchecking return vaule for sdma_v7
[AMD Official Use Only - General]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: amd-gfx On Behalf Of Jesse
> Zhang
> Sent: Friday, May 10, 2024 10:50 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 04/22] drm/amd: fix the warning unchecking return vaule for
> sdma_v7
>
> check ring allocate success before emit preempt ib
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> index 0b5af1c50461..7db53a96cff0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> @@ -1347,7 +1347,11 @@ static int sdma_v7_0_ring_preempt_ib(struct
> amdgpu_ring *ring)
>
> /* emit the trailing fence */
> ring->trail_seq += 1;
> - amdgpu_ring_alloc(ring, 10);
> + r = amdgpu_ring_alloc(ring, 10);
> + if (r) {
> + DRM_ERROR("ring %d failed to be allocated \n", ring->idx);
> + return r;
> + }
> sdma_v7_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
> ring->trail_seq, 0);
> amdgpu_ring_commit(ring);
> --
> 2.25.1
RE: [PATCH 05/22] drm/amd/pm: check specific index for aldebaran
[AMD Official Use Only - General]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: amd-gfx On Behalf Of Jesse
> Zhang
> Sent: Friday, May 10, 2024 10:50 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 05/22] drm/amd/pm: check specific index for aldebaran
>
> Check for specific indexes that may be invalid values.
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> index ce941fbb9cfb..a22eb6bbb05e 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> @@ -1886,7 +1886,8 @@ static int aldebaran_mode2_reset(struct
> smu_context *smu)
>
> index = smu_cmn_to_asic_specific_index(smu,
> CMN2ASIC_MAPPING_MSG,
> SMU_MSG_GfxDeviceDriverReset);
> -
> + if (index < 0 )
> + return -EINVAL;
> mutex_lock(&smu->message_lock);
> if (smu->smc_fw_version >= 0x00441400) {
> ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
> SMU_RESET_MODE_2);
> --
> 2.25.1
RE: [PATCH 09/22] drm/amd/pm: check specific index for smu13
[AMD Official Use Only - General] Hi Jesse, > -Original Message- > From: amd-gfx On Behalf Of Jesse > Zhang > Sent: Friday, May 10, 2024 10:50 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Huang, Tim ; Zhang, > Jesse(Jie) ; Zhang, Jesse(Jie) > > Subject: [PATCH 09/22] drm/amd/pm: check specific index for smu13 > > Check for specific indexes that may be invalid values. > > Signed-off-by: Jesse Zhang > --- > drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c > index 051092f1b1b4..7c343dd12a7f 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c > @@ -2336,6 +2336,8 @@ static int smu_v13_0_6_mode2_reset(struct > smu_context *smu) > > index = smu_cmn_to_asic_specific_index(smu, > CMN2ASIC_MAPPING_MSG, > SMU_MSG_GfxDeviceDriverReset); > + if (index < 0) > + ret = -EINVAL; We should need to return the index here? Tim > > mutex_lock(&smu->message_lock); > > -- > 2.25.1
RE: [PATCH 10/22] drm/amdgpu: remove structurally dead code
[AMD Official Use Only - General] This patch is, Reviewed-by: Tim Huang > -Original Message- > From: amd-gfx On Behalf Of Jesse > Zhang > Sent: Friday, May 10, 2024 10:50 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Huang, Tim ; Zhang, > Jesse(Jie) ; Zhang, Jesse(Jie) > > Subject: [PATCH 10/22] drm/amdgpu: remove structurally dead code > > This code cannot be reached: return "UNKNOWN";. > > Signed-off-by: Jesse Zhang > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h > index 9a946f0e015c..109f471ff315 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h > @@ -554,8 +554,6 @@ static inline const char > *amdgpu_gfx_compute_mode_desc(int mode) > default: > return "UNKNOWN"; > } > - > - return "UNKNOWN"; > } > > #endif > -- > 2.25.1
RE: [PATCH 11/22] drm/amdgpu: remove structurally dead code for amd_gmc
[AMD Official Use Only - General] This patch is, Reviewed-by: Tim Huang > -Original Message- > From: Jesse Zhang > Sent: Friday, May 10, 2024 10:50 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Huang, Tim ; Zhang, > Jesse(Jie) ; Zhang, Jesse(Jie) > > Subject: [PATCH 11/22] drm/amdgpu: remove structurally dead code for > amd_gmc > > This code cannot be reached: return sysfs_emit(buf, "UNK) > > Signed-off-by: Jesse Zhang > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > index a5f970fec242..f8ed886ffca3 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > @@ -1148,8 +1148,6 @@ static ssize_t current_memory_partition_show( > default: > return sysfs_emit(buf, "UNKNOWN\n"); > } > - > - return sysfs_emit(buf, "UNKNOWN\n"); > } > > static DEVICE_ATTR_RO(current_memory_partition); > -- > 2.25.1
RE: [PATCH 15/22] drm/amd/pm: fix enum feature compared against 0
[AMD Official Use Only - General]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: Jesse Zhang
> Sent: Friday, May 10, 2024 10:51 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 15/22] drm/amd/pm: fix enum feature compared against 0
>
> This less-than-zero comparison of an unsigned value is never true. feature <
> 0U
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> index 6d1c3af927ca..d439b95bfb79 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> @@ -760,7 +760,7 @@ static const char *__smu_feature_names[] =
> { static const char *smu_get_feature_name(struct smu_context *smu,
> enum smu_feature_mask feature)
> {
> - if (feature < 0 || feature >= SMU_FEATURE_COUNT)
> + if (feature >= SMU_FEATURE_COUNT)
> return "unknown smu feature";
> return __smu_feature_names[feature];
> }
> --
> 2.25.1
RE: [PATCH 14/22] drm/amdgu: remove unused code
[AMD Official Use Only - General]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: amd-gfx On Behalf Of Jesse
> Zhang
> Sent: Friday, May 10, 2024 10:51 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 14/22] drm/amdgu: remove unused code
>
> The same code is executed when the condition err is true or false, because the
> code in the if-then branch and after the if statement is identical
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 541dbd70d8c7..16d3deac375d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -963,8 +963,6 @@ static int gfx_v7_0_init_microcode(struct
> amdgpu_device *adev)
>
> snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
> err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
> - if (err)
> - goto out;
> out:
> if (err) {
> pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name);
> --
> 2.25.1
RE: [PATCH 16/22] drm/amd/pm: fix enum type compared against 0
[AMD Official Use Only - General]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: amd-gfx On Behalf Of Jesse
> Zhang
> Sent: Friday, May 10, 2024 10:51 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 16/22] drm/amd/pm: fix enum type compared against 0
>
> This less-than-zero comparison of an unsigned value is never true. type < 0U
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> index d439b95bfb79..602aa6941231 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> @@ -56,7 +56,7 @@ static const char * const __smu_message_names[] =
> { static const char *smu_get_message_name(struct smu_context *smu,
> enum smu_message_type type)
> {
> - if (type < 0 || type >= SMU_MSG_MAX_COUNT)
> + if (type >= SMU_MSG_MAX_COUNT)
> return "unknown smu message";
>
> return __smu_message_names[type];
> --
> 2.25.1
RE: [PATCH 19/22] drm/amdgpu: Fix the warning division or modulo by zero for the variable num_xcc_per_xcp
[AMD Official Use Only - General] This patch is, Reviewed-by: Tim Huang > -Original Message- > From: amd-gfx On Behalf Of Jesse > Zhang > Sent: Friday, May 10, 2024 10:51 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Huang, Tim ; Zhang, > Jesse(Jie) ; Zhang, Jesse(Jie) > > Subject: [PATCH 19/22] drm/amdgpu: Fix the warning division or modulo by > zero for the variable num_xcc_per_xcp > > Dividing expression num_xcc_per_xcp which may be zero has undefined > behavior. > > Signed-off-by: Jesse Zhang > --- > drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c > b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c > index 414ea3f560a7..5752c6760992 100644 > --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c > +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c > @@ -522,6 +522,9 @@ static int > aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, > goto unlock; > > num_xcc_per_xcp = __aqua_vanjaram_get_xcc_per_xcp(xcp_mgr, > mode); > + if (!num_xcc_per_xcp) > + goto unlock; > + > if (adev->gfx.funcs->switch_partition_mode) > adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev, > num_xcc_per_xcp); > -- > 2.25.1
RE: [PATCH 22/22] drm/amdgpu: clear the warning unsigned compared against 0 for xcp_id
[AMD Official Use Only - General]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: Jesse Zhang
> Sent: Friday, May 10, 2024 10:51 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 22/22] drm/amdgpu: clear the warning unsigned compared
> against 0 for xcp_id
>
> This greater-than-or-equal-to-zero comparison of an unsigned value is always
> true. fpriv->xcp_id >= 0U
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 977cde6d1362..66782be5917b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -618,7 +618,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void
> *data, struct drm_file *filp)
> return -EINVAL;
>
> if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 &&
> - fpriv->xcp_id >= 0 && fpriv->xcp_id <
> adev->xcp_mgr->num_xcps) {
> + fpriv->xcp_id < adev->xcp_mgr->num_xcps) {
> xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id];
> switch (type) {
> case AMD_IP_BLOCK_TYPE_GFX:
> --
> 2.25.1
RE: [PATCH 09/22 V2] drm/amd/pm: check specific index for smu13
[AMD Official Use Only - General] This patch is, Reviewed-by: Tim Huang > -Original Message- > From: Jesse Zhang > Sent: Friday, May 10, 2024 3:07 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Huang, Tim ; Zhang, > Jesse(Jie) ; Zhang, Jesse(Jie) > > Subject: [PATCH 09/22 V2] drm/amd/pm: check specific index for smu13 > > Check for specific indexes that may be invalid values. > > Signed-off-by: Jesse Zhang > Suggested-by: Tim Huang > --- > drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c > index 051092f1b1b4..7c343dd12a7f 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c > @@ -2336,6 +2336,8 @@ static int smu_v13_0_6_mode2_reset(struct > smu_context *smu) > > index = smu_cmn_to_asic_specific_index(smu, > CMN2ASIC_MAPPING_MSG, > SMU_MSG_GfxDeviceDriverReset); > + if (index < 0) > + return index; > > mutex_lock(&smu->message_lock); > > -- > 2.25.1
RE: [PATCH 06/22] drm/amd/pm: check the return of send smc msg for sienna_cichild
[AMD Official Use Only - General] This patch is, Reviewed-by: Tim Huang > -Original Message- > From: amd-gfx On Behalf Of Jesse > Zhang > Sent: Friday, May 10, 2024 10:50 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Huang, Tim ; Zhang, > Jesse(Jie) ; Zhang, Jesse(Jie) > > Subject: [PATCH 06/22] drm/amd/pm: check the return of send smc msg for > sienna_cichild > > Set smu work laod mask may fail, so check return. > > Signed-off-by: Jesse Zhang > --- > drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > index e426f457a017..e7ef8cb3a791 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > @@ -1782,8 +1782,10 @@ static int > sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long * > smu->power_profile_mode); > if (workload_type < 0) > return -EINVAL; > - smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetWorkloadMask, > + ret = smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetWorkloadMask, > 1 << workload_type, NULL); > + if (ret) > + dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", > __func__); > > return ret; > } > -- > 2.25.1
RE: [PATCH 07/22] drm/amd/pm: check the return of send smc msg for navi10
[AMD Official Use Only - General] This patch is, Reviewed-by: Tim Huang > -Original Message- > From: Jesse Zhang > Sent: Friday, May 10, 2024 10:50 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Huang, Tim ; Zhang, > Jesse(Jie) ; Zhang, Jesse(Jie) > > Subject: [PATCH 07/22] drm/amd/pm: check the return of send smc msg for > navi10 > > Set smu work laod mask may fail, so check return. > Signed-off-by: Jesse Zhang > --- > drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > index c06e0d6e3017..f30f1facc0f6 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > @@ -2081,9 +2081,11 @@ static int navi10_set_power_profile_mode(struct > smu_context *smu, long *input, u > smu->power_profile_mode); > if (workload_type < 0) > return -EINVAL; > - smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetWorkloadMask, > + ret = smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetWorkloadMask, > 1 << workload_type, NULL); > - > + if (ret) > + dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", > __func__); > + > return ret; > } > > -- > 2.25.1
RE: [PATCH 08/22] drm/amd/pm: check the return of send smc msg for smu_v13
[AMD Official Use Only - General] This patch is, Reviewed-by: Tim Huang > -Original Message- > From: amd-gfx On Behalf Of Jesse > Zhang > Sent: Friday, May 10, 2024 10:50 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Huang, Tim ; Zhang, > Jesse(Jie) ; Zhang, Jesse(Jie) > > Subject: [PATCH 08/22] drm/amd/pm: check the return of send smc msg for > smu_v13 > > Set smu work laod mask may fail, so check return. > > Signed-off-by: Jesse Zhang > --- > drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > index e996a0a4d33e..dcb68ab51fa0 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > @@ -2495,8 +2495,10 @@ static int > smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp > smu->power_profile_mode); > if (workload_type < 0) > return -EINVAL; > - smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetWorkloadMask, > + ret = smu_cmn_send_smc_msg_with_param(smu, > SMU_MSG_SetWorkloadMask, > 1 << workload_type, NULL); > + if (ret) > + dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", > __func__); > > return ret; > } > -- > 2.25.1
RE: [PATCH 18/22] drm/amd/pm: check negtive return for table entries
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Jesse,
> -Original Message-
> From: Zhang, Jesse(Jie)
> Sent: Monday, May 13, 2024 10:19 AM
> To: Zhang, Jesse(Jie) ;
> amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim
> Subject: RE: [PATCH 18/22] drm/amd/pm: check negtive return for table
> entries
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Ping ...
>
> -Original Message-
> From: Jesse Zhang
> Sent: Friday, May 10, 2024 10:51 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 18/22] drm/amd/pm: check negtive return for table entries
>
> Function hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr)
> returns a negative number
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
> index f4bd8e9357e2..4433ec4e9cf2 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
> @@ -30,9 +30,8 @@ int psm_init_power_state_table(struct pp_hwmgr
> *hwmgr) {
> int result;
> unsigned int i;
> - unsigned int table_entries;
> struct pp_power_state *state;
> - int size;
> + int size, table_entries;
>
> if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
> return 0;
> @@ -45,7 +44,7 @@ int psm_init_power_state_table(struct pp_hwmgr
> *hwmgr)
> hwmgr->ps_size = size =
> hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
> sizeof(struct
> pp_power_state);
>
> - if (table_entries == 0 || size == 0) {
> + if (table_entries <= 0 || size == 0) {
> pr_warn("Please check whether power state
> management is supported on this asic\n");
> return 0;
> }
We should need to check this before set the hwmgr->num_ps and hwmgr->ps_size,
otherwise we may have incorrect hwmgr->num_ps if meet the condition
table_entries < 0.
Tim Huang
> --
> 2.25.1
>
RE: [PATCH 02/22] drm/amdgpu: the warning dereferencing obj for nbio_v7_4
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Jesse,
> -Original Message-
> From: Zhang, Jesse(Jie)
> Sent: Monday, May 13, 2024 10:18 AM
> To: Zhang, Jesse(Jie) ;
> amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim
> Subject: RE: [PATCH 02/22] drm/amdgpu: the warning dereferencing obj for
> nbio_v7_4
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Ping ...
>
> -Original Message-
> From: Jesse Zhang
> Sent: Friday, May 10, 2024 10:50 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 02/22] drm/amdgpu: the warning dereferencing obj for
> nbio_v7_4
>
> if ras_manager obj null, don't print NBIO err data
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index fe18df10daaa..26e5885db9b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -383,7 +383,7 @@ static void
> nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
> else
> WREG32_SOC15(NBIO, 0,
> mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
>
> - if (!ras->disable_ras_err_cnt_harvest) {
> + if (!ras->disable_ras_err_cnt_harvest && obj) {
We may need to check the ras pointer as well? Such as change to " if (ras &&
!ras->disable_ras_err_cnt_harvest && obj) {"
Tim Huang
> /*
> * clear error status after ras_controller_intr
> * according to hw team and count ue number
> --
> 2.25.1
>
RE: [PATCH 2/22 V2] drm/amdgpu: the warning dereferencing obj for nbio_v7_4
[AMD Official Use Only - AMD Internal Distribution Only]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: Jesse Zhang
> Sent: Monday, May 13, 2024 3:33 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 2/22 V2] drm/amdgpu: the warning dereferencing obj for
> nbio_v7_4
>
> if ras_manager obj null, don't print NBIO err data
>
> Signed-off-by: Jesse Zhang
> Suggested-by: Tim Huang
> ---
> drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index fe18df10daaa..32cc60ce5521 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -383,7 +383,7 @@ static void
> nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
> else
> WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL,
> bif_doorbell_intr_cntl);
>
> - if (!ras->disable_ras_err_cnt_harvest) {
> + if (ras && !ras->disable_ras_err_cnt_harvest && obj) {
> /*
>* clear error status after ras_controller_intr
>* according to hw team and count ue number
> --
> 2.25.1
RE: [PATCH 18/22] drm/amd/pm: check negtive return for table entries
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Jesse,
> -Original Message-
> From: Jesse Zhang
> Sent: Monday, May 13, 2024 3:34 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Huang, Tim ; Zhang,
> Jesse(Jie) ; Zhang, Jesse(Jie)
>
> Subject: [PATCH 18/22] drm/amd/pm: check negtive return for table entries
>
> Function hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr)
> returns a negative number
>
> Signed-off-by: Jesse Zhang
> Suggested-by: Tim Huang
> ---
> drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c | 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
> index f4bd8e9357e2..1276a95acc90 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c
> @@ -30,9 +30,8 @@ int psm_init_power_state_table(struct pp_hwmgr
> *hwmgr) {
> int result;
> unsigned int i;
> - unsigned int table_entries;
> struct pp_power_state *state;
> - int size;
> + int size, table_entries;
>
> if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
> return 0;
> @@ -40,15 +39,17 @@ int psm_init_power_state_table(struct pp_hwmgr
> *hwmgr)
> if (hwmgr->hwmgr_func->get_power_state_size == NULL)
> return 0;
>
> - hwmgr->num_ps = table_entries =
> hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
> + table_entries =
> hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
>
> - hwmgr->ps_size = size =
> hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
> + size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
> sizeof(struct pp_power_state);
>
> - if (table_entries == 0 || size == 0) {
> + if (table_entries <= 0 || size == 0) {
> pr_warn("Please check whether power state management is
> supported on this asic\n");
As we return 0 here, we still need to set the hwmgr->num_ps and hwmgr->ps_size
to 0 here.
Tim Huang
> return 0;
> }
> + hwmgr->num_ps = table_entries;
> + hwmgr->ps_size = size;
>
> hwmgr->ps = kcalloc(table_entries, size, GFP_KERNEL);
> if (hwmgr->ps == NULL)
> --
> 2.25.1
RE: [PATCH 2/2] drm/amdgpu: update ATHUB_MISC_CNTL offset for nbio v3.3
[AMD Official Use Only - General] Hi Yifan, -Original Message- From: amd-gfx On Behalf Of Yifan Zhang Sent: Tuesday, January 9, 2024 10:06 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Zhang, Yifan ; Yu, Lang ; Ma, Li Subject: [PATCH 2/2] drm/amdgpu: update ATHUB_MISC_CNTL offset for nbio v3.3 This patch to update ATHUB_MISC_CNTL offset for nbio v3.3 Signed-off-by: Yifan Zhang Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/athub_v3_0.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c index f0737fb3a999..644dbae9f1d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c @@ -30,6 +30,8 @@ #define regATHUB_MISC_CNTL_V3_0_1 0x00d7 #define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX 0 +#define regATHUB_MISC_CNTL_V3_3_0 0x00d8 +#define regATHUB_MISC_CNTL_V3_3_0_BASE_IDX 0 static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev) @@ -40,6 +42,9 @@ static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev) case IP_VERSION(3, 0, 1): data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1); break; + case IP_VERSION(3, 3, 0): + data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0); + break; default: data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL); break; @@ -53,6 +58,9 @@ static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data) case IP_VERSION(3, 0, 1): WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1, data); break; + case IP_VERSION(3, 3, 0): + data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0); Is this a typo? It should be WREG32_SOC15. Thanks. Best Regards, Tim Huang + break; default: WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data); break; -- 2.37.3
RE: [PATCH v2 2/2] drm/amdgpu: update ATHUB_MISC_CNTL offset for nbio v3.3
[Public] Series is Reviewed-by: Tim Huang Best Regards, Tim Huang -Original Message- From: Zhang, Yifan Sent: Tuesday, January 9, 2024 11:01 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Yu, Lang ; Ma, Li ; Huang, Tim ; Zhang, Yifan Subject: [PATCH v2 2/2] drm/amdgpu: update ATHUB_MISC_CNTL offset for nbio v3.3 This patch to update ATHUB_MISC_CNTL offset for nbio v3.3 v2: correct a type (Tim) Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/athub_v3_0.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c index f0737fb3a999..d1bba9c64e16 100644 --- a/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c @@ -30,6 +30,8 @@ #define regATHUB_MISC_CNTL_V3_0_1 0x00d7 #define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX 0 +#define regATHUB_MISC_CNTL_V3_3_0 0x00d8 +#define regATHUB_MISC_CNTL_V3_3_0_BASE_IDX 0 static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev) @@ -40,6 +42,9 @@ static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev) case IP_VERSION(3, 0, 1): data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1); break; + case IP_VERSION(3, 3, 0): + data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0); + break; default: data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL); break; @@ -53,6 +58,9 @@ static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data) case IP_VERSION(3, 0, 1): WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1, data); break; + case IP_VERSION(3, 3, 0): + WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0, data); + break; default: WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data); break; -- 2.37.3
RE: [PATCH] drm/amdgpu: update regGL2C_CTRL4 value in golden setting
[Public]
Reviewed-by: Tim Huang
-Original Message-
From: Zhang, Yifan
Sent: Wednesday, January 10, 2024 8:56 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Yu, Lang ;
Ma, Li ; Huang, Tim ; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: update regGL2C_CTRL4 value in golden setting
This patch to update regGL2C_CTRL4 in golden setting.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 36c4efd89dc5..43dec9dfb3fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -119,7 +119,7 @@ static const struct soc15_reg_golden
golden_settings_gc_11_5_0[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_ADDR_MATCH_MASK, 0x,
0xfff3),
SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL, 0x, 0xf37fff3f),
SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xfffb, 0x00f40188),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ff, 0x8000b007),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ff, 0x80009007),
SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf1ff, 0x00880007),
SOC15_REG_GOLDEN_VALUE(GC, 0, regPC_CONFIG_CNTL_1, 0x,
0x0001),
SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7, 0x0103),
--
2.37.3
RE: [PATCH] drm/amdgpu: remove imu start dependency on amdgpu_dpm.
[Public]
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
-Original Message-
From: Zhang, Yifan
Sent: Saturday, January 20, 2024 4:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Feng, Kenneth
; Huang, Tim ; Ma, Li ;
Zhang, Yifan
Subject: [PATCH] drm/amdgpu: remove imu start dependency on amdgpu_dpm.
IMU starts anyway when dpm is disabled in backdoor loading.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index a2d3cced8f19..c5b1d036c95d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4324,7 +4324,7 @@ static int gfx_v11_0_hw_init(void *handle)
return r;
} else {
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
- if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
+ if (adev->gfx.imu.funcs) {
if (adev->gfx.imu.funcs->load_microcode)
adev->gfx.imu.funcs->load_microcode(adev);
if (adev->gfx.imu.funcs->setup_imu)
--
2.37.3
Re: [PATCH] drm/amd/pm: skip the RLC stop when S0i3 suspend for SMU v13.0.4/11
[AMD Official Use Only - General]
From: Limonciello, Mario
Sent: Friday, July 28, 2023 9:14 AM
To: Huang, Tim ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
Subject: Re: [PATCH] drm/amd/pm: skip the RLC stop when S0i3 suspend for SMU
v13.0.4/11
On 7/27/23 20:05, Tim Huang wrote:
> From: Tim Huang
>
> For SMU v13.0.4/11, driver does not need to stop RLC for S0i3,
> the firmwares will handle that properly.
> Conceptually I'm aligned to this.
> But, just to confirm, have you already run some testing with this
> with current GPU F/W, BIOS and either 6.1.y, 6.4.y or ASDN?
> I checked with this on my side and saw success but I'm fearful
> that it introduces some of the fence expiration problems we
> had in the past and I'm just not seeing them for some reason.
Yes, verified based on current BIOS and latest drm-next kernel and the working
FWs as the latest FWs
may have some new issues.
For this patch, it is asked by the FW guys, driver should not touch RLC_CNTL in
S0i3, let RLC FW to do that. If driver programs RLC_CNTL to halt RLC, RLC
cannot go GFXOFF exit sequence.
The fence expiration should be still there by the delayed GFXOFF , but this
patch should be useful to help debug it as it avoids the system hang when the
issue happens.
Best Regards,
Tim
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index ce41a8309582..222af2fae745 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1581,9 +1581,9 @@ static int smu_disable_dpms(struct smu_context *smu)
>
>/*
> * For SMU 13.0.4/11, PMFW will handle the features disablement
> properly
> - * for gpu reset case. Driver involvement is unnecessary.
> + * for gpu reset and S0i3 cases. Driver involvement is unnecessary.
> */
> - if (amdgpu_in_reset(adev)) {
> + if (amdgpu_in_reset(adev) || adev->in_s0ix) {
>switch (adev->ip_versions[MP1_HWIP][0]) {
>case IP_VERSION(13, 0, 4):
>case IP_VERSION(13, 0, 11):
Re: [PATCH] drm/amd/pm: skip the RLC stop when S0i3 suspend for SMU v13.0.4/11
[AMD Official Use Only - General]
From: Limonciello, Mario
Sent: Friday, July 28, 2023 10:39 AM
To: Huang, Tim ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
Subject: Re: [PATCH] drm/amd/pm: skip the RLC stop when S0i3 suspend for SMU
v13.0.4/11
On 7/27/23 21:21, Huang, Tim wrote:
> [AMD Official Use Only - General]
>
>
>
> *From:* Limonciello, Mario
> *Sent:* Friday, July 28, 2023 9:14 AM
> *To:* Huang, Tim ; amd-gfx@lists.freedesktop.org
>
> *Cc:* Deucher, Alexander ; Zhang, Yifan
>
> *Subject:* Re: [PATCH] drm/amd/pm: skip the RLC stop when S0i3 suspend
> for SMU v13.0.4/11
> On 7/27/23 20:05, Tim Huang wrote:
>> From: Tim Huang
>>
>> For SMU v13.0.4/11, driver does not need to stop RLC for S0i3,
>> the firmwares will handle that properly.
>> Conceptually I'm aligned to this.
>> But, just to confirm, have you already run some testing with this
>> with current GPU F/W, BIOS and either 6.1.y, 6.4.y or ASDN?
>
>> I checked with this on my side and saw success but I'm fearful
>> that it introduces some of the fence expiration problems we
>> had in the past and I'm just not seeing them for some reason.
>
> Yes, verified based on current BIOS and latest drm-next kernel and the
> working FWs as the latest FWs
> may have some new issues.
> For this patch, it is asked by the FW guys, driver should not touch
> RLC_CNTL in S0i3, let RLC FW to do that. If driver programs RLC_CNTL to
> halt RLC, RLC cannot go GFXOFF exit sequence.
>
> The fence expiration should be still there by the delayed GFXOFF , but
> this patch should be useful to help debug it as it avoids the system
> hang when the issue happens.
> So in that case you think that when the driver programs RLC_CNTL but
> GFXOFF was delayed sequence was going out of order and it triggered
> system hang. But now with this patch it will not hang but fences expire.
> It makes sense to me. This patch shouldn't be any "more" harmful then.
> Reviewed-by: Mario Limonciello
> For the delayed GFXOFF issue maybe we should revisit my previous idea
> for flushing GFXOFF requests. IIRC the most recent version was:
>
> https://patchwork.freedesktop.org/patch/537888/?series=117965&rev=1
I agree. We can add this patch to the latest test build and check whether the
issue is gone.
Thanks.
>
> Best Regards,
> Tim
>
>>
>> Signed-off-by: Tim Huang
>> ---
>> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> index ce41a8309582..222af2fae745 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> @@ -1581,9 +1581,9 @@ static int smu_disable_dpms(struct smu_context *smu)
>>
>>/*
>> * For SMU 13.0.4/11, PMFW will handle the features disablement
>> properly
>> - * for gpu reset case. Driver involvement is unnecessary.
>> + * for gpu reset and S0i3 cases. Driver involvement is unnecessary.
>> */
>> - if (amdgpu_in_reset(adev)) {
>> + if (amdgpu_in_reset(adev) || adev->in_s0ix) {
>>switch (adev->ip_versions[MP1_HWIP][0]) {
>>case IP_VERSION(13, 0, 4):
>>case IP_VERSION(13, 0, 11):
>
RE: [PATCH] drm/amdgpu: Fix APU handling in amdgpu_pm_load_smu_firmware()
[Public]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: Deucher, Alexander
> Sent: Friday, July 26, 2024 5:36 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Tim
>
> Subject: [PATCH] drm/amdgpu: Fix APU handling in
> amdgpu_pm_load_smu_firmware()
>
> We only need to skip this on modern APUs. It's required on older APUs as it's
> where start_smu gets called from.
>
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3502
> Fixes: 064d92436b69 ("drm/amd/pm: avoid to load smu firmware for APUs")
> Signed-off-by: Alex Deucher
> Cc: Tim Huang
> ---
> drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> index f78b4f013ed4..62df787d7b28 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> @@ -631,7 +631,8 @@ int amdgpu_pm_load_smu_firmware(struct
> amdgpu_device *adev, uint32_t *smu_versio
> const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
> int r = 0;
>
> - if (!pp_funcs || !pp_funcs->load_firmware || adev->flags & AMD_IS_APU)
> + if (!pp_funcs || !pp_funcs->load_firmware ||
> + (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU)))
> return 0;
>
> mutex_lock(&adev->pm.mutex);
> --
> 2.45.2
RE: [PATCH] drm/amdgpu: use CPU for page table update if SDMA is unavailable
[Public]
This patch is,
Reviewed-by: Tim Huang
> -Original Message-
> From: amd-gfx On Behalf Of Yifan
> Zhang
> Sent: Tuesday, July 30, 2024 12:37 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Jesse(Jie)
> ; Zhang, Yifan
> Subject: [PATCH] drm/amdgpu: use CPU for page table update if SDMA is
> unavailable
>
> avoid using SDMA if it is unavailable.
>
> Signed-off-by: Yifan Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index a060c28f0877..bcb729094521 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2397,6 +2397,7 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm
> *vm) int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm
> *vm,
> int32_t xcp_id)
> {
> + struct amdgpu_ip_block *ip_block;
> struct amdgpu_bo *root_bo;
> struct amdgpu_bo_vm *root;
> int r, i;
> @@ -2426,6 +2427,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev,
> struct amdgpu_vm *vm,
> vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
> AMDGPU_VM_USE_CPU_FOR_GFX);
>
> + /* use CPU for page table update if SDMA is unavailable */
> + ip_block = amdgpu_device_ip_get_ip_block(adev,
> AMD_IP_BLOCK_TYPE_SDMA);
> + if (!ip_block || ip_block->status.valid == false)
> + vm->use_cpu_for_update = true;
> +
> DRM_DEBUG_DRIVER("VM update mode is %s\n",
>vm->use_cpu_for_update ? "CPU" : "SDMA");
> WARN_ONCE((vm->use_cpu_for_update &&
> --
> 2.37.3
RE: [PATCH v2] drm/amdgpu/mes: zero the sdma_hqd_mask of 2nd SDMA engine for SDMA 6.0.1
[AMD Official Use Only - General]
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
-Original Message-
From: Zhang, Yifan
Sent: Wednesday, August 31, 2022 8:56 AM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Tim ; Deucher, Alexander
; Du, Xiaojian ; Xiao, Jack
; Zhang, Yifan
Subject: [PATCH v2] drm/amdgpu/mes: zero the sdma_hqd_mask of 2nd SDMA engine
for SDMA 6.0.1
there is only one SDMA engine in SDMA 6.0.1, the sdma_hqd_mask has to be zeroed
for the 2nd engine, otherwise MES scheduler will consider 2nd engine exists and
map/unmap SDMA queues to the non-existent engine.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index fe82b8b19a4e..0c546245793b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -181,6 +181,9 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
if (adev->ip_versions[SDMA0_HWIP][0] < IP_VERSION(6, 0, 0))
adev->mes.sdma_hqd_mask[i] = i ? 0 : 0x3fc;
+ /* zero sdma_hqd_mask for non-existent engine */
+ else if (adev->sdma.num_instances == 1)
+ adev->mes.sdma_hqd_mask[i] = i ? 0 : 0xfc;
else
adev->mes.sdma_hqd_mask[i] = 0xfc;
}
--
2.37.1
RE: [PATCH] drm/amdkfd: Match GC 11.0.1 cache info to yellow carp
[Public] Reviewed-by: Tim Huang Best Regards, Tim Huang -Original Message- From: Zhang, Yifan Sent: Thursday, September 1, 2022 3:30 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Huang, Tim ; Du, Xiaojian ; Zhang, Yifan Subject: [PATCH] drm/amdkfd: Match GC 11.0.1 cache info to yellow carp Current discovery table doesn't have cache info for GC 11.0.1, thus can't be parsed like other GC 11, this patch to match GC 11.0.1 cache info to yellow carp Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index 24b414cff3ec..1c500bfb0b28 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -1516,11 +1516,11 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev, case IP_VERSION(10, 3, 3): case IP_VERSION(10, 3, 6): /* TODO: Double check these on production silicon */ case IP_VERSION(10, 3, 7): /* TODO: Double check these on production silicon */ + case IP_VERSION(11, 0, 1): /* TODO: Double check these on production +silicon */ pcache_info = yellow_carp_cache_info; num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info); break; case IP_VERSION(11, 0, 0): - case IP_VERSION(11, 0, 1): case IP_VERSION(11, 0, 2): case IP_VERSION(11, 0, 3): pcache_info = cache_info; -- 2.37.1
RE: [PATCH] drm/amdgpu: add MES and MES-KIQ version in debugfs
[AMD Official Use Only - General]
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
-Original Message-
From: Zhang, Yifan
Sent: Friday, September 16, 2022 12:39 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Tim
; Du, Xiaojian ; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: add MES and MES-KIQ version in debugfs
This patch addes MES and MES-KIQ version in debugfs.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 24
include/uapi/drm/amdgpu_drm.h | 4
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 1369c25448dc..bb0ed358909f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -328,6 +328,14 @@ static int amdgpu_firmware_info(struct
drm_amdgpu_info_firmware *fw_info,
fw_info->ver = adev->psp.cap_fw_version;
fw_info->feature = adev->psp.cap_feature_version;
break;
+ case AMDGPU_INFO_FW_MES_KIQ:
+ fw_info->ver = adev->mes.ucode_fw_version[0];
+ fw_info->feature = 0;
+ break;
+ case AMDGPU_INFO_FW_MES:
+ fw_info->ver = adev->mes.ucode_fw_version[1];
+ fw_info->feature = 0;
+ break;
default:
return -EINVAL;
}
@@ -1581,6 +1589,22 @@ static int amdgpu_debugfs_firmware_info_show(struct
seq_file *m, void *unused)
fw_info.feature, fw_info.ver);
}
+ /* MES_KIQ */
+ query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
+ ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
+ if (ret)
+ return ret;
+ seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
+ fw_info.feature, fw_info.ver);
+
+ /* MES */
+ query_fw.fw_type = AMDGPU_INFO_FW_MES;
+ ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
+ if (ret)
+ return ret;
+ seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
+ fw_info.feature, fw_info.ver);
+
seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
return 0;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index c2c9c674a223..12fdf62730b8 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -755,6 +755,10 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_FW_TOC 0x15
/* Subquery id: Query CAP firmware version */
#define AMDGPU_INFO_FW_CAP 0x16
+ /* Subquery id: Query MES_KIQ firmware version */
+ #define AMDGPU_INFO_FW_MES_KIQ 0x17
+ /* Subquery id: Query MES firmware version */
+ #define AMDGPU_INFO_FW_MES 0x18
/* number of bytes moved for TTM migration */
#define AMDGPU_INFO_NUM_BYTES_MOVED0x0f
--
2.37.3
RE: [PATCH 1/2] drm/amdgpu: add tmz support for GC 11.0.1
[AMD Official Use Only - General]
Series is
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
-Original Message-
From: amd-gfx On Behalf Of Yifan Zhang
Sent: Sunday, October 9, 2022 2:40 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Tim
; Du, Xiaojian ; Zhang, Yifan
Subject: [PATCH 1/2] drm/amdgpu: add tmz support for GC 11.0.1
this patch to add tmz support for GC 11.0.1.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 34233a74248c..9c0d9baab4e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -542,6 +542,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
case IP_VERSION(10, 3, 1):
/* YELLOW_CARP*/
case IP_VERSION(10, 3, 3):
+ case IP_VERSION(11, 0, 1):
/* Don't enable it by default yet.
*/
if (amdgpu_tmz < 1) {
--
2.37.3
RE: [1/2] drm/amd/pm: update SMU IP v13.0.4 driver interface version
[Public]
Hi Mario,
Comments inline. Thanks.
Best Regards,
Tim Huang
-Original Message-
From: Limonciello, Mario
Sent: Friday, October 14, 2022 5:35 AM
To: Huang, Tim ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Du, Xiaojian ; Gong, Richard
Subject: Re: [1/2] drm/amd/pm: update SMU IP v13.0.4 driver interface version
On 10/13/2022 00:46, Tim Huang wrote:
> Update the SMU driver interface version to V7.
>
> Signed-off-by: Tim Huang
> ---
> .../swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h | 17 +++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h
> index ae2d337158f3..f77401709d83 100644
> ---
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4
> +++ .h
> @@ -27,7 +27,7 @@
> // *** IMPORTANT ***
> // SMU TEAM: Always increment the interface version if
> // any structure is changed in this file -#define
> PMFW_DRIVER_IF_VERSION 5
> +#define PMFW_DRIVER_IF_VERSION 7
>
> typedef struct {
> int32_t value;
> @@ -163,8 +163,8 @@ typedef struct {
> uint16_t DclkFrequency; //[MHz]
> uint16_t MemclkFrequency; //[MHz]
> uint16_t spare; //[centi]
> - uint16_t UvdActivity; //[centi]
> uint16_t GfxActivity; //[centi]
> + uint16_t UvdActivity; //[centi]
This is unfortunate, it means that these two flipped based on PMFW driver
interface version!
With 13.0.4 in 6.0, this should probably come back.
>> This flipping already happened in the PMFW driver interface version V6. So,
>> should notice this compatible issue from V6.
Cc: sta...@vger.kernel.org #6.0
Reviewed-by: Mario Limonciello
>
> uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC
> uint16_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_SOC
> @@ -199,6 +199,19 @@ typedef struct {
> uint16_t DeviceState;
> uint16_t CurTemp; //[centi-Celsius]
> uint16_t spare2;
> +
> + uint16_t AverageGfxclkFrequency;
> + uint16_t AverageFclkFrequency;
> + uint16_t AverageGfxActivity;
> + uint16_t AverageSocclkFrequency;
> + uint16_t AverageVclkFrequency;
> + uint16_t AverageVcnActivity;
> + uint16_t AverageDRAMReads; //Filtered DF Bandwidth::DRAM Reads
> + uint16_t AverageDRAMWrites; //Filtered DF Bandwidth::DRAM Writes
> + uint16_t AverageSocketPower;//Filtered value of CurrentSocketPower
> + uint16_t AverageCorePower; //Filtered of [sum of CorePower[8]])
> + uint16_t AverageCoreC0Residency[8]; //Filtered of [average C0 residency %
> per core]
> + uint32_t MetricsCounter;//Counts the # of metrics table
> parameter reads per update to the metrics table, i.e. if the metrics table
> update happens every 1 second, this value could be up to 1000 if the smu
> collected metrics data every cycle, or as low as 0 if the smu was asleep the
> whole time. Reset to 0 after writing.
> } SmuMetrics_t;
>
> typedef struct {
RE: [PATCH v2] drm/amdgpu: set fb_modifiers_not_supported in vkms
[Public] Reviewed-by: Tim Huang Best Regards, Tim Huang -Original Message- From: amd-gfx On Behalf Of Yifan Zhang Sent: Monday, October 24, 2022 12:51 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Zhang, Yifan ; Wentland, Harry ; Koenig, Christian ; Chen, Guchun Subject: [PATCH v2] drm/amdgpu: set fb_modifiers_not_supported in vkms This patch to fix the gdm3 start failure with virual display: /usr/libexec/gdm-x-session[1711]: (II) AMDGPU(0): Setting screen physical size to 270 x 203 /usr/libexec/gdm-x-session[1711]: (EE) AMDGPU(0): Failed to make import prime FD as pixmap: 22 /usr/libexec/gdm-x-session[1711]: (EE) AMDGPU(0): failed to set mode: Invalid argument /usr/libexec/gdm-x-session[1711]: (WW) AMDGPU(0): Failed to set mode on CRTC 0 /usr/libexec/gdm-x-session[1711]: (EE) AMDGPU(0): Failed to enable any CRTC gnome-shell[1840]: Running GNOME Shell (using mutter 42.2) as a X11 window and compositing manager /usr/libexec/gdm-x-session[1711]: (EE) AMDGPU(0): failed to set mode: Invalid argument vkms doesn't have modifiers support, set fb_modifiers_not_supported to bring the gdm back. Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 576849e95296..f69827aefb57 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -500,6 +500,8 @@ static int amdgpu_vkms_sw_init(void *handle) adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base; + adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; + r = amdgpu_display_modeset_create_props(adev); if (r) return r; -- 2.37.3
RE: [PATCH] drm/amdgpu: force read discovery file if set discovery=2
[Public]
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
-Original Message-
From: Zhang, Yifan
Sent: Wednesday, October 26, 2022 11:14 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Tim
; Du, Xiaojian ; Liu, Aaron
; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: force read discovery file if set discovery=2
If discovery is set to 2 in module parameters explicitly, the intention is to
use the discovery file in FW rather than the one in BIOS, usually because the
latter is incorrect. This patch to force read discovery file if set discovery=2.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 3993e6134914..5ea9afaaf4f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -305,8 +305,13 @@ static int amdgpu_discovery_init(struct amdgpu_device
*adev)
goto out;
}
- if
(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
- dev_warn(adev->dev, "get invalid ip discovery binary signature
from vram\n");
+ if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)
|| amdgpu_discovery == 2) {
+ /* ignore the discovery binary from vram if discovery=2 in
kernel module parameter */
+ if (amdgpu_discovery == 2)
+ dev_info(adev->dev,"force read ip discovery binary from
file");
+ else
+ dev_warn(adev->dev, "get invalid ip discovery binary
signature from
+vram\n");
+
/* retry read ip discovery binary from file */
r = amdgpu_discovery_read_binary_from_file(adev,
adev->mman.discovery_bin);
if (r) {
--
2.37.3
RE: [PATCH] drm/amdgpu: change gfx 11.0.4 external_id range
[AMD Official Use Only - General]
This patch is
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
-Original Message-
From: Zhang, Yifan
Sent: Wednesday, May 10, 2023 4:38 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Tim
; Du, Xiaojian ; Limonciello, Mario
; Mohan Marimuthu, Yogesh
; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: change gfx 11.0.4 external_id range
gfx 11.0.4 range starts from 0x80.
Fixes: 311d52367d0a ("drm/amdgpu: add soc21 common ip block support for GC
11.0.4")
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 0f82b8e83acb..6bff936a6e55 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -711,7 +711,7 @@ static int soc21_common_early_init(void *handle)
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_GFX_PG |
AMD_PG_SUPPORT_JPEG;
- adev->external_rev_id = adev->rev_id + 0x1;
+ adev->external_rev_id = adev->rev_id + 0x80;
break;
default:
--
2.37.3
RE: [PATCH 2/3] drm/amd: Poll for GFX core to be off
[AMD Official Use Only - General]
Hi Lijo,
Yes, the GFX_IMU_MSG_FLAGS is outside of GFXOFF domain. It can be accessed when
GFXOFF is entry.
Best Regards,
Tim Huang
-Original Message-
From: Lazar, Lijo
Sent: Wednesday, May 17, 2023 10:48 AM
To: Limonciello, Mario ;
amd-gfx@lists.freedesktop.org
Cc: Tsao, Anson ; Huang, Tim ; Martinez,
Juan ; Limonciello, Mario ;
Gong, Richard
Subject: RE: [PATCH 2/3] drm/amd: Poll for GFX core to be off
[AMD Official Use Only - General]
Is this register GFX_IMU_MSG_FLAGS outside of GFXOFF domain?
Thanks,
Lijo
-Original Message-
From: amd-gfx On Behalf Of Mario
Limonciello
Sent: Tuesday, May 16, 2023 11:22 PM
To: amd-gfx@lists.freedesktop.org
Cc: Tsao, Anson ; Huang, Tim ; Martinez,
Juan ; Limonciello, Mario ;
Gong, Richard
Subject: [PATCH 2/3] drm/amd: Poll for GFX core to be off
If GFXOFF was flushed during suspend entry it may take some time for GFX core
to be powered down. Ensure that it's powered off before continuing any
operations that may try to utilize related IP. This avoids hangs from stopping
RLC as well as problems with fence interrupts timing out during s2idle entry
and exit.
Cc: sta...@vger.kernel.org # 6.1+
Tested-by: Juan Martinez
Tested-by: Anson Tsao
Suggested-by: Tim Huang
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 20 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 18 ++
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
3 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 059139f1f973..17fc053405ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3055,12 +3055,28 @@ static void amdgpu_device_delay_enable_gfx_off(struct
work_struct *work) {
struct amdgpu_device *adev =
container_of(work, struct amdgpu_device,
gfx.gfx_off_delay_work.work);
+ int r, i;
WARN_ON_ONCE(adev->gfx.gfx_off_state);
WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
- if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX,
true))
- adev->gfx.gfx_off_state = true;
+ r = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX,
true);
+ if (r) {
+ DRM_ERROR("failed to enable gfxoff: %d\n", r);
+ return;
+ }
+ for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
+ if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_GFX)
+ continue;
+ if (!adev->ip_blocks[i].version->funcs->wait_for_off)
+ continue;
+ r = adev->ip_blocks[i].version->funcs->wait_for_off((void
*)adev);
+ if (r) {
+ DRM_ERROR("failed to wait for gfxoff: %d\n", r);
+ return;
+ }
+ }
+ adev->gfx.gfx_off_state = true;
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 4b7224de879e..dcbdb2641086 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4434,6 +4434,23 @@ static int gfx_v11_0_wait_for_idle(void *handle)
return -ETIMEDOUT;
}
+
+static int gfx_v11_0_wait_for_off(void *handle) {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ u32 tmp;
+ int i;
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ tmp = RREG32_SOC15(GC, 0, regGFX_IMU_MSG_FLAGS);
+ if (!(tmp & 0x06))
+ return 0;
+ udelay(1);
+ }
+ dev_dbg(adev->dev, "GFX IMU is %x\n", tmp);
+ return -ETIMEDOUT;
+}
+
static int gfx_v11_0_soft_reset(void *handle) {
u32 grbm_soft_reset = 0;
@@ -6109,6 +6126,7 @@ static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
.resume = gfx_v11_0_resume,
.is_idle = gfx_v11_0_is_idle,
.wait_for_idle = gfx_v11_0_wait_for_idle,
+ .wait_for_off = gfx_v11_0_wait_for_off,
.soft_reset = gfx_v11_0_soft_reset,
.check_soft_reset = gfx_v11_0_check_soft_reset,
.post_soft_reset = gfx_v11_0_post_soft_reset, diff --git
a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index f175e65b853a..ce2e2b6fd6ff 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -298,6 +298,7 @@ struct amd_ip_funcs {
int (*resume)(void *handle);
bool (*is_idle)(void *handle);
int (*wait_for_idle)(void *handle);
+ int (*wait_for_off)(void *handle);
bool (*check_soft_reset)(void *handle);
int (*pre_soft_reset)(void *handle);
int (*soft_reset)(void *handle);
--
2.34.1
Re: [PATCH 4/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for vangogh
[AMD Official Use Only - General]
Thanks Alex.
Renoir didn't use the DFPstateTable but it needs to reverse the clocks levels
as well.
Will send out a new patch for Renoir.
Best Regards,
Tim
From: Alex Deucher
Sent: Monday, May 22, 2023 9:19 PM
To: Huang, Tim
Cc: amd-gfx@lists.freedesktop.org ; Deucher,
Alexander ; Zhang, Yifan
Subject: Re: [PATCH 4/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for
vangogh
Reviewed-by: Alex Deucher
Does Renoir need a similar fix?
Alex
On Mon, May 22, 2023 at 6:10 AM Tim Huang wrote:
>
> This patch reverses the DPM clocks levels output of pp_dpm_mclk
> and pp_dpm_fclk.
>
> On dGPUs and older APUs we expose the levels from lowest clocks
> to highest clocks. But for some APUs, the clocks levels that from
> the DFPstateTable are given the reversed orders by PMFW. Like the
> memory DPM clocks that are exposed by pp_dpm_mclk.
>
> It's not intuitive that they are reversed on these APUs. All tools
> and software that talks to the driver then has to know different ways
> to interpret the data depending on the asic.
>
> So we need to reverse them to expose the clocks levels from the
> driver consistently.
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 7433dcaa16e0..067b4e0b026c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -582,7 +582,7 @@ static int vangogh_print_legacy_clk_levels(struct
> smu_context *smu,
> DpmClocks_t *clk_table = smu->smu_table.clocks_table;
> SmuMetrics_legacy_t metrics;
> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> - int i, size = 0, ret = 0;
> + int i, idx, size = 0, ret = 0;
> uint32_t cur_value = 0, value = 0, count = 0;
> bool cur_value_match_level = false;
>
> @@ -656,7 +656,8 @@ static int vangogh_print_legacy_clk_levels(struct
> smu_context *smu,
> case SMU_MCLK:
> case SMU_FCLK:
> for (i = 0; i < count; i++) {
> - ret = vangogh_get_dpm_clk_limited(smu, clk_type, i,
> &value);
> + idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK)
> ? (count - i - 1) : i;
> + ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx,
> &value);
> if (ret)
> return ret;
> if (!value)
> @@ -683,7 +684,7 @@ static int vangogh_print_clk_levels(struct smu_context
> *smu,
> DpmClocks_t *clk_table = smu->smu_table.clocks_table;
> SmuMetrics_t metrics;
> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> - int i, size = 0, ret = 0;
> + int i, idx, size = 0, ret = 0;
> uint32_t cur_value = 0, value = 0, count = 0;
> bool cur_value_match_level = false;
> uint32_t min, max;
> @@ -765,7 +766,8 @@ static int vangogh_print_clk_levels(struct smu_context
> *smu,
> case SMU_MCLK:
> case SMU_FCLK:
> for (i = 0; i < count; i++) {
> - ret = vangogh_get_dpm_clk_limited(smu, clk_type, i,
> &value);
> + idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK)
> ? (count - i - 1) : i;
> + ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx,
> &value);
> if (ret)
> return ret;
> if (!value)
> --
> 2.34.1
>
Re: [PATCH] drm/amd/pm: enable more Pstates profile levels for yellow_carp
[AMD Official Use Only - General]
Hi Shikai,
Comments inline.
From: Guo, Shikai
Sent: Wednesday, June 7, 2023 7:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liang, Prike ; Liu, Aaron ; Huang,
Tim ; Guo, Shikai
Subject: [PATCH] drm/amd/pm: enable more Pstates profile levels for yellow_carp
This patch enables following UMD stable Pstates profile levels for
power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: shikaguo
---
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 94 ++-
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h | 8 +-
2 files changed, 98 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index a92da336ecec..5c968ab2ea8d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -957,6 +957,9 @@ static int yellow_carp_set_soft_freq_limited_range(struct
smu_context *smu,
uint32_t max)
{
enum smu_message_type msg_set_min, msg_set_max;
+ uint32_t min_clk = min;
+ uint32_t max_clk = max;
+
int ret = 0;
if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
@@ -985,11 +988,17 @@ static int yellow_carp_set_soft_freq_limited_range(struct
smu_context *smu,
return -EINVAL;
}
- ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
+ if (clk_type == SMU_VCLK) {
+ min_clk = min << SMU_13_VCLK_SHIFT;
+ max_clk = max << SMU_13_VCLK_SHIFT;
+ }
+
+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
+
if (ret)
goto out;
- ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
if (ret)
goto out;
@@ -1107,6 +1116,50 @@ static int yellow_carp_force_clk_levels(struct
smu_context *smu,
return ret;
}
+static int yellow_carp_get_dpm_profile_freq(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ enum smu_clk_type clk_type,
+ uint32_t *min_clk,
+ uint32_t *max_clk)
+{
+ int ret = 0;
+ uint32_t clk_limit = 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_GFXCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK,
&clk_limit, NULL);
+ break;
+ case SMU_SOCCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_SOCCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK,
NULL, &clk_limit);
+ break;
+ case SMU_FCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_FCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK,
&clk_limit, NULL);
+ break;
+ case SMU_VCLK:
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
&clk_limit);
+ break;
+ case SMU_DCLK:
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL,
&clk_limit);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ *min_clk = *max_clk = clk_limit;
+ return ret;
+}
+
static int yellow_carp_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level
level)
{
@@ -1114,6 +1167,9 @@ static int yellow_carp_set_performance_level(struct
smu_context *smu,
uint32_t sclk_min = 0, sclk_max = 0;
uint32_t fclk_min = 0, fclk_max = 0;
uint32_t socclk_min = 0, socclk_max = 0;
+ uint32_t vclk_min = 0, vclk_max = 0;
+ uint32_t dclk_min = 0, dclk_max = 0;
+
int ret = 0;
switch (level) {
@@ -1121,28 +1177,42 @@ static int yellow_carp_set_performance_level(struct
smu_context *smu,
yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&sclk_max);
yellow_carp_get_dpm_u
Re: [PATCH v2] drm/amd/pm: enable more Pstates profile levels for yellow_carp
[Public]
Hi Shikai,
From: Guo, Shikai
Sent: Thursday, June 8, 2023 11:27 AM
To: amd-gfx@lists.freedesktop.org
Cc: Liang, Prike ; Liu, Aaron ; Huang,
Tim ; Deucher, Alexander ; Guo,
Shikai
Subject: [PATCH v2] drm/amd/pm: enable more Pstates profile levels for
yellow_carp
This patch enables following UMD stable Pstates profile levels for
power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: shikaguo
---
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 94 ++-
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h | 5 +-
2 files changed, 95 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index a92da336ecec..5c968ab2ea8d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -957,6 +957,9 @@ static int yellow_carp_set_soft_freq_limited_range(struct
smu_context *smu,
uint32_t max)
{
enum smu_message_type msg_set_min, msg_set_max;
+ uint32_t min_clk = min;
+ uint32_t max_clk = max;
+
int ret = 0;
if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
@@ -985,11 +988,17 @@ static int yellow_carp_set_soft_freq_limited_range(struct
smu_context *smu,
return -EINVAL;
}
- ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
+ if (clk_type == SMU_VCLK) {
+ min_clk = min << SMU_13_VCLK_SHIFT;
+ max_clk = max << SMU_13_VCLK_SHIFT;
+ }
+
+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
+
if (ret)
goto out;
- ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
if (ret)
goto out;
@@ -1107,6 +1116,50 @@ static int yellow_carp_force_clk_levels(struct
smu_context *smu,
return ret;
}
+static int yellow_carp_get_dpm_profile_freq(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ enum smu_clk_type clk_type,
+ uint32_t *min_clk,
+ uint32_t *max_clk)
+{
+ int ret = 0;
+ uint32_t clk_limit = 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_GFXCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK,
&clk_limit, NULL);
+ break;
+ case SMU_SOCCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_SOCCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK,
NULL, &clk_limit);
+ break;
+ case SMU_FCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_FCLK;
This is shared by other APU ASICs, like the SMU v13.0.8. We should need to
apply the different profiling standard clocks for sclk/fclk/socclk according to
the IP version checking. Thanks.
Tim
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK,
&clk_limit, NULL);
+ break;
+ case SMU_VCLK:
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
&clk_limit);
+ break;
+ case SMU_DCLK:
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL,
&clk_limit);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ *min_clk = *max_clk = clk_limit;
+ return ret;
+}
+
static int yellow_carp_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level
level)
{
@@ -1114,6 +1167,9 @@ static int yellow_carp_set_performance_level(struct
smu_context *smu,
uint32_t sclk_min = 0, sclk_max = 0;
uint32_t fclk_min = 0, fclk_max = 0;
uint32_t socclk_min = 0, socclk_max = 0;
+ uint32_t vclk_min = 0, vclk_max = 0;
+ uint32_t dclk_min = 0, dclk_max = 0;
+
int ret = 0;
switch (level) {
@@ -1121,28 +1177,42 @@ static int yellow_carp_set_pe
Re: [PATCH v3] drm/amd/pm: enable more Pstates profile levels for yellow_carp
[Public]
Hi Shikai
From: Guo, Shikai
Sent: Thursday, June 8, 2023 6:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liang, Prike ; Liu, Aaron ; Huang,
Tim ; Deucher, Alexander ; Guo,
Shikai
Subject: [PATCH v3] drm/amd/pm: enable more Pstates profile levels for
yellow_carp
This patch enables following UMD stable Pstates profile levels for
power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: shikaguo
---
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 140 +-
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h | 1 -
2 files changed, 136 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index a92da336ecec..71566c60372f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -47,6 +47,14 @@
#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x0006L
#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1L
+#define SMU_13_0_8_UMD_PSTATE_GFXCLK 533
+#define SMU_13_0_8_UMD_PSTATE_SOCCLK 533
+#define SMU_13_0_8_UMD_PSTATE_FCLK 800
+
+#define SMU_13_0_1_UMD_PSTATE_GFXCLK 700
+#define SMU_13_0_1_UMD_PSTATE_SOCCLK 678
+#define SMU_13_0_1_UMD_PSTATE_FCLK 1800
+
#define FEATURE_MASK(feature) (1ULL << feature)
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@@ -957,6 +965,9 @@ static int yellow_carp_set_soft_freq_limited_range(struct
smu_context *smu,
uint32_t max)
{
enum smu_message_type msg_set_min, msg_set_max;
+ uint32_t min_clk = min;
+ uint32_t max_clk = max;
+
int ret = 0;
if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
@@ -985,11 +996,17 @@ static int yellow_carp_set_soft_freq_limited_range(struct
smu_context *smu,
return -EINVAL;
}
- ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
+ if (clk_type == SMU_VCLK) {
+ min_clk = min << SMU_13_VCLK_SHIFT;
+ max_clk = max << SMU_13_VCLK_SHIFT;
+ }
+
+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
+
if (ret)
goto out;
- ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
if (ret)
goto out;
@@ -997,12 +1014,48 @@ static int
yellow_carp_set_soft_freq_limited_range(struct smu_context *smu,
return ret;
}
+static int yellow_carp_get_umd_pstate_clk_default(struct smu_context *smu,
It should return uint32_t for the default clk. With this fixed, this patch is
Reviewed-by: Tim Huang
+ enum smu_clk_type clk_type)
+{
+ uint32_t clk_limit = 0;
+ struct amdgpu_device *adev = smu->adev;
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 8))
+ clk_limit = SMU_13_0_8_UMD_PSTATE_GFXCLK;
+ if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 1) ||
+ (adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0,
3))
+ clk_limit = SMU_13_0_1_UMD_PSTATE_GFXCLK;
+ break;
+ case SMU_SOCCLK:
+ if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 8))
+ clk_limit = SMU_13_0_8_UMD_PSTATE_SOCCLK;
+ if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 1) ||
+ (adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0,
3))
+ clk_limit = SMU_13_0_1_UMD_PSTATE_SOCCLK;
+ break;
+ case SMU_FCLK:
+ if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 8))
+ clk_limit = SMU_13_0_8_UMD_PSTATE_FCLK;
+ if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 1) ||
+ (adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0,
3))
+ clk_limit = SMU_13_0_1_UMD_PSTATE_FCLK;
+ break;
+ default:
+ break;
+ }
+
+ return clk_limit;
+}
+
static int yellow_carp_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf)
{
int i, idx, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
uint32_t min, max;
+ uint32_t clk_limit = 0;
smu_cmn_get_sysfs_buf
RE: [PATCH] drm/amdkfd: correct sdma queue number of sdma 6.0.1
[AMD Official Use Only - General] Reviewed-by: Tim Huang -Original Message- From: Zhang, Yifan Sent: Monday, June 20, 2022 4:42 PM To: amd-gfx@lists.freedesktop.org Cc: Huang, Ray ; Deucher, Alexander ; Huang, Tim ; Zhang, Yifan Subject: [PATCH] drm/amdkfd: correct sdma queue number of sdma 6.0.1 sdma 6.0.1 has 8 queues instead of 2. Fixes: 2f68559102cb (drm/amdkfd: add GC 11.0.1 KFD support) Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index bf4200457772..c8fee0dbfdcb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -75,7 +75,6 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ - case IP_VERSION(6, 0, 1): kfd->device_info.num_sdma_queues_per_engine = 2; break; case IP_VERSION(4, 2, 0):/* VEGA20 */ @@ -90,6 +89,7 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ case IP_VERSION(6, 0, 0): + case IP_VERSION(6, 0, 1): case IP_VERSION(6, 0, 2): kfd->device_info.num_sdma_queues_per_engine = 8; break; -- 2.35.1
RE: [PATCH] drm/amdgpu: correct RLC_RLCS_BOOTLOAD_STATUS offset and index
[AMD Official Use Only - General]
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
-Original Message-
From: Zhang, Yifan
Sent: Saturday, July 23, 2022 8:42 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Tim ; Deucher, Alexander
; Du, Xiaojian ; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: correct RLC_RLCS_BOOTLOAD_STATUS offset and index
this patch corrects RLC_RLCS_BOOTLOAD_STATUS offset and index for GC 11.0.1
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 0787a965615b..fb9aefb1b404 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -77,6 +77,9 @@
#define regICG_SQ_CLK_CTRL_BASE_IDX
1
#define regSPI_GFX_CRAWLER_CONFIG
0x1296
#define regSPI_GFX_CRAWLER_CONFIG_BASE_IDX
0
+#define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1
0x4e7e
+#define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX
1
+
MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");
MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
@@ -2800,7 +2803,10 @@ static int
gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
for (i = 0; i < adev->usec_timeout; i++) {
cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
- bootload_status = RREG32_SOC15(GC, 0,
regRLC_RLCS_BOOTLOAD_STATUS);
+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1))
+ bootload_status = RREG32_SOC15(GC, 0,
regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
+ else
+ bootload_status = RREG32_SOC15(GC, 0,
regRLC_RLCS_BOOTLOAD_STATUS);
if ((cp_status == 0) &&
(REG_GET_FIELD(bootload_status,
RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
--
2.37.1
RE: [PATCH 1/5] drm/amdgpu: send msg to IMU for the front-door loading
Hi Xiaojian,
Please move the power up IPU to "smu->is_apu" as Evan' comment and make sure
this is only called for PSP FW load type as
backdoor loading already included this in the IMU start process. After this,
Series is
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
-Original Message-
From: Quan, Evan
Sent: Thursday, July 28, 2022 4:14 PM
To: Du, Xiaojian ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Tim
; Du, Xiaojian ; Zhang, Yifan
Subject: RE: [PATCH 1/5] drm/amdgpu: send msg to IMU for the front-door loading
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of
> Xiaojian Du
> Sent: Thursday, July 28, 2022 3:04 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Tim
> ; Du, Xiaojian ; Zhang, Yifan
>
> Subject: [PATCH 1/5] drm/amdgpu: send msg to IMU for the front-door
> loading
>
> This patch will make SMU send msg to IMU for the front-door loading,
> it is required by some ASICs.
>
> Signed-off-by: Yifan Zhang
> Signed-off-by: Xiaojian Du
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 6d9b3c6af164..79c01fa4b875 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1360,6 +1360,14 @@ static int smu_hw_init(void *handle)
> return ret;
> }
>
> + if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
> + ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
> + if (ret) {
> + dev_err(adev->dev, "Failed to Enable gfx imu!\n");
> + return ret;
> + }
> + }
[Quan, Evan] Per my understandings, this should be needed by APU only. Can you
move this under "smu->is_apu" control as other features below?
Evan
> +
> if (smu->is_apu) {
> smu_dpm_set_vcn_enable(smu, true);
> smu_dpm_set_jpeg_enable(smu, true);
> --
> 2.25.1
RE: [PATCH 1/2] drm/amdgpu: enable GFX Power Gating for GC IP v11.0.1
[AMD Official Use Only - General]
Hi Alex,
Yes, we need to call amdgpu_gfx_off_ctrl(adev, enable) as well, but now the
GFXOFF feature is still not ready
on the FW side. I will add some comments about this and resend this patch to
avoid confusion.
Best Regards,
Tim Huang
-Original Message-
From: Alex Deucher
Sent: Tuesday, August 9, 2022 4:13 AM
To: Huang, Tim
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Yifan ; Du, Xiaojian
Subject: Re: [PATCH 1/2] drm/amdgpu: enable GFX Power Gating for GC IP v11.0.1
On Mon, Aug 8, 2022 at 6:32 AM Tim Huang wrote:
>
> Enable GFX Power Gating control for GC IP v11.0.1.
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 35
> ++
> 1 file changed, 35 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index e03618803a1c..319f07f61be5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -53,6 +53,7 @@
> #define GFX11_MEC_HPD_SIZE 2048
>
> #define RLCG_UCODE_LOADING_START_ADDRESS 0x2000L
> +#define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388
>
> #define regCGTT_WD_CLK_CTRL0x5086
> #define regCGTT_WD_CLK_CTRL_BASE_IDX 1
> @@ -5279,6 +5280,38 @@ static const struct amdgpu_rlc_funcs
> gfx_v11_0_rlc_funcs = {
> .update_spm_vmid = gfx_v11_0_update_spm_vmid, };
>
> +static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev,
> +bool enable) {
> + u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
> +
> + if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
> + data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> + else
> + data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> +
> + WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);
> +
> + // Program RLC_PG_DELAY3 for CGPG hysteresis
> + if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(11, 0, 1):
> + WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3,
> RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
> + break;
> + default:
> + break;
> + }
> + }
> +}
> +
> +static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
> +{
> + amdgpu_gfx_rlc_enter_safe_mode(adev);
> +
> + gfx_v11_cntl_power_gating(adev, enable);
> +
> + amdgpu_gfx_rlc_exit_safe_mode(adev);
> +}
> +
> static int gfx_v11_0_set_powergating_state(void *handle,
>enum amd_powergating_state
> state) { @@ -5293,6 +5326,8 @@ static int
> gfx_v11_0_set_powergating_state(void *handle,
> case IP_VERSION(11, 0, 2):
> amdgpu_gfx_off_ctrl(adev, enable);
> break;
> + case IP_VERSION(11, 0, 1):
> + gfx_v11_cntl_pg(adev, enable);
do we need to call amdgpu_gfx_off_ctrl(adev, enable); here as well?
Alex
> default:
> break;
> }
> --
> 2.25.1
>
RE: [PATCH v2] drm/amdkfd: reserve 2 queues for sdma 6.0.1
[AMD Official Use Only - General]
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
-Original Message-
From: amd-gfx On Behalf Of Yifan Zhang
Sent: Thursday, August 11, 2022 8:46 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Joshi, Mukul
; Kuehling, Felix ; Zhang, Yifan
Subject: [PATCH v2] drm/amdkfd: reserve 2 queues for sdma 6.0.1
There is only one engine in sdma 6.0.1, the total number of reserved queues
should be 2.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index f5853835f03a..357298e69495 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -102,13 +102,18 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev
*kfd)
switch (sdma_version) {
case IP_VERSION(6, 0, 0):
- case IP_VERSION(6, 0, 1):
case IP_VERSION(6, 0, 2):
/* Reserve 1 for paging and 1 for gfx */
kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
/* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0;
BIT(2)=engine-0 queue-1; ... */
kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL;
break;
+ case IP_VERSION(6, 0, 1):
+ /* Reserve 1 for paging and 1 for gfx */
+ kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
+ /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */
+ kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL;
+ break;
default:
break;
}
--
2.37.1
RE: drm/amdgpu: skip mes self test after s0i3 resume for MES IP v11.0
[AMD Official Use Only - General]
Hi Mario,
Comments inline. Thanks.
-Original Message-
From: Limonciello, Mario
Sent: Monday, December 19, 2022 11:22 PM
To: Huang, Tim ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Ma, Li ; Du, Xiaojian
Subject: Re: drm/amdgpu: skip mes self test after s0i3 resume for MES IP v11.0
On 12/19/2022 06:12, Tim Huang wrote:
> MES is part of gfxoff for S0i3 and does not require self-test after S0i3.
> Besides, self-test will free the BO that triggers a wraning while in
> the suspend state.
>
> [ 81.656085] WARNING: CPU: 2 PID: 1550 at
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:425
> amdgpu_bo_free_kernel+0xfc/0x110 [amdgpu]
> [ 81.679435] Call Trace:
> [ 81.679726]
> [ 81.679981] amdgpu_mes_remove_hw_queue+0x17a/0x230 [amdgpu]
> [ 81.680857] amdgpu_mes_self_test+0x390/0x430 [amdgpu]
> [ 81.681665] mes_v11_0_late_init+0x37/0x50 [amdgpu]
> [ 81.682423] amdgpu_device_ip_late_init+0x53/0x280 [amdgpu]
> [ 81.683257] amdgpu_device_resume+0xae/0x2a0 [amdgpu]
> [ 81.684043] amdgpu_pmops_resume+0x37/0x70 [amdgpu]
> [ 81.684818] pci_pm_resume+0x5c/0xa0
> [ 81.685247] ? pci_pm_thaw+0x90/0x90
> [ 81.685658] dpm_run_callback+0x4e/0x160
> [ 81.686110] device_resume+0xad/0x210
> [ 81.686529] async_resume+0x1e/0x40
> [ 81.686931] async_run_entry_fn+0x33/0x120
> [ 81.687405] process_one_work+0x21d/0x3f0
> [ 81.687869] worker_thread+0x4a/0x3c0
> [ 81.688293] ? process_one_work+0x3f0/0x3f0
> [ 81.688777] kthread+0xff/0x130
> [ 81.689157] ? kthread_complete_and_exit+0x20/0x20
> [ 81.689707] ret_from_fork+0x22/0x30
> [ 81.690118]
> [ 81.690380] ---[ end trace ]---
Is this still needed with https://patchwork.freedesktop.org/patch/515278/ ?
Patch 515278 skipped the MES suspend and resume, But the self-test stilled be
called by ip late init. Please get detail for patch v2.
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index 5459366f49ff..80e8cf826e71 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -1342,7 +1342,7 @@ static int mes_v11_0_late_init(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - if (!amdgpu_in_reset(adev) &&
> + if (!amdgpu_in_reset(adev) && !adev->in_suspend &&
I think in this case you should be using adev->in_s0ix instead.
Yes, adev->in_s0ix should be better, thanks for pointing that out.
> (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3)))
> amdgpu_mes_self_test(adev);
>
RE: [PATCH 2/2] drm/amd/pm: drop unneeded dpm features disablement for SMU 13.0.4/11
[Public] Hi Mario, -Original Message- From: Limonciello, Mario Sent: Saturday, January 21, 2023 12:36 AM To: Huang, Tim ; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Zhang, Yifan ; Du, Xiaojian ; Ma, Li Subject: RE: [PATCH 2/2] drm/amd/pm: drop unneeded dpm features disablement for SMU 13.0.4/11 [Public] > -Original Message- > From: Huang, Tim > Sent: Friday, January 20, 2023 10:29 > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Zhang, Yifan > ; Du, Xiaojian ; Ma, Li > ; Limonciello, Mario ; > Huang, Tim > Subject: [PATCH 2/2] drm/amd/pm: drop unneeded dpm features > disablement for SMU 13.0.4/11 > > PMFW will handle that properly. Driver involvement may cause some > unexpected issues. > > Signed-off-by: Tim Huang > --- > drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c > b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c > index ec52830dde24..800eb5ad1dcb 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c > @@ -1448,6 +1448,8 @@ static int smu_disable_dpms(struct smu_context > *smu) > case IP_VERSION(13, 0, 0): > case IP_VERSION(13, 0, 7): > case IP_VERSION(13, 0, 10): > + case IP_VERSION(13, 0, 4): > To keep a consistent ordering scheme, I think IP_VERSION(13, 0, 4) should > come after IP_VERION(13, 0, 0). Thanks for point out that, but I will drop this patch and send a new one to apply it only for gpu reset case. w/ that fixed: Reviewed-by: Mario Limonciello 6.1 is used for IP_VERSION(13, 0, 4), so please also include Cc: sta...@vger.kernel.org #6.1 > + case IP_VERSION(13, 0, 11): > return 0; > default: > break; > -- > 2.25.1
RE: [PATCH] drm/amdgpu: skip ASIC reset for GC IP v11.0.4/11 when go to S4
[AMD Official Use Only - General]
Please ignore this patch, will send out a new one to skip ASIC reset for all
APUs. Thanks.
-Original Message-
From: Huang, Tim
Sent: Monday, March 13, 2023 7:42 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Du, Xiaojian ; Ma, Li
; Limonciello, Mario ; Huang, Tim
Subject: [PATCH] drm/amdgpu: skip ASIC reset for GC IP v11.0.4/11 when go to S4
[Why]
For GC IP v11.0.4/11, PSP TMR need to be reserved for ASIC mode2 reset. But for
S4, when psp suspend, it will destroy the TMR that fails the ASIC reset.
[ 96.006101] amdgpu :62:00.0: amdgpu: MODE2 reset [ 100.409717] amdgpu
:62:00.0: amdgpu: SMU: I'm not done with your previous command:
SMN_C2PMSG_66:0x0011 SMN_C2PMSG_82:0x0002 [ 100.411593] amdgpu
:62:00.0: amdgpu: Mode2 reset failed!
[ 100.412470] amdgpu :62:00.0: PM: pci_pm_freeze():
amdgpu_pmops_freeze+0x0/0x50 [amdgpu] returns -62 [ 100.414020] amdgpu
:62:00.0: PM: dpm_run_callback(): pci_pm_freeze+0x0/0xd0 returns -62 [
100.415311] amdgpu :62:00.0: PM: pci_pm_freeze+0x0/0xd0 returned -62 after
4623202 usecs [ 100.416608] amdgpu :62:00.0: PM: failed to freeze async:
error -62
[How]
Skip the ASIC reset for S4, assuming we can resume properly without reset.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 8fa9a36c38b6..ba02b0d9ef7e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -980,6 +980,8 @@ static int smu_v13_0_4_set_performance_level(struct
smu_context *smu,
static int smu_v13_0_4_mode2_reset(struct smu_context *smu) {
+ if (!amdgpu_in_reset(smu->adev)) /* Skip the reset for S4 */
+ return 0;
return smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GfxDeviceDriverReset,
SMU_RESET_MODE_2, NULL);
}
--
2.25.1
RE: [PATCH 1/2] drm/amdgpu: reposition the gpu reset checking for reuse
[Public]
-Original Message-
From: Alex Deucher
Sent: Wednesday, March 15, 2023 10:36 PM
To: Huang, Tim
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Yifan ; Limonciello,
Mario
Subject: Re: [PATCH 1/2] drm/amdgpu: reposition the gpu reset checking for reuse
On Wed, Mar 15, 2023 at 7:05 AM Tim Huang wrote:
>
> Move the amdgpu_acpi_should_gpu_reset out of CONFIG_SUSPEND to share
> it with hibernate case.
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +--
> drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 40
> +---
> 2 files changed, 24 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 5c6132502f35..5bddc03332b3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1392,10 +1392,12 @@ int amdgpu_acpi_smart_shift_update(struct
> drm_device *dev, enum amdgpu_ss ss_sta int
> amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
>
> void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps
> *caps);
> +bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
> void amdgpu_acpi_detect(void);
> #else
> static inline int amdgpu_acpi_init(struct amdgpu_device *adev) {
> return 0; } static inline void amdgpu_acpi_fini(struct amdgpu_device
> *adev) { }
> +static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device
> +*adev) { return false; }
> static inline void amdgpu_acpi_detect(void) { } static inline bool
> amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
> static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device
> *adev, @@ -1406,11 +1408,9 @@ static inline int
> amdgpu_acpi_smart_shift_update(struct drm_device *dev,
>
> #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) bool
> amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); -bool
> amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); bool
> amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); #else static
> inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) {
> return false; } -static inline bool
> amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return
> false; } static inline bool amdgpu_acpi_is_s3_active(struct
> amdgpu_device *adev) { return false; } #endif
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> index 25e902077caf..065944bdeee4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> @@ -971,6 +971,28 @@ static bool amdgpu_atcs_pci_probe_handle(struct pci_dev
> *pdev)
> return true;
> }
>
> +
> +/**
> + * amdgpu_acpi_should_gpu_reset
> + *
> + * @adev: amdgpu_device_pointer
> + *
> + * returns true if should reset GPU, false if not */ bool
> +amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) {
> + if (adev->flags & AMD_IS_APU)
> + return false;
> +
> + if (amdgpu_sriov_vf(adev))
> + return false;
> +
> +#if IS_ENABLED(CONFIG_SUSPEND)
> + return pm_suspend_target_state != PM_SUSPEND_TO_IDLE; #endif
> +/* CONFIG_SUSPEND */
> + return true;
Should probably be:
#if IS_ENABLED(CONFIG_SUSPEND)
return pm_suspend_target_state != PM_SUSPEND_TO_IDLE; #else
return true;
#endif
Yes, will fix it. Thanks Alex.
With that fixed, series is:
Reviewed-by: Alex Deucher
> +}
> +
> /*
> * amdgpu_acpi_detect - detect ACPI ATIF/ATCS methods
> *
> @@ -1042,24 +1064,6 @@ bool amdgpu_acpi_is_s3_active(struct amdgpu_device
> *adev)
> (pm_suspend_target_state == PM_SUSPEND_MEM); }
>
> -/**
> - * amdgpu_acpi_should_gpu_reset
> - *
> - * @adev: amdgpu_device_pointer
> - *
> - * returns true if should reset GPU, false if not
> - */
> -bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) -{
> - if (adev->flags & AMD_IS_APU)
> - return false;
> -
> - if (amdgpu_sriov_vf(adev))
> - return false;
> -
> - return pm_suspend_target_state != PM_SUSPEND_TO_IDLE;
> -}
> -
> /**
> * amdgpu_acpi_is_s0ix_active
> *
> --
> 2.25.1
>
RE: [PATCH] drm/amd/pm: re-enable the gfx imu when smu resume
[Public]
-Original Message-
From: Quan, Evan
Sent: Friday, March 24, 2023 3:17 PM
To: Huang, Tim ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Ma, Li ; Du, Xiaojian
; Huang, Tim
Subject: RE: [PATCH] drm/amd/pm: re-enable the gfx imu when smu resume
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of Tim
> Huang
> Sent: Friday, March 24, 2023 3:08 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
> ; Ma, Li ; Du, Xiaojian
> ; Huang, Tim
> Subject: [PATCH] drm/amd/pm: re-enable the gfx imu when smu resume
>
> If the gfx imu is poweroff when suspend, then it need to be re-enabled
> when resume.
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 40
> ---
> 1 file changed, 28 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index b5d64749990e..94fe8593444a 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -162,10 +162,15 @@ int smu_get_dpm_freq_range(struct smu_context
> *smu,
>
> int smu_set_gfx_power_up_by_imu(struct smu_context *smu) {
> - if (!smu->ppt_funcs || !smu->ppt_funcs-
> >set_gfx_power_up_by_imu)
> - return -EOPNOTSUPP;
>> This assumes that all APUs need to support the ->set_gfx_power_up_by_imu int
>> interface.
>> Otherwise, the driver loading will fail?
>>Is that expected?
>> Evan
Only the GFX11 APUs that have the IMU need to support the
->set_gfx_power_up_by_imu interface.
Before it should be ok as it only be used for backdoor FW loading in
imu_v11_0.c, now It will be used for more case,
then return EOPNOTSUPP should not be expected. Thanks.
Tim
> + int ret = 0;
> + struct amdgpu_device *adev = smu->adev;
>
> - return smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
> + if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
> + ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
> + if (ret)
> + dev_err(adev->dev, "Failed to enable gfx imu!\n");
> + }
> + return ret;
> }
>
> static u32 smu_get_mclk(void *handle, bool low) @@ -196,6 +201,19 @@
> static u32 smu_get_sclk(void *handle, bool low)
> return clk_freq * 100;
> }
>
> +static int smu_set_gfx_imu_enable(struct smu_context *smu) {
> + struct amdgpu_device *adev = smu->adev;
> +
> + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
> + return 0;
> +
> + if (amdgpu_in_reset(smu->adev) || adev->in_s0ix)
> + return 0;
> +
> + return smu_set_gfx_power_up_by_imu(smu); }
> +
> static int smu_dpm_set_vcn_enable(struct smu_context *smu,
> bool enable)
> {
> @@ -1396,15 +1414,9 @@ static int smu_hw_init(void *handle)
> }
>
> if (smu->is_apu) {
> - if ((smu->ppt_funcs->set_gfx_power_up_by_imu) &&
> - likely(adev->firmware.load_type ==
> AMDGPU_FW_LOAD_PSP)) {
> - ret = smu->ppt_funcs-
> >set_gfx_power_up_by_imu(smu);
> - if (ret) {
> - dev_err(adev->dev, "Failed to Enable gfx
> imu!\n");
> - return ret;
> - }
> - }
> -
> + ret = smu_set_gfx_imu_enable(smu);
> + if (ret)
> + return ret;
> smu_dpm_set_vcn_enable(smu, true);
> smu_dpm_set_jpeg_enable(smu, true);
> smu_set_gfx_cgpg(smu, true);
> @@ -1681,6 +1693,10 @@ static int smu_resume(void *handle)
> return ret;
> }
>
> + ret = smu_set_gfx_imu_enable(smu);
> + if (ret)
> + return ret;
> +
> smu_set_gfx_cgpg(smu, true);
>
> smu->disable_uclk_switch = 0;
> --
> 2.25.1
RE: [PATCH] drm/amd/pm: re-enable the gfx imu when smu resume
[Public]
-Original Message-
From: Chen, Guchun
Sent: Friday, March 24, 2023 3:26 PM
To: Huang, Tim ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Ma, Li ; Du, Xiaojian
; Huang, Tim
Subject: RE: [PATCH] drm/amd/pm: re-enable the gfx imu when smu resume
> -Original Message-
> From: amd-gfx On Behalf Of Tim
> Huang
> Sent: Friday, March 24, 2023 3:08 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
> ; Ma, Li ; Du, Xiaojian
> ; Huang, Tim
> Subject: [PATCH] drm/amd/pm: re-enable the gfx imu when smu resume
>
> If the gfx imu is poweroff when suspend, then it need to be re-enabled
> when resume.
>
> Signed-off-by: Tim Huang
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 40 -
> --
> 1 file changed, 28 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index b5d64749990e..94fe8593444a 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -162,10 +162,15 @@ int smu_get_dpm_freq_range(struct smu_context
> *smu,
>
> int smu_set_gfx_power_up_by_imu(struct smu_context *smu) {
> - if (!smu->ppt_funcs || !smu->ppt_funcs->set_gfx_power_up_by_imu)
> - return -EOPNOTSUPP;
> + int ret = 0;
> + struct amdgpu_device *adev = smu->adev;
>
> - return smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
> + if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
> + ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
> + if (ret)
> + dev_err(adev->dev, "Failed to enable gfx imu!\n");
> + }
> + return ret;
> }
>
> static u32 smu_get_mclk(void *handle, bool low) @@ -196,6 +201,19 @@
> static u32 smu_get_sclk(void *handle, bool low)
> return clk_freq * 100;
> }
>
> +static int smu_set_gfx_imu_enable(struct smu_context *smu) {
> + struct amdgpu_device *adev = smu->adev;
> +
> + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
> + return 0;
> +
> + if (amdgpu_in_reset(smu->adev) || adev->in_s0ix)
> + return 0;
> +
> + return smu_set_gfx_power_up_by_imu(smu); }
> +
> static int smu_dpm_set_vcn_enable(struct smu_context *smu,
> bool enable)
> {
> @@ -1396,15 +1414,9 @@ static int smu_hw_init(void *handle)
> }
>
> if (smu->is_apu) {
> - if ((smu->ppt_funcs->set_gfx_power_up_by_imu) &&
> - likely(adev->firmware.load_type ==
> AMDGPU_FW_LOAD_PSP)) {
> - ret = smu->ppt_funcs-
> >set_gfx_power_up_by_imu(smu);
> - if (ret) {
> - dev_err(adev->dev, "Failed to Enable gfx
> imu!\n");
> - return ret;
> - }
> - }
> -
> + ret = smu_set_gfx_imu_enable(smu);
> + if (ret)
> + return ret;
> smu_dpm_set_vcn_enable(smu, true);
> smu_dpm_set_jpeg_enable(smu, true);
> smu_set_gfx_cgpg(smu, true);
> @@ -1681,6 +1693,10 @@ static int smu_resume(void *handle)
> return ret;
> }
>
> + ret = smu_set_gfx_imu_enable(smu);
> + if (ret)
> + return ret;
>> smu_set_gfx_imu_enable in smu_hw_init is valid when sum->is_apu is true. So
>> such check is still necessary in smu_resume?
>>Regards,
>>Guchun
For both hw_init or resume, it should be ok if not have the smu->is_apu
checking. Because we will check the valid of
smu->ppt_funcs->set_gfx_power_up_by_imu in the final call path,
so, for dGPU or APUs without IMU that did not implement this interface will
return 0. Thanks.
Tim
> smu_set_gfx_cgpg(smu, true);
>
> smu->disable_uclk_switch = 0;
> --
> 2.25.1
