[PATCH 23/24] drm/amd/display: Fix POWERPC_64 compilation
From: Roman Li
[Why]
Compilation errors while compiling without CONFIG_DRM_AMD_DC_FP:
"undefined reference to `dc_bandwidth_in_kbps_from_timing'"
[How]
Fix Makefile to move dsc files out of DC_FP guard.
Fixes: 50253f5d9ff4 ("drm/amd/display: Add misc DC changes for DCN401")
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dsc/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
index 66ea5f104019..94883c4e4c61 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
@@ -29,6 +29,7 @@ DSC_DCN401 += dcn401_dsc.o
AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn401/,$(DSC_DCN401))
+endif
DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o
@@ -36,4 +37,3 @@ AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
AMD_DISPLAY_FILES += $(AMD_DAL_DSC)
-endif
--
2.34.1
[PATCH 24/24] drm/amd/display: 3.2.286
From: Aric Cyr This version pairs with DMUB FW Release 0.0.218.0 for dcn314/315/316, dcn35/351, dcn401 and brings along the following: - Fix powerpc compilation - Fix TBT+TypeC Daisy-chain lightup - Fix ODM combine setup - Fix OTC underflow on dcn35 - Fix DVI config for dcn401 - Add ips status info to debugfs - Add 3DLUT DMA load trigger - Modify clock programming to support DPM - Disable dcn401 idle optimizations Acked-by: Roman Li Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5ae74558632b..a711e3fd6f1b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.285" +#define DC_VER "3.2.286" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.34.1
[PATCH 19/24] drm/amd/display: Fix ODM + underscan case with cursor
From: Alvin Lee
[Description]
There is a corner case where we're in an ODM config that
has recout.x != 0. In these scenarios we have to take into
account the extra offset in the ODM adjustment for cursor.
Reviewed-by: Aric Cyr
Acked-by: Roman Li
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c| 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index a619da7716ed..f5333a095adb 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1089,7 +1089,9 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) ||
(pipe_ctx->prev_odm_pipe != NULL);
int prev_odm_width = 0;
+ int prev_odm_offset = 0;
int next_odm_width = 0;
+ int next_odm_offset = 0;
int x_pos = pos_cpy.x;
int y_pos = pos_cpy.y;
@@ -1152,22 +1154,26 @@ void dcn401_set_cursor_position(struct pipe_ctx
*pipe_ctx)
y_pos += pipe_ctx->plane_state->src_rect.y;
}
- /* Adjust for ODM Combine */
+ /* Adjust for ODM Combine
+* next/prev_odm_offset is to account for scaled modes that have
underscan
+*/
if (odm_combine_on) {
struct pipe_ctx *next_odm_pipe = pipe_ctx->next_odm_pipe;
struct pipe_ctx *prev_odm_pipe = pipe_ctx->prev_odm_pipe;
while (next_odm_pipe != NULL) {
next_odm_width +=
next_odm_pipe->plane_res.scl_data.recout.width;
+ next_odm_offset +=
next_odm_pipe->plane_res.scl_data.recout.x;
next_odm_pipe = next_odm_pipe->next_odm_pipe;
}
while (prev_odm_pipe != NULL) {
prev_odm_width +=
prev_odm_pipe->plane_res.scl_data.recout.width;
+ prev_odm_offset +=
prev_odm_pipe->plane_res.scl_data.recout.x;
prev_odm_pipe = prev_odm_pipe->prev_odm_pipe;
}
if (param.rotation == ROTATION_ANGLE_0) {
- x_pos -= prev_odm_width;
+ x_pos -= (prev_odm_width + prev_odm_offset);
}
}
@@ -1269,7 +1275,7 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
pos_cpy.y += pos_cpy_x_offset;
} else {
- pos_cpy.x =
pipe_ctx->plane_res.scl_data.recout.width + next_odm_width - pos_cpy.y;
+ pos_cpy.x =
pipe_ctx->plane_res.scl_data.recout.width + next_odm_width + next_odm_offset -
pos_cpy.y;
pos_cpy.y = temp_x;
}
} else {
--
2.34.1
[PATCH 14/24] drm/amd/display: Clear shared dmub firmware state on init
From: Roman Li [Why] Reset the shared dmub firmware region on dmub hw init to start with known state. [How] Memset the shared region to 0 in dmub_hw_init(). Suggested-by: Nicholas Kazlauskas Reviewed-by: Nicholas Kazlauskas Signed-off-by: Roman Li --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 616c0aa73224..53dc4c75fb75 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1207,6 +1207,9 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); + memset(fb_info->fb[DMUB_WINDOW_SHARED_STATE].cpu_addr, 0, + fb_info->fb[DMUB_WINDOW_SHARED_STATE].size); + /* Initialize hardware. */ memset(_params, 0, sizeof(hw_params)); hw_params.fb_base = adev->gmc.fb_start; -- 2.34.1
[PATCH 18/24] drm/amd/display: fix a typo which causes an incorrect ODM combine setup
From: Wenjing Liu [why] A recent change for ODM combine refactor contains a typo which causes ODM combine mode programmed incorrectly. Reviewed-by: George Shen Acked-by: Roman Li Signed-off-by: Wenjing Liu --- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index d085c9ff9d38..42c3c440ed89 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -854,7 +854,7 @@ enum dc_status dcn20_enable_stream_timing( opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, >res_ctx, opp_heads); for (i = 0; i < opp_cnt; i++) - opp_inst[opp_cnt] = opp_heads[i]->stream_res.opp->inst; + opp_inst[i] = opp_heads[i]->stream_res.opp->inst; odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false); last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true); -- 2.34.1
[PATCH 03/24] drm/amd/display: Add missing enable and disable symclk_se functions for dcn401
From: Wenjing Liu
The functions are missing. These two functions are required to support
MST.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
.../amd/display/dc/dccg/dcn401/dcn401_dccg.c | 159 ++
.../amd/display/dc/dccg/dcn401/dcn401_dccg.h | 12 ++
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 5 +
.../dc/resource/dcn401/dcn401_resource.h | 6 +-
4 files changed, 181 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
index 72cbff8632dd..a496a250f892 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
@@ -785,6 +785,163 @@ static void dccg401_set_ref_dscclk(struct dccg *dccg,
}
}
+static void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t
stream_enc_inst, uint32_t link_enc_inst)
+{
+ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+ switch (link_enc_inst) {
+ case 0:
+ REG_UPDATE(SYMCLKA_CLOCK_ENABLE,
+ SYMCLKA_CLOCK_ENABLE, 1);
+ if
(dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKA_ROOT_GATE_DISABLE, 1);
+ break;
+ case 1:
+ REG_UPDATE(SYMCLKB_CLOCK_ENABLE,
+ SYMCLKB_CLOCK_ENABLE, 1);
+ if
(dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKB_ROOT_GATE_DISABLE, 1);
+ break;
+ case 2:
+ REG_UPDATE(SYMCLKC_CLOCK_ENABLE,
+ SYMCLKC_CLOCK_ENABLE, 1);
+ if
(dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKC_ROOT_GATE_DISABLE, 1);
+ break;
+ case 3:
+ REG_UPDATE(SYMCLKD_CLOCK_ENABLE,
+ SYMCLKD_CLOCK_ENABLE, 1);
+ if
(dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKD_ROOT_GATE_DISABLE, 1);
+ break;
+ }
+
+ switch (stream_enc_inst) {
+ case 0:
+ REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,
+ SYMCLKA_FE_EN, 1,
+ SYMCLKA_FE_SRC_SEL, link_enc_inst);
+ if
(dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKA_FE_ROOT_GATE_DISABLE, 1);
+ break;
+ case 1:
+ REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,
+ SYMCLKB_FE_EN, 1,
+ SYMCLKB_FE_SRC_SEL, link_enc_inst);
+ if
(dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKB_FE_ROOT_GATE_DISABLE, 1);
+ break;
+ case 2:
+ REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,
+ SYMCLKC_FE_EN, 1,
+ SYMCLKC_FE_SRC_SEL, link_enc_inst);
+ if
(dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKC_FE_ROOT_GATE_DISABLE, 1);
+ break;
+ case 3:
+ REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,
+ SYMCLKD_FE_EN, 1,
+ SYMCLKD_FE_SRC_SEL, link_enc_inst);
+ if
(dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKD_FE_ROOT_GATE_DISABLE, 1);
+ break;
+ }
+}
+
+/*get other front end connected to this backend*/
+static uint8_t dccg401_get_other_enabled_symclk_fe(struct dccg *dccg, uint32_t
stream_enc_inst, uint32_t link_enc_inst)
+{
+ uint8_t num_enabled_symclk_fe = 0;
+ uint32_t be_clk_en = 0, fe_clk_en[4] = {0}, be_clk_sel[4] = {0};
+ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+ switch (link_enc_inst) {
+ case 0:
+ REG_GET_3(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE,
_clk_en,
+ SYMCLKA_FE_EN, _clk_en[0],
+ SYMCLKA_FE_SRC_SEL, _clk_sel[0]);
+ break;
+ case 1:
+ REG_GET_3(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE,
_clk_en,
+ SYMCLKB_FE_EN, _clk_en[1],
+ SYMCLKB_FE_SRC_SEL, _clk_sel[1]);
+ break;
+ case 2:
+ REG_GET_3(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE,
_clk_en,
+ SYMCLKC_FE_EN,
[PATCH 17/24] drm/amd/display: Remove redundant idle optimization check
From: Roman Li
[Why]
Disable idle optimization for each atomic commit is unnecessary,
and can lead to a potential race condition.
[How]
Remove idle optimization check from amdgpu_dm_atomic_commit_tail()
Fixes: 196107eb1e15 ("drm/amd/display: Add IPS checks before dcn register
access")
Cc: sta...@vger.kernel.org
Reviewed-by: Hamza Mahfooz
Acked-by: Roman Li
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 53dc4c75fb75..328db84e3d44 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9395,9 +9395,6 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
trace_amdgpu_dm_atomic_commit_tail_begin(state);
- if (dm->dc->caps.ips_support && dm->dc->idle_optimizations_allowed)
- dc_allow_idle_optimizations(dm->dc, false);
-
drm_atomic_helper_update_legacy_modeset_state(dev, state);
drm_dp_mst_atomic_wait_for_dependencies(state);
--
2.34.1
[PATCH 22/24] drm/amd/display: Not fallback if link BW is smaller than req BW
From: Cruise
[Why]
When the link BW is smaller than the request BW,
the DP LT just kept running and fallback to lower link config.
DP LT just aborted if is_hpd_pending bit is high.
But is_hpd_pending bit indicates a new HPD event received.
It doesn't mean the HPD is low.
[How]
Abort the DP LT if the link BW is smaller than the request BW.
Remove checking is_hpd_pending bit in DP LT.
Reviewed-by: Wenjing Liu
Acked-by: Roman Li
Signed-off-by: Cruise
---
.../display/dc/link/protocols/link_dp_training.c | 5 -
.../dc/link/protocols/link_dp_training_dpia.c| 16
2 files changed, 4 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
index b8e704dbe956..a93dd83cd8c0 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
@@ -1704,10 +1704,13 @@ bool perform_link_training_with_retries(
is_link_bw_min = ((cur_link_settings.link_rate <=
LINK_RATE_LOW) &&
(cur_link_settings.lane_count <=
LANE_COUNT_ONE));
- if (is_link_bw_low)
+ if (is_link_bw_low) {
DC_LOG_WARNING(
"%s: Link(%d) bandwidth too low after
fallback req_bw(%d) > link_bw(%d)\n",
__func__, link->link_index, req_bw,
link_bw);
+
+ return false;
+ }
}
msleep(delay_between_attempts);
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
index edb21d21952a..cd1975c03f38 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
@@ -430,10 +430,6 @@ static enum link_training_result
dpia_training_cr_non_transparent(
retry_count++;
}
- /* Abort link training if clock recovery failed due to HPD unplug. */
- if (link->is_hpd_pending)
- result = LINK_TRAINING_ABORT;
-
DC_LOG_HW_LINK_TRAINING(
"%s\n DPIA(%d) clock recovery\n -hop(%d)\n - result(%d)\n -
retries(%d)\n - status(%d)\n",
__func__,
@@ -537,10 +533,6 @@ static enum link_training_result
dpia_training_cr_transparent(
retry_count++;
}
- /* Abort link training if clock recovery failed due to HPD unplug. */
- if (link->is_hpd_pending)
- result = LINK_TRAINING_ABORT;
-
DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) clock recovery\n -hop(%d)\n -
result(%d)\n - retries(%d)\n",
__func__,
link->link_id.enum_id - ENUM_ID_1,
@@ -731,10 +723,6 @@ static enum link_training_result
dpia_training_eq_non_transparent(
lt_settings->hw_lane_settings,
lt_settings->dpcd_lane_settings);
}
- /* Abort link training if equalization failed due to HPD unplug. */
- if (link->is_hpd_pending)
- result = LINK_TRAINING_ABORT;
-
DC_LOG_HW_LINK_TRAINING(
"%s\n DPIA(%d) equalization\n - hop(%d)\n - result(%d)\n -
retries(%d)\n - status(%d)\n",
__func__,
@@ -822,10 +810,6 @@ static enum link_training_result
dpia_training_eq_transparent(
lt_settings->hw_lane_settings,
lt_settings->dpcd_lane_settings);
}
- /* Abort link training if equalization failed due to HPD unplug. */
- if (link->is_hpd_pending)
- result = LINK_TRAINING_ABORT;
-
DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) equalization\n - hop(%d)\n -
result(%d)\n - retries(%d)\n",
__func__,
link->link_id.enum_id - ENUM_ID_1,
--
2.34.1
[PATCH 21/24] drm/amd/display: Correct display clocks update block sequence
From: Dillon Varone
[WHY]
At the time of block sequence construction, the exact reference DPP/DISP clock
is
not yet known, so the clock should be passed by reference to the DTO programming
function.
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Dillon Varone
---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 577 --
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.h| 8 +-
2 files changed, 272 insertions(+), 313 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index 0b2a3863b1f8..e3a3893a9cab 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -328,12 +328,12 @@ static void dcn401_update_clocks_update_dtb_dto(struct
clk_mgr_internal *clk_mgr
}
}
-void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
- struct dc_state *context, bool safe_to_lower, int dppclk_khz)
+static void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal
*clk_mgr,
+ struct dc_state *context, bool safe_to_lower, int
ref_dppclk_khz)
{
int i;
- clk_mgr->dccg->ref_dppclk = dppclk_khz;
+ clk_mgr->dccg->ref_dppclk = ref_dppclk_khz;
for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
@@ -391,8 +391,6 @@ static void dcn401_update_clocks_update_dentist(
{
uint32_t new_disp_divider = 0;
uint32_t new_dispclk_wdivider = 0;
- uint32_t old_dispclk_wdivider = 0;
- uint32_t i;
uint32_t dentist_dispclk_wdivider_readback = 0;
struct dc *dc = clk_mgr->base.ctx->dc;
@@ -403,86 +401,6 @@ static void dcn401_update_clocks_update_dentist(
* clk_mgr->base.dentist_vco_freq_khz /
clk_mgr->base.clks.dispclk_khz;
new_dispclk_wdivider = dentist_get_did_from_divider(new_disp_divider);
- REG_GET(DENTIST_DISPCLK_CNTL,
- DENTIST_DISPCLK_WDIVIDER, _dispclk_wdivider);
-
- /* When changing divider to or from 127, some extra programming is
required to prevent corruption */
- if (old_dispclk_wdivider == 127 && new_dispclk_wdivider != 127) {
- for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count;
i++) {
- struct pipe_ctx *pipe_ctx =
>res_ctx.pipe_ctx[i];
- uint32_t fifo_level;
- struct dccg *dccg =
clk_mgr->base.ctx->dc->res_pool->dccg;
- struct stream_encoder *stream_enc =
pipe_ctx->stream_res.stream_enc;
- int32_t N;
- int32_t j;
-
- if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))
- continue;
- /* Virtual encoders don't have this function */
- if (!stream_enc->funcs->get_fifo_cal_average_level)
- continue;
- fifo_level =
stream_enc->funcs->get_fifo_cal_average_level(
- stream_enc);
- N = fifo_level / 4;
- dccg->funcs->set_fifo_errdet_ovr_en(
- dccg,
- true);
- for (j = 0; j < N - 4; j++)
- dccg->funcs->otg_drop_pixel(
- dccg,
- pipe_ctx->stream_res.tg->inst);
- dccg->funcs->set_fifo_errdet_ovr_en(
- dccg,
- false);
- }
- } else if (new_dispclk_wdivider == 127 && old_dispclk_wdivider != 127) {
- /* request clock with 126 divider first */
- uint32_t temp_disp_divider = dentist_get_divider_from_did(126);
- uint32_t temp_dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
* clk_mgr->base.dentist_vco_freq_khz) / temp_disp_divider;
-
- if (clk_mgr->smu_present &&
dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DISPCLK))
- dcn401_set_hard_min_by_freq_optimized(clk_mgr,
PPCLK_DISPCLK,
- temp_dispclk_khz);
-
- if (dc->debug.override_dispclk_programming) {
- REG_GET(DENTIST_DISPCLK_CNTL,
- DENTIST_DISPCLK_WDIVIDER,
_dispclk_wdivider_readback);
-
- if (dentist_dispclk_wdivider_readback != 126) {
- REG_UPDATE(DENTIST_DISPCLK_CNTL,
- DENTIST_DISPCLK_WDIVIDER, 126);
- REG_WAIT(DENTIST_DISPCLK_CNTL,
DENTIST_DISPCLK_CHG_DONE, 1,
[PATCH 15/24] drm/amd/display: Add ips status info to debugfs
From: Roman Li
[Why]
For debugging and testing purposes.
[How]
If IPS is supported create ips_status debugfs entry.
Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status
Reviewed-by: Jerry Zuo
Acked-by: Roman Li
Signed-off-by: Roman Li
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 47 +++
1 file changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 7d97fdd9da92..27d5c6077630 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -2670,6 +2670,49 @@ static ssize_t dp_max_bpc_write(struct file *f, const
char __user *buf,
return size;
}
+/*
+ * IPS status. Read only.
+ *
+ * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status
+ */
+static int ips_status_show(struct seq_file *m, void *unused)
+{
+ struct amdgpu_device *adev = m->private;
+ struct dc *dc = adev->dm.dc;
+ struct dc_dmub_srv *dc_dmub_srv;
+
+ seq_printf(m, "IPS config: %d\n", dc->config.disable_ips);
+ seq_printf(m, "Idle optimization: %d\n",
dc->idle_optimizations_allowed);
+
+ if (adev->dm.idle_workqueue) {
+ seq_printf(m, "Idle workqueue - enabled: %d\n",
adev->dm.idle_workqueue->enable);
+ seq_printf(m, "Idle workqueue - running: %d\n",
adev->dm.idle_workqueue->running);
+ }
+
+ dc_dmub_srv = dc->ctx->dmub_srv;
+ if (dc_dmub_srv && dc_dmub_srv->dmub) {
+ uint32_t rcg_count, ips1_count, ips2_count;
+ volatile const struct dmub_shared_state_ips_fw *ips_fw =
+
_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;
+ rcg_count = ips_fw->rcg_entry_count;
+ ips1_count = ips_fw->ips1_entry_count;
+ ips2_count = ips_fw->ips2_entry_count;
+ seq_printf(m, "entry counts: rcg=%u ips1=%u ips2=%u\n",
+ rcg_count,
+ ips1_count,
+ ips2_count);
+ rcg_count = ips_fw->rcg_exit_count;
+ ips1_count = ips_fw->ips1_exit_count;
+ ips2_count = ips_fw->ips2_exit_count;
+ seq_printf(m, "exit counts: rcg=%u ips1=%u ips2=%u",
+ rcg_count,
+ ips1_count,
+ ips2_count);
+ seq_puts(m, "\n");
+ }
+ return 0;
+}
+
/*
* Backlight at this moment. Read only.
* As written to display, taking ABM and backlight lut into account.
@@ -3240,6 +3283,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops,
DEFINE_SHOW_ATTRIBUTE(current_backlight);
DEFINE_SHOW_ATTRIBUTE(target_backlight);
+DEFINE_SHOW_ATTRIBUTE(ips_status);
static const struct {
char *name;
@@ -4129,4 +4173,7 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
_hpd_ops);
+ if (adev->dm.dc->caps.ips_support)
+ debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root,
adev,
+ _status_fops);
}
--
2.34.1
[PATCH 13/24] drm/amd/display: Add 3DLUT DMA load trigger
From: Ilya Bakoulin
[Why/How]
Need to be able to trigger a DMA load to update 3DLUT contents in MPC.
Adding a HWSS function to serve as the trigger.
Reviewed-by: Krunoslav Kovac
Acked-by: Roman Li
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 8
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 17 +
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 2 ++
.../amd/display/dc/hwss/dcn401/dcn401_init.c| 1 +
.../gpu/drm/amd/display/dc/hwss/hw_sequencer.h | 1 +
5 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1008fbc57dbd..3a2101b052ea 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -4074,6 +4074,14 @@ static void commit_planes_for_stream(struct dc *dc,
if (!should_update_pipe_for_plane(context,
pipe_ctx, plane_state))
continue;
+ if (srf_updates[i].cm2_params &&
+
srf_updates[i].cm2_params->cm2_luts.lut3d_data.lut3d_src ==
+
DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM &&
+
srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting ==
+
DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT &&
+ dc->hwss.trigger_3dlut_dma_load)
+ dc->hwss.trigger_3dlut_dma_load(dc,
pipe_ctx);
+
/*program triple buffer after lock based on
flip type*/
if (dc->hwss.program_triplebuffer != NULL &&
dc->debug.enable_tri_buf) {
/*only enable triplebuffer for
fast_update*/
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index c3bed33eb5d6..a619da7716ed 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -498,9 +498,9 @@ void dcn401_populate_mcm_luts(struct dc *dc,
if (m_lut_params.pwl) {
if (mpc->funcs->populate_lut)
mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT,
m_lut_params, lut_bank_a, mpcc_id);
- if (mpc->funcs->program_lut_mode)
- mpc->funcs->program_lut_mode(mpc,
MCM_LUT_1DLUT, lut1d_xable, lut_bank_a, mpcc_id);
}
+ if (mpc->funcs->program_lut_mode)
+ mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT,
lut1d_xable, lut_bank_a, mpcc_id);
}
/* Shaper */
@@ -519,9 +519,9 @@ void dcn401_populate_mcm_luts(struct dc *dc,
if (m_lut_params.pwl) {
if (mpc->funcs->populate_lut)
mpc->funcs->populate_lut(mpc, MCM_LUT_SHAPER,
m_lut_params, lut_bank_a, mpcc_id);
- if (mpc->funcs->program_lut_mode)
- mpc->funcs->program_lut_mode(mpc,
MCM_LUT_SHAPER, shaper_xable, lut_bank_a, mpcc_id);
}
+ if (mpc->funcs->program_lut_mode)
+ mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER,
shaper_xable, lut_bank_a, mpcc_id);
}
/* 3DLUT */
@@ -635,6 +635,15 @@ void dcn401_populate_mcm_luts(struct dc *dc,
}
}
+void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx)
+{
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+
+ if (hubp->funcs->hubp_enable_3dlut_fl) {
+ hubp->funcs->hubp_enable_3dlut_fl(hubp, true);
+ }
+}
+
bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state)
{
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
index dd5bae93dc05..f91159a6e6d4 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
@@ -40,6 +40,8 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
bool dcn401_set_output_transfer_func(struct dc *dc,
struct pipe_ctx *pipe_ctx,
const struct dc_stream_state *stream);
+void dcn401_trigger_3dlut_dma_load(struct dc *dc,
+ struct pipe_ctx *pipe_ctx);
void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,
unsigned int *tmds_div);
enum dc_status dcn401_enable_stream_timing(
diff --git
[PATCH 20/24] drm/amd/display: Disable DCN401 idle optimizations
From: Dillon Varone
[WHY]
Disable to improve stability for now.
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index fc43e7b5ec90..247bac177d1b 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -731,6 +731,7 @@ static const struct dc_debug_options debug_defaults_drv = {
}
},
.force_cositing = CHROMA_COSITING_TOPLEFT + 1,
+ .disable_idle_power_optimizations = true,
};
static struct dce_aux *dcn401_aux_engine_create(
--
2.34.1
[PATCH 16/24] drm/amd/display: Fix pipe addition logic in calc_blocks_to_ungate DCN35
From: Nicholas Susanto
[Why]
Missing check for when there is new pipe configuration but both cur_pipe
and new_pipe are both populated causing update_state of DSC for that
instance not being updated correctly.
This causes some display mode changes to cause underflow since DSCCLK
is still gated when the display requires DSC.
[How]
Added another condition in the new pipe addition branch that checks if
there is a new pipe configuration and if it is not the same as cur_pipe.
cur_pipe does not necessarily have to be NULL to go in this branch.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Nicholas Susanto
---
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 6d40e93b5497..2b3ba5971c69 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -1097,7 +1097,8 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct
dc_state *context,
continue;
if ((!cur_pipe->plane_state && new_pipe->plane_state) ||
- (!cur_pipe->stream && new_pipe->stream)) {
+ (!cur_pipe->stream && new_pipe->stream) ||
+ (cur_pipe->stream != new_pipe->stream &&
new_pipe->stream)) {
// New pipe addition
for (j = 0; j < PG_HW_PIPE_RESOURCES_NUM_ELEMENT; j++) {
if (j == PG_HUBP && new_pipe->plane_res.hubp)
--
2.34.1
[PATCH 09/24] drm/amd/display: Modify HPO pixel clock programming to support DPM
From: Dillon Varone
Need to select DTBCLK and DPREFCLK as DTBCLK_p source according to
hardware guidance.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index f39700832639..63deb5b60548 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1082,11 +1082,11 @@ static bool dcn401_program_pix_clk(
// all but TMDS gets Driver to program DP_DTO without calling VBIOS
Command table
if (!dc_is_tmds_signal(pix_clk_params->signal_type)) {
- long long ref_dtbclk_khz =
clock_source->ctx->dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(clock_source->ctx->dc->clk_mgr);
- long long dprefclk_khz =
clock_source->ctx->dc->clk_mgr->dprefclk_khz;
long long dtbclk_p_src_clk_khz;
- /* if signal is DP132B128B dtbclk_p_src is DTBCLK else DPREFCLK
*/
- dtbclk_p_src_clk_khz = encoding == DP_128b_132b_ENCODING ?
ref_dtbclk_khz : dprefclk_khz;
+
+ dtbclk_p_src_clk_khz =
clock_source->ctx->dc->clk_mgr->dprefclk_khz;
+ dto_params.clk_src = DPREFCLK;
+
if (e) {
dto_params.pixclk_hz = e->target_pixel_rate_khz *
e->mult_factor;
dto_params.refclk_hz = dtbclk_p_src_clk_khz *
e->div_factor;
--
2.34.1
[PATCH 11/24] drm/amd/display: Add NULL check within get_target_mpc_factor
From: Hersen Wu
[Why] Coverity reports NULL_RETURN warning.
[How] Add pointer NULL check.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Hersen Wu
---
.../gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
index 190fa2962271..02fb2cb1c43c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
@@ -819,7 +819,16 @@ static unsigned int get_target_mpc_factor(struct
dml2_context *ctx,
/* get stream id of main stream */
main_stream =
ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(state, stream);
+ if (!main_stream) {
+ ASSERT(false);
+ return 1;
+ }
+
main_stream_status =
ctx->config.callbacks.get_stream_status(state, main_stream);
+ if (!main_stream_status) {
+ ASSERT(false);
+ return 1;
+ }
/* get plane id for associated main plane */
get_plane_id(ctx, state,
main_stream_status->plane_states[plane_idx],
--
2.34.1
[PATCH 12/24] drm/amd/display: Deallocate DML 2.1 Memory Allocation
From: Chris Park
[Why]
DML 2.1 allocates two types of memory in its ctx structure but does not
destroy them, causing memory leak whenever DML 2.1 instance is created
and destroyed.
[How]
Deallocate two instances of allocated memory whenever DML 2.1 is
destroyed.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c | 6 ++
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h | 1 +
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c| 2 ++
3 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
index cb8b2d77a1ac..4e0b7d2d63b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
@@ -107,6 +107,12 @@ bool dml21_create(const struct dc *in_dc, struct
dml2_context **dml_ctx, const s
return true;
}
+void dml21_destroy(struct dml2_context *dml2)
+{
+ kfree(dml2->v21.dml_init.dml2_instance);
+ kfree(dml2->v21.mode_programming.programming);
+}
+
static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct
dc_state *context, struct resource_context *out_new_hw_state,
struct dml2_context *in_ctx, unsigned int pipe_cnt)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
index 6708f7117fbd..b2075b8c363b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
@@ -27,6 +27,7 @@ struct dml2_context;
* Return: True if dml2 is successfully created, false otherwise.
*/
bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const
struct dml2_configuration_options *config);
+void dml21_destroy(struct dml2_context *dml2);
void dml21_copy(struct dml2_context *dst_dml_ctx,
struct dml2_context *src_dml_ctx);
bool dml21_create_copy(struct dml2_context **dst_dml_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index 4be304ebf0b4..22f6a59d8ed2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -782,6 +782,8 @@ void dml2_destroy(struct dml2_context *dml2)
if (!dml2)
return;
+ if (dml2->architecture == dml2_architecture_21)
+ dml21_destroy(dml2);
kfree(dml2);
}
--
2.34.1
[PATCH 10/24] drm/amd/display: Add missing DML2 var helpers
From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c index c054c22cf305..ff2adc9eab0d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c @@ -10226,9 +10226,11 @@ dml_get_var_func(stutter_efficiency_z8_bestcase, dml_float_t, mode_lib->mp.Z8Stu dml_get_var_func(stutter_num_bursts_z8_bestcase, dml_float_t, mode_lib->mp.Z8NumberOfStutterBurstsPerFrameBestCase); dml_get_var_func(stutter_period_bestcase, dml_float_t, mode_lib->mp.StutterPeriodBestCase); dml_get_var_func(urgent_extra_latency, dml_float_t, mode_lib->mp.UrgentExtraLatency); +dml_get_var_func(fclk_change_latency, dml_float_t, mode_lib->mp.MaxActiveFCLKChangeLatencySupported); dml_get_var_func(dispclk_calculated, dml_float_t, mode_lib->mp.Dispclk_calculated); dml_get_var_func(total_data_read_bw, dml_float_t, mode_lib->mp.TotalDataReadBandwidth); dml_get_var_func(return_bw, dml_float_t, mode_lib->ms.ReturnBW); +dml_get_var_func(return_dram_bw, dml_float_t, mode_lib->ms.ReturnDRAMBW); dml_get_var_func(tcalc, dml_float_t, mode_lib->mp.TCalc); dml_get_var_func(comp_buffer_size_kbytes, dml_uint_t, mode_lib->mp.CompressedBufferSizeInkByte); dml_get_var_func(pixel_chunk_size_in_kbyte, dml_uint_t, mode_lib->ms.ip.pixel_chunk_size_kbytes); diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h index 3116b88e99dc..a38ed89c47a9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h @@ -105,10 +105,12 @@ dml_get_var_decl(stutter_num_bursts_z8_bestcase, dml_float_t); dml_get_var_decl(stutter_period_bestcase, dml_float_t); dml_get_var_decl(urgent_latency, dml_float_t); dml_get_var_decl(urgent_extra_latency, dml_float_t); +dml_get_var_decl(fclk_change_latency, dml_float_t); dml_get_var_decl(nonurgent_latency, dml_float_t); dml_get_var_decl(dispclk_calculated, dml_float_t); dml_get_var_decl(total_data_read_bw, dml_float_t); dml_get_var_decl(return_bw, dml_float_t); +dml_get_var_decl(return_dram_bw, dml_float_t); dml_get_var_decl(tcalc, dml_float_t); dml_get_var_decl(fraction_of_urgent_bandwidth, dml_float_t); dml_get_var_decl(fraction_of_urgent_bandwidth_imm_flip, dml_float_t); -- 2.34.1
[PATCH 05/24] drm/amd/display: Use the correct TMDS function to avoid DVI issues
From: Chris Park
[Why]
DVI is TMDS signal like HDMI but without audio. Current signal check
does not correctly reflect DVI clock programming.
[How]
Define a new signal check for TMDS that includes DVI to HDMI TMDS
programming.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 6b33117ab5fc..f39700832639 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1081,7 +1081,7 @@ static bool dcn401_program_pix_clk(
dto_params.signal = pix_clk_params->signal_type;
// all but TMDS gets Driver to program DP_DTO without calling VBIOS
Command table
- if (!dc_is_hdmi_tmds_signal(pix_clk_params->signal_type)) {
+ if (!dc_is_tmds_signal(pix_clk_params->signal_type)) {
long long ref_dtbclk_khz =
clock_source->ctx->dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(clock_source->ctx->dc->clk_mgr);
long long dprefclk_khz =
clock_source->ctx->dc->clk_mgr->dprefclk_khz;
long long dtbclk_p_src_clk_khz;
--
2.34.1
[PATCH 07/24] drm/amd/display: enable EASF support for DCN40
From: Samson Tam
[Why]
Enable adaptive scaler support for DCN401
[How]
- Enable build flag for SPL
- Set prefer_easf flag to true
- Apply light linear scaling policy based on transfer function and pixel
format. Choose between linear or non-linear scaling
- Set matrix_mode based on pixel format
- Disable ring estimator
- Add missing EASF register defines, masks, and writes
- Disable EASF if scale ratio or number of taps is unsupported and when
bypassing the scaler
- Add debug flags and registry keys for debugging SPL and EASF
- Add support for Visual Confirm with EASF
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Samson Tam
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 11 +-
drivers/gpu/drm/amd/display/dc/dc.h | 3 +
.../gpu/drm/amd/display/dc/dc_spl_translate.c | 15 +-
.../amd/display/dc/dpp/dcn401/dcn401_dpp.h| 6 +-
.../display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 207 +-
.../dc/resource/dcn401/dcn401_resource.c | 1 +
.../dc/resource/dcn401/dcn401_resource.h | 48 +++-
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 95 ++--
.../gpu/drm/amd/display/dc/spl/dc_spl_types.h | 30 ++-
9 files changed, 382 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 70c39eef99e5..ce1991e06049 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1500,8 +1500,8 @@ bool resource_build_scaling_params(struct pipe_ctx
*pipe_ctx)
pipe_ctx->plane_res.scl_data.format =
convert_pixel_format_to_dalsurface(
pipe_ctx->plane_state->format);
- if (pipe_ctx->stream->ctx->dc->config.use_spl) {
#if defined(CONFIG_DRM_AMD_DC_FP)
+ if ((pipe_ctx->stream->ctx->dc->config.use_spl) &&
(!pipe_ctx->stream->ctx->dc->debug.disable_spl)) {
struct spl_in *spl_in = _ctx->plane_res.spl_in;
struct spl_out *spl_out = _ctx->plane_res.spl_out;
@@ -1516,15 +1516,18 @@ bool resource_build_scaling_params(struct pipe_ctx
*pipe_ctx)
// Convert pipe_ctx to respective input params for SPL
translate_SPL_in_params_from_pipe_ctx(pipe_ctx, spl_in);
+ /* Pass visual confirm debug information */
+ calculate_adjust_recout_for_visual_confirm(pipe_ctx,
+ _in->debug.visual_confirm_base_offset,
+ _in->debug.visual_confirm_dpp_offset);
// Set SPL output parameters to dscl_prog_data to be used for
hw registers
spl_out->dscl_prog_data = resource_get_dscl_prog_data(pipe_ctx);
// Calculate scaler parameters from SPL
res = spl_calculate_scaler_params(spl_in, spl_out);
// Convert respective out params from SPL to scaler data
translate_SPL_out_params_to_pipe_ctx(pipe_ctx, spl_out);
-#endif
} else {
-
+#endif
/* depends on h_active */
calculate_recout(pipe_ctx);
/* depends on pixel format */
@@ -1604,7 +1607,9 @@ bool resource_build_scaling_params(struct pipe_ctx
*pipe_ctx)
pipe_ctx->plane_res.scl_data.viewport.height =
MIN_VIEWPORT_SIZE;
if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;
+#ifdef CONFIG_DRM_AMD_DC_FP
}
+#endif
DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d
Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n"
"src_rect: height:%d width:%d x:%d y:%d dst_rect:
height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n",
__func__,
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index fd948e4cec0d..5ae74558632b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1038,6 +1038,9 @@ struct dc_debug_options {
union dmub_fams2_global_feature_config fams2_config;
bool enable_legacy_clock_update;
unsigned int force_cositing;
+ unsigned int disable_spl;
+ unsigned int force_easf;
+ unsigned int force_lls;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
index daf97688e901..6e37b166802b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
@@ -129,6 +129,11 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx
*pipe_ctx, struct spl
populate_spltaps_from_taps(_in->scaling_quality,
_state->scaling_quality);
// Translate edge adaptive scaler preference
spl_in->prefer_easf = pipe_ctx->stream->ctx->dc->config.prefer_easf;
+ spl_in->disable_easf = false;
+ if
[PATCH 08/24] drm/amd/display: Refactor HUBBUB into component folder for DCN401
From: "Revalla, Harikrishna"
[why]
Cleaning up the code refactor requires hubbub to be in its own
component.
[how]
Move all DCN401 files under newly created hubbub folder and fixing the
makefiles.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Harikrishna Revalla
---
drivers/gpu/drm/amd/display/dc/dcn401/Makefile | 1 -
drivers/gpu/drm/amd/display/dc/hubbub/Makefile | 6 +-
.../drm/amd/display/dc/{ => hubbub}/dcn401/dcn401_hubbub.c | 0
.../drm/amd/display/dc/{ => hubbub}/dcn401/dcn401_hubbub.h | 0
4 files changed, 5 insertions(+), 2 deletions(-)
rename drivers/gpu/drm/amd/display/dc/{ => hubbub}/dcn401/dcn401_hubbub.c
(100%)
rename drivers/gpu/drm/amd/display/dc/{ => hubbub}/dcn401/dcn401_hubbub.h
(100%)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/Makefile
b/drivers/gpu/drm/amd/display/dc/dcn401/Makefile
index 73544559f41f..f3fdfa1fba37 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn401/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn401/Makefile
@@ -6,7 +6,6 @@ DCN401 += dcn401_dio_link_encoder.o
DCN401 += dcn401_dio_stream_encoder.o
DCN401 += dcn401_hubp.o
DCN401 += dcn401_mpc.o
-DCN401 += dcn401_hubbub.o
AMD_DAL_DCN401 = $(addprefix $(AMDDALPATH)/dc/dcn401/,$(DCN401))
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/Makefile
b/drivers/gpu/drm/amd/display/dc/hubbub/Makefile
index ab2fddc4a858..66ca5a6a0415 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/Makefile
@@ -94,7 +94,11 @@ AMD_DAL_HUBBUB_DCN35 = $(addprefix
$(AMDDALPATH)/dc/hubbub/dcn35/,$(HUBBUB_DCN35
AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN35)
###
+HUBBUB_DCN401 = dcn401_hubbub.o
+AMD_DAL_HUBBUB_DCN401 = $(addprefix
$(AMDDALPATH)/dc/hubbub/dcn401/,$(HUBBUB_DCN401))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN401)
###
-endif
\ No newline at end of file
+endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_hubbub.c
b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dcn401/dcn401_hubbub.c
rename to drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_hubbub.h
b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dcn401/dcn401_hubbub.h
rename to drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
--
2.34.1
[PATCH 06/24] drm/amd/display: Adjust incorrect indentations and spaces
From: Alex Hung
This fixes indentations and adjust spaces for better readability and
code styles.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile | 1 -
.../amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 1 -
drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ---
.../gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 3 +--
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 12 ++--
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 1 -
.../gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 1 -
.../drm/amd/display/dc/dcn20/dcn20_link_encoder.h| 1 -
10 files changed, 13 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index dfaa200ecf1a..ab1132bc896a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -83,7 +83,6 @@ CLK_MGR_DCN10 = rv1_clk_mgr.o rv1_clk_mgr_vbios_smu.o
rv2_clk_mgr.o
AMD_DAL_CLK_MGR_DCN10 = $(addprefix
$(AMDDALPATH)/dc/clk_mgr/dcn10/,$(CLK_MGR_DCN10))
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN10)
-
###
# DCN20
###
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index d2abc00a60c5..0b2a3863b1f8 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -1539,7 +1539,6 @@ struct clk_mgr_internal *dcn401_clk_mgr_construct(
}
return _mgr401->base;
-
}
void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 518164dd9c3c..1008fbc57dbd 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1019,7 +1019,7 @@ static bool dc_construct(struct dc *dc,
goto fail;
}
-dc_ctx = dc->ctx;
+ dc_ctx = dc->ctx;
/* Resource should construct all asic specific resources.
* This should be the only place where we need to parse the asic id
@@ -3361,10 +3361,10 @@ static void commit_planes_do_stream_update(struct dc
*dc,
if (stream_update->mst_bw_update->is_increase)
dc->link_srv->increase_mst_payload(pipe_ctx,
stream_update->mst_bw_update->mst_stream_bw);
- else
+ else
dc->link_srv->reduce_mst_payload(pipe_ctx,
stream_update->mst_bw_update->mst_stream_bw);
- }
+ }
if (stream_update->pending_test_pattern) {
/*
@@ -3970,6 +3970,7 @@ static void commit_planes_for_stream(struct dc *dc,
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *plane_state = srf_updates[i].surface;
+
/*set logical flag for lock/unlock use*/
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx =
>res_ctx.pipe_ctx[j];
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
index e3be0bab4007..cd261051dc2c 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
@@ -132,7 +132,7 @@
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
- DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh), \
+ DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh),\
DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\
DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\
DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 739298d2dff3..b8996d285f00 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -770,7 +770,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
aux_defer_retries,
[PATCH 02/24] drm/amd/display: Remove duplicate configuration
From: Rodrigo Siqueira The function that commits planes calls the same set of functions twice, and in the case of the FAMs utilization, it is not desired to call the dmub, hwss_build and hwss_execute. This commit just removes the unnecessary calls to those functions. Acked-by: Roman Li Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/core/dc.c | 18 -- 1 file changed, 18 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 6f534c2e76b7..ae04937e60b0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3741,24 +3741,6 @@ static void commit_planes_for_stream_fast(struct dc *dc, context->block_sequence_steps); } - build_dmub_cmd_list(dc, - srf_updates, - surface_count, - stream, - context, - context->dc_dmub_cmd, - &(context->dmub_cmd_count)); - hwss_build_fast_sequence(dc, - context->dc_dmub_cmd, - context->dmub_cmd_count, - context->block_sequence, - &(context->block_sequence_steps), - top_pipe_to_program, - stream_status, - context); - hwss_execute_sequence(dc, - context->block_sequence, - context->block_sequence_steps); /* Clear update flags so next flip doesn't have redundant programming * (if there's no stream update, the update flags are not cleared). * Surface updates are cleared unconditionally at the beginning of each flip, -- 2.34.1
[PATCH 04/24] drm/amd/display: Fix incorrect DCN401 comparison
From: Alex Hung
The comparisons intend to be DCN401 inclusive, and fix it by adding
equal signs.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ae04937e60b0..518164dd9c3c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -5104,7 +5104,7 @@ bool dc_update_planes_and_stream(struct dc *dc,
* specially handle compatibility problems with transitions among those
* features as they are now transparent to the new sequence.
*/
- if (dc->ctx->dce_version > DCN_VERSION_4_01)
+ if (dc->ctx->dce_version >= DCN_VERSION_4_01)
return update_planes_and_stream_v3(dc, srf_updates,
surface_count, stream, stream_update);
return update_planes_and_stream_v2(dc, srf_updates,
@@ -5124,7 +5124,7 @@ void dc_commit_updates_for_stream(struct dc *dc,
* we get more confident about this change we'll need to enable
* the new sequence for all ASICs.
*/
- if (dc->ctx->dce_version > DCN_VERSION_4_01) {
+ if (dc->ctx->dce_version >= DCN_VERSION_4_01) {
update_planes_and_stream_v3(dc, srf_updates, surface_count,
stream, stream_update);
return;
--
2.34.1
[PATCH 01/24] drm/amd/display: Move DSC functions from dc.c to dc_dsc.c
From: George Shen
Move dsc functions from dc.c to dc_dsc.c.
Co-Developed-by: George Shen
Signed-off-by: Wenjing Liu
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 99 -
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 96
2 files changed, 96 insertions(+), 99 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0208b28517ac..6f534c2e76b7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -5979,102 +5979,3 @@ struct dc_power_profile
dc_get_power_profile_for_dc_state(const struct dc_state
return profile;
}
-
-/* Need to account for padding due to pixel-to-symbol packing
- * for uncompressed 128b/132b streams.
- */
-static uint32_t apply_128b_132b_stream_overhead(
- const struct dc_crtc_timing *timing, const uint32_t kbps)
-{
- uint32_t total_kbps = kbps;
-#if defined(CONFIG_DRM_AMD_DC_FP)
- if (dc_get_disable_128b_132b_stream_overhead())
- return kbps;
-#endif
-
- if (!timing->flags.DSC) {
- struct fixed31_32 bpp;
- struct fixed31_32 overhead_factor;
-
- bpp = dc_fixpt_from_int(kbps);
- bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10);
-
- /* Symbols_per_HActive = HActive * bpp / (4 lanes * 32-bit
symbol size)
-* Overhead_factor = ceil(Symbols_per_HActive) /
Symbols_per_HActive
-*/
- overhead_factor = dc_fixpt_from_int(timing->h_addressable);
- overhead_factor = dc_fixpt_mul(overhead_factor, bpp);
- overhead_factor = dc_fixpt_div_int(overhead_factor, 128);
- overhead_factor = dc_fixpt_div(
- dc_fixpt_from_int(dc_fixpt_ceil(overhead_factor)),
- overhead_factor);
-
- total_kbps = dc_fixpt_ceil(
- dc_fixpt_mul_int(overhead_factor, total_kbps));
- }
-
- return total_kbps;
-}
-
-uint32_t dc_bandwidth_in_kbps_from_timing(
- const struct dc_crtc_timing *timing,
- const enum dc_link_encoding_format link_encoding)
-{
- uint32_t bits_per_channel = 0;
- uint32_t kbps;
-
-#if defined(CONFIG_DRM_AMD_DC_FP)
- if (timing->flags.DSC)
- return dc_dsc_stream_bandwidth_in_kbps(timing,
- timing->dsc_cfg.bits_per_pixel,
- timing->dsc_cfg.num_slices_h,
- timing->dsc_cfg.is_dp);
-#endif
-
- switch (timing->display_color_depth) {
- case COLOR_DEPTH_666:
- bits_per_channel = 6;
- break;
- case COLOR_DEPTH_888:
- bits_per_channel = 8;
- break;
- case COLOR_DEPTH_101010:
- bits_per_channel = 10;
- break;
- case COLOR_DEPTH_121212:
- bits_per_channel = 12;
- break;
- case COLOR_DEPTH_141414:
- bits_per_channel = 14;
- break;
- case COLOR_DEPTH_161616:
- bits_per_channel = 16;
- break;
- default:
- ASSERT(bits_per_channel != 0);
- bits_per_channel = 8;
- break;
- }
-
- kbps = timing->pix_clk_100hz / 10;
- kbps *= bits_per_channel;
-
- if (timing->flags.Y_ONLY != 1) {
- /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
- kbps *= 3;
- if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
- kbps /= 2;
- else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
- kbps = kbps * 2 / 3;
- }
-
- if (link_encoding == DC_LINK_ENCODING_DP_128b_132b)
- kbps = apply_128b_132b_stream_overhead(timing, kbps);
-
- if (link_encoding == DC_LINK_ENCODING_HDMI_FRL &&
- timing->vic == 0 && timing->hdmi_vic == 0 &&
- timing->frl_uncompressed_video_bandwidth_in_kbps != 0)
- kbps = timing->frl_uncompressed_video_bandwidth_in_kbps;
-
- return kbps;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index dd7091628b3c..b9d10e95ef7a 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -49,6 +49,102 @@ static bool disable_128b_132b_stream_overhead;
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
#endif
+/* Need to account for padding due to pixel-to-symbol packing
+ * for uncompressed 128b/132b streams.
+ */
+static uint32_t apply_128b_132b_stream_overhead(
+ const struct dc_crtc_timing *timing, const uint32_t kbps)
+{
+ uint32_t total_kbps = kbps;
+
+ if (disable_128b_132b_stream_overhead)
+ return kbps;
+
+
[PATCH 00/24] DC Patches May 16, 2024
From: Roman Li
This DC patchset brings improvements in multiple areas. In summary, we have:
- Fix powerpc compilation
- Fix TBT+TypeC Daisy-chain lightup
- Fix underflow on dcn35
- Fix DVI for dcn401
- Add 3DLUT DMA load trigger
- Modify clock programming to support DPM
Cc: Daniel Wheeler hubbub}/dcn401/dcn401_hubbub.c| 0
.../dc/{ => hubbub}/dcn401/dcn401_hubbub.h| 0
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +-
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 3 +-
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 34 +-
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 2 +
.../amd/display/dc/hwss/dcn401/dcn401_init.c | 1 +
.../drm/amd/display/dc/hwss/hw_sequencer.h| 1 +
.../dc/link/protocols/link_dp_training.c | 5 +-
.../dc/link/protocols/link_dp_training_dpia.c | 16 -
.../dc/resource/dcn401/dcn401_resource.c | 2 +
.../dc/resource/dcn401/dcn401_resource.h | 54 +-
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 95 ++-
.../gpu/drm/amd/display/dc/spl/dc_spl_types.h | 30 +-
45 files changed, 1072 insertions(+), 522 deletions(-)
rename drivers/gpu/drm/amd/display/dc/{ => hubbub}/dcn401/dcn401_hubbub.c
(100%)
rename drivers/gpu/drm/amd/display/dc/{ => hubbub}/dcn401/dcn401_hubbub.h
(100%)
--
2.34.1
[PATCH 41/43] drm/amd/display: Includes adjustments
From: Rodrigo Siqueira This commit clean up some of the includes used by DCN. Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c | 4 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c | 2 -- .../gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c | 2 -- .../gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h | 1 - drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h| 2 +- 5 files changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c index f9d6a181164a..b851fc65f5b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c @@ -34,11 +34,7 @@ #include "reg_helper.h" #include "fixed31_32.h" -#ifdef _WIN32 -#include "atombios.h" -#else #include "atom.h" -#endif #define TO_DMUB_ABM(abm)\ container_of(abm, struct dce_abm, base) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c index 1fb8fd7afc95..b8e31b5ea114 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c @@ -30,8 +30,6 @@ #include "dcn30_dio_link_encoder.h" #include "stream_encoder.h" #include "dc_bios_types.h" -/* #include "dcn3ag/dcn3ag_phy_fw.h" */ - #include "gpio_service_interface.h" #define CTX \ diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c index 005dbe099a7a..8ed7125d230d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c @@ -30,8 +30,6 @@ #include "hw_shared.h" #include "dc.h" #include "core_types.h" -#include - #define DC_LOGGER \ enc1->base.ctx->logger diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h index 499052329ebb..1212fcee38f2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h @@ -28,7 +28,6 @@ #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "stream_encoder.h" -#include "dcn10/dcn10_link_encoder.h" #include "dcn20/dcn20_stream_encoder.h" /* Register bit field name change */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h index 9e4ddc985240..55529c5f471c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h @@ -31,7 +31,7 @@ #define __DCN_CALCS_H__ #include "bw_fixed.h" -#include "../dml/display_mode_lib.h" +#include "dml/display_mode_lib.h" struct dc; -- 2.34.1
[PATCH 42/43] drm/amd/display: Add color logs for dcn20
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
index 884e3e323338..ef6488165b8f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
@@ -67,6 +67,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
.setup_stereo = dcn10_setup_stereo,
.set_avmute = dce110_set_avmute,
.log_hw_state = dcn10_log_hw_state,
+ .log_color_state = dcn20_log_color_state,
.get_hw_state = dcn10_get_hw_state,
.clear_status_bits = dcn10_clear_status_bits,
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
--
2.34.1
[PATCH 39/43] drm/amd/display: Add WBSCL ram coefficient for writeback
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
index f8667be57046..80779e85e2c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
@@ -299,6 +299,17 @@ void dwb2_set_scaler(struct dwbc *dwbc, struct
dc_dwb_params *params)
}
}
+
+ if (dwbc20->dwbc_mask->WBSCL_COEF_RAM_SEL) {
+ /* Swap double buffered coefficient set */
+ uint32_t wbscl_mode = REG_READ(WBSCL_MODE);
+ bool coef_ram_current = get_reg_field_value_ex(
+ wbscl_mode,
dwbc20->dwbc_mask->WBSCL_COEF_RAM_SEL_CURRENT,
+ dwbc20->dwbc_shift->WBSCL_COEF_RAM_SEL_CURRENT);
+
+ REG_UPDATE(WBSCL_MODE, WBSCL_COEF_RAM_SEL, !coef_ram_current);
+ }
+
}
static const struct dwbc_funcs dcn20_dwbc_funcs = {
--
2.34.1
[PATCH 33/43] drm/amd/display: Drop legacy code
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h| 10 --
.../amd/display/dc/gpio/dcn21/hw_translate_dcn21.c | 13 -
2 files changed, 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 1cb7765f593a..b7ad64e7b62a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -917,16 +917,6 @@ struct dpcd_usb4_dp_tunneling_info {
uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];
};
-#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT
-#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT0x0A3
-#endif
-#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0
-#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230
-#endif
-#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256
-#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250
-#endif
-
union dp_main_line_channel_coding_cap {
struct {
uint8_t DP_8b_10b_SUPPORTED :1;
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
index d734e3a134d1..2840ed5c57d8 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
@@ -95,10 +95,6 @@ static bool offset_to_id(
return true;
default:
ASSERT_CRITICAL(false);
-#ifdef PALLADIUM_SUPPORTED
- *en = GPIO_DDC_LINE_DDC1;
- return true;
-#endif
return false;
}
break;
@@ -184,11 +180,6 @@ static bool offset_to_id(
/* UNEXPECTED */
default:
/* case REG(DC_GPIO_SYNCA_A): not exista */
-#ifdef PALLADIUM_SUPPORTED
- *id = GPIO_ID_HPD;
- *en = GPIO_DDC_LINE_DDC1;
- return true;
-#endif
ASSERT_CRITICAL(false);
return false;
}
@@ -308,10 +299,6 @@ static bool id_to_offset(
break;
default:
ASSERT_CRITICAL(false);
-#ifdef PALLADIUM_SUPPORTED
- info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
- result = true;
-#endif
result = false;
}
break;
--
2.34.1
[PATCH 31/43] drm/amd/display: Add some missing debug registers
From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h | 4 .../include/asic_reg/dcn/dcn_3_0_0_offset.h | 24 +++ .../include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 9 +++ .../include/asic_reg/dcn/dcn_3_0_2_offset.h | 20 .../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h | 8 +++ .../include/asic_reg/dcn/dcn_3_0_3_offset.h | 8 +++ .../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h | 7 ++ .../include/asic_reg/dcn/dcn_3_2_0_sh_mask.h | 5 8 files changed, 85 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h index 2ac8045a87a1..269f437c1633 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h @@ -132,6 +132,8 @@ SRI(CM_POST_CSC_B_C33_C34, CM, id), \ SRI(CM_MEM_PWR_CTRL, CM, id), \ SRI(CM_CONTROL, CM, id), \ + SRI(CM_TEST_DEBUG_INDEX, CM, id), \ + SRI(CM_TEST_DEBUG_DATA, CM, id), \ SRI(FORMAT_CONTROL, CNVC_CFG, id), \ SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ SRI(CURSOR0_CONTROL, CNVC_CUR, id), \ @@ -294,6 +296,7 @@ TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C12, mask_sh), \ TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C33, mask_sh), \ TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C34, mask_sh), \ + TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \ TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \ TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ @@ -426,6 +429,7 @@ type CM_GAMCOR_LUT_DATA; \ type CM_GAMCOR_LUT_WRITE_COLOR_MASK; \ type CM_GAMCOR_LUT_READ_COLOR_SEL; \ + type CM_GAMCOR_LUT_READ_DBG; \ type CM_GAMCOR_LUT_HOST_SEL; \ type CM_GAMCOR_LUT_CONFIG_MODE; \ type CM_GAMCOR_LUT_STATUS; \ diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h index f2f8f9b39c6b..b5bfaa64a9db 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h @@ -4513,6 +4513,10 @@ #define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 #define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18 #define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 +#define mmCM0_CM_TEST_DEBUG_INDEX 0x0e19 +#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmCM0_CM_TEST_DEBUG_DATA 0x0e1a +#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec @@ -5201,6 +5205,10 @@ #define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 #define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83 #define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 +#define mmCM1_CM_TEST_DEBUG_INDEX 0x0f84 +#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmCM1_CM_TEST_DEBUG_DATA 0x0f85 +#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec @@ -5888,6 +5896,10 @@ #define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 #define mmCM2_CM_3DLUT_OUT_OFFSET_B 0x10ee #define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 +#define mmCM2_CM_TEST_DEBUG_INDEX 0x10ef +#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmCM2_CM_TEST_DEBUG_DATA 0x10f0 +#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec @@ -6576,6 +6588,10 @@
[PATCH 37/43] drm/amd/display: Initialize debug variable data
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index d9ade9ee0aeb..6dd355a03033 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -130,7 +130,7 @@ bool hubbub1_verify_allow_pstate_change_high(
static unsigned int max_sampled_pstate_wait_us; /* data collection */
static bool forced_pstate_allow; /* help with revert wa */
- unsigned int debug_data;
+ unsigned int debug_data = 0;
unsigned int i;
if (forced_pstate_allow) {
--
2.34.1
[PATCH 38/43] drm/amd/display: Fix MPCC DTN logging
From: Eric Bernstein
[Why]
DTN only logs 'pipe_count' instances of MPCC.
However in some cases there are different number of
MPCC than DPP (pipe_count).
[How]
Add mpcc_count parameter to resource_pool and set it
during pool construction and use it for DTN logging of
MPCC state.
Signed-off-by: Eric Bernstein
Reviewed-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
index 9033b39e0e0c..c51b717e5622 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
@@ -392,7 +392,7 @@ static unsigned int dcn10_get_mpcc_states(struct dc *dc,
char *pBuf, unsigned in
remaining_buffer -= chars_printed;
pBuf += chars_printed;
- for (i = 0; i < pool->pipe_count; i++) {
+ for (i = 0; i < pool->mpcc_count; i++) {
struct mpcc_state s = {0};
pool->mpc->funcs->read_mpcc_state(pool->mpc, i, );
--
2.34.1
[PATCH 36/43] drm/amd/display: Add missing SFB and OPP_SF
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index f98400efdd9b..e34e445a4013 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -181,6 +181,7 @@ struct dce_mem_input_registers {
SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
+ SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
index bf1ffc3629c7..3d9be87aae45 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
@@ -111,6 +111,7 @@ enum dce110_opp_reg_type {
OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
+ OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
--
2.34.1
[PATCH 34/43] drm/amd/display: Add missing registers
From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- .../include/asic_reg/dcn/dcn_3_0_3_offset.h | 20 +++ .../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h | 11 .../include/asic_reg/dcn/dcn_3_1_2_offset.h | 4 ++ .../include/asic_reg/dcn/dcn_3_1_2_sh_mask.h | 19 ++ .../include/asic_reg/dcn/dcn_3_2_0_offset.h | 60 +++ .../include/asic_reg/dcn/dcn_3_2_0_sh_mask.h | 22 +++ .../asic_reg/dpcs/dpcs_3_0_3_sh_mask.h| 4 +- .../include/asic_reg/dpcs/dpcs_4_2_0_offset.h | 10 8 files changed, 149 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h index e90f31bbb4d2..8b0d2638a6b0 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h @@ -5695,6 +5695,16 @@ #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a +#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 +#define mmDSCC0_DSCC_TEST_DEBUG_DATA0 0x303b +#define mmDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 +#define mmDSCC0_DSCC_TEST_DEBUG_DATA1 0x303c +#define mmDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 +#define mmDSCC0_DSCC_TEST_DEBUG_DATA2 0x303d +#define mmDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 +#define mmDSCC0_DSCC_TEST_DEBUG_DATA3 0x303e +#define mmDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec @@ -5825,6 +5835,16 @@ #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 +#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 +#define mmDSCC1_DSCC_TEST_DEBUG_DATA0 0x3097 +#define mmDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 +#define mmDSCC1_DSCC_TEST_DEBUG_DATA1 0x3098 +#define mmDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 +#define mmDSCC1_DSCC_TEST_DEBUG_DATA2 0x3099 +#define mmDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 +#define mmDSCC1_DSCC_TEST_DEBUG_DATA3 0x309a +#define mmDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 // addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h index 3be176174b20..53f1705f8d99 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h @@ -22265,7 +22265,9 @@ #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x0100L //DSC_TOP0_DSC_DEBUG_CONTROL #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x0001L +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x0070L // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec @@
[PATCH 43/43] drm/amd/display: Enable FGCG for DCN351
From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c| 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index 66ab6aba26aa..8a57adb27264 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -1893,6 +1893,8 @@ static bool dcn351_resource_construct( if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; + /*HW default is to have all the FGCG enabled, SW no need to program them*/ + dc->debug.enable_fine_grain_clock_gating.u32All = 0x; // Init the vm_helper if (dc->vm_helper) vm_helper_init(dc->vm_helper, 16); -- 2.34.1
[PATCH 28/43] drm/amd/display: Initialize DP ref clk with the correct clock
From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index b77804cfde0f..2a5dd3a296b2 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -131,8 +131,8 @@ int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); int dprefclk_wdivider; int dprefclk_src_sel; - int dp_ref_clk_khz; - int target_div = 60; + int dp_ref_clk_khz = 60; + int target_div; /* ASSERT DP Reference Clock source is from DFS*/ REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, _src_sel); -- 2.34.1
[PATCH 29/43] drm/amd/display: Set alpha enable to 0 for some specific formats
From: Rodrigo Siqueira Set alpha_en to 0 in some specific color formats. Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c index 58095ac75506..f8c0cee34080 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c @@ -293,9 +293,11 @@ void dpp3_cnv_setup ( break; case SURFACE_PIXEL_FORMAT_GRPH_RGB10_FIX: pixel_format = 112; + alpha_en = 0; break; case SURFACE_PIXEL_FORMAT_GRPH_BGR10_FIX: pixel_format = 113; + alpha_en = 0; break; case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: pixel_format = 114; @@ -319,9 +321,11 @@ void dpp3_cnv_setup ( break; case SURFACE_PIXEL_FORMAT_GRPH_RGB10_FLOAT: pixel_format = 118; + alpha_en = 0; break; case SURFACE_PIXEL_FORMAT_GRPH_BGR10_FLOAT: pixel_format = 119; + alpha_en = 0; break; default: break; -- 2.34.1
[PATCH 30/43] drm/amd/display: Enable cur_rom_en even if cursor degamma is not enabled
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
index f8c0cee34080..ed1e2f65f5b5 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
@@ -395,9 +395,7 @@ void dpp3_set_cursor_attributes(
if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
- if
(cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
- cur_rom_en = 1;
- }
+ cur_rom_en = 1;
}
REG_UPDATE_3(CURSOR0_CONTROL,
--
2.34.1
[PATCH 35/43] drm/amd/display: Remove redundant RESERVE0 and RESERVE1
From: Rodrigo Siqueira
This commit drops the RESERVE0 and RESERVE1 since both of them can be
summarized as RESERVED.
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index b7ad64e7b62a..b9f8eee5d2d1 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -1222,8 +1222,7 @@ union replay_enable_and_configuration {
unsigned char FREESYNC_PANEL_REPLAY_MODE :1;
unsigned char TIMING_DESYNC_ERROR_VERIFICATION:1;
unsigned char STATE_TRANSITION_ERROR_DETECTION:1;
- unsigned char RESERVED0 :1;
- unsigned char RESERVED1 :4;
+ unsigned char RESERVED:5;
} bits;
unsigned char raw;
};
--
2.34.1
[PATCH 25/43] drm/amd/display: Fix compiler warnings on high compiler warning levels
From: Aric Cyr [why] Enabling higher compiler warning levels results in many issues that can be trivially resolved as well as some potentially critical issues. [how] Fix all compiler warnings found with various compilers and higher warning levels. Primarily, potentially uninitialized variables and unreachable code. Reviewed-by: Leo Li Acked-by: Roman Li Signed-off-by: Aric Cyr Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 -- .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 3 ++- .../drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 3 ++- .../amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 3 ++- .../amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 3 ++- .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 2 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 2 +- .../drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 1 - .../amd/display/dc/dcn32/dcn32_resource_helpers.c | 2 +- .../amd/display/dc/dcn35/dcn35_dio_link_encoder.c | 1 - .../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 -- .../amd/display/dc/dml/dcn30/display_mode_vba_30.c | 1 - .../amd/display/dc/dml/dcn31/display_mode_vba_31.c | 1 - .../gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 2 +- .../display/dc/dml/dcn314/display_mode_vba_314.c | 1 - .../dc/dml/dcn32/display_mode_vba_util_32.c| 14 ++ .../gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 2 +- .../gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c | 2 +- .../drm/amd/display/dc/dml2/display_mode_core.c| 12 +--- drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c | 2 +- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c| 8 .../drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 2 +- .../drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c| 2 +- drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h | 2 +- .../amd/display/dc/link/accessories/link_dp_cts.c | 2 +- drivers/gpu/drm/amd/display/dc/link/link_dpms.c| 2 +- .../dc/link/protocols/link_dp_training_dpia.c | 4 ++-- .../display/dc/resource/dce112/dce112_resource.c | 2 -- .../display/dc/resource/dce120/dce120_resource.c | 2 +- .../amd/display/dc/resource/dcn30/dcn30_resource.c | 2 +- .../amd/display/dc/resource/dcn31/dcn31_resource.c | 2 +- .../display/dc/resource/dcn316/dcn316_resource.c | 2 +- .../drm/amd/display/modules/color/color_gamma.c| 2 +- .../drm/amd/display/modules/hdcp/hdcp2_execution.c | 2 +- 35 files changed, 44 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 05f392501c0a..517c976dbc19 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -1594,8 +1594,6 @@ static bool bios_parser_is_device_id_supported( return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0; break; } - - return false; } static uint32_t bios_parser_get_ss_entry_number( diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index f65bb4c21b7d..5ef0879f6ad9 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -642,7 +642,8 @@ static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params j = -1; - ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL); + static_assert(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL, + "number of reported FCLK DPM levels exceed maximum"); /* Find lowest DPM, FCLK is filled in reverse order*/ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c index aa9fd1dc550a..191d8b969d19 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c @@ -566,7 +566,8 @@ static void vg_clk_mgr_helper_populate_bw_params( j = -1; - ASSERT(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL); + static_assert(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL, + "number of reported FCLK DPM levels exceeds maximum"); /* Find lowest DPM, FCLK is filled in reverse order*/ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c index ce1386e22576..12a7752758b8 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c @@ -562,7 +562,8 @@ static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk j = -1; - ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL); +
[PATCH 32/43] drm/amd/display: Update DSC compute parameter calculation
From: Rodrigo Siqueira
Adjust bytes per pixel calculation to use div_u64.
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
index 36d6c1646a51..59864130cf83 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
@@ -101,7 +101,6 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config
*pps,
{
int ret;
struct drm_dsc_config dsc_cfg;
- unsigned long long tmp;
dsc_params->pps = *pps;
dsc_params->pps.initial_scale_value = 8 * rc->rc_model_size /
(rc->rc_model_size - rc->initial_fullness_offset);
@@ -112,9 +111,9 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config
*pps,
dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 :
64;
ret = drm_dsc_compute_rc_parameters(_cfg);
- tmp = (unsigned long long)dsc_cfg.slice_chunk_size * 0x1000 +
(dsc_cfg.slice_width - 1);
- do_div(tmp, (uint32_t)dsc_cfg.slice_width); //ROUND-UP
- dsc_params->bytes_per_pixel = (uint32_t)tmp;
+ dsc_params->bytes_per_pixel =
+ (uint32_t)(div_u64(((uint64_t)dsc_cfg.slice_chunk_size
* 0x1000 + (dsc_cfg.slice_width - 1)),
+
(uint32_t)dsc_cfg.slice_width)); /* Round-up */
copy_pps_fields(_params->pps, _cfg);
dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits;
--
2.34.1
[PATCH 40/43] drm/amd/display: Add code comments clock and encode code
From: Rodrigo Siqueira
This commit adds some comments to make easier to understand the clock
update for DCN 201, the encode function, and other minor comments.
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
.../amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c| 11 +++
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.c | 2 +-
.../display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c| 4
drivers/gpu/drm/amd/display/dc/resource/Makefile | 6 --
4 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
index 9c90090e7351..f77840dd051e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
@@ -100,7 +100,15 @@ static void dcn201_update_clocks(struct clk_mgr
*clk_mgr_base,
if (clk_mgr_base->clks.dispclk_khz == 0 ||
dc->debug.force_clock_mode & 0x1) {
+ /* this is from resume or boot up, if forced_clock cfg option
+* used, we bypass program dispclk and DPPCLK, but need set them
+* for S3.
+*/
+
force_reset = true;
+ /* force_clock_mode 0x1: force reset the clock even it is the
+* same clock as long as it is in Passive level.
+*/
dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
}
@@ -150,11 +158,14 @@ static void dcn201_update_clocks(struct clk_mgr
*clk_mgr_base,
if (dc->config.forced_clocks == false || (force_reset &&
safe_to_lower)) {
if (dpp_clock_lowered) {
+ // if clock is being lowered, increase DTO before
lowering refclk
dcn20_update_clocks_update_dpp_dto(clk_mgr, context,
safe_to_lower);
dcn20_update_clocks_update_dentist(clk_mgr, context);
} else {
+ // if clock is being raised, increase refclk before
lowering DTO
if (update_dppclk || update_dispclk)
dcn20_update_clocks_update_dentist(clk_mgr,
context);
+ // always update dtos unless clock is lowered and not
safe to lower
dcn20_update_clocks_update_dpp_dto(clk_mgr, context,
safe_to_lower);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.c
index 09ea65acb2c4..63798132ed95 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.c
@@ -103,5 +103,5 @@ void hubbub201_construct(struct dcn20_hubbub *hubbub,
hubbub->masks = hubbub_mask;
hubbub->debug_test_index_pstate = 0xB;
- hubbub->detile_buf_size = 164 * 1024;
+ hubbub->detile_buf_size = 164 * 1024; /* 164KB for DCN2.0 */
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
index 45143459eedd..678db949cfe3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
@@ -474,6 +474,10 @@ static void dcn31_hpo_dp_stream_enc_update_dp_info_packets(
_frame->hdrsmd,
true);
+ /* packetIndex 4 is used for send immediate sdp message, and please
+* use other packetIndex (such as 5,6) for other info packet
+*/
+
if (info_frame->adaptive_sync.valid)
enc->vpg->funcs->update_generic_info_packet(
enc->vpg,
diff --git a/drivers/gpu/drm/amd/display/dc/resource/Makefile
b/drivers/gpu/drm/amd/display/dc/resource/Makefile
index 184b1f23aa77..db9048974d74 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/resource/Makefile
@@ -102,10 +102,6 @@ AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN21)
###
-###
-
-###
-
RESOURCE_DCN30 = dcn30_resource.o
AMD_DAL_RESOURCE_DCN30 = $(addprefix
$(AMDDALPATH)/dc/resource/dcn30/,$(RESOURCE_DCN30))
@@ -202,6 +198,4 @@ AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN351)
###
-###
-
endif
--
2.34.1
[PATCH 26/43] drm/amd/display: Allow RCG for Static Screen + LVP for DCN35
From: Roman Li [Why] We want to block IPS2 for static screen but allow it for power state transitions. [How] Set DalDisableIPS=6 for DCN35 which allows: 1. RCG during static screen 2. RCG during LVP 3. IPS2 for display off / S0i3 Reviewed-by: Nicholas Kazlauskas Acked-by: Roman Li Signed-off-by: Nicholas Kazlauskas Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e9044415bf1f..9220acbdf981 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1726,8 +1726,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; + else + init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; - init_data.flags.disable_ips_in_vpb = 1; + init_data.flags.disable_ips_in_vpb = 0; /* Enable DWB for tested platforms only */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) -- 2.34.1
[PATCH 22/43] drm/amd/display: remove context->dml2 dependency from DML21 wrapper
From: Joshua Aberback
[Why]
When the DML2 wrapper explicitly accesses context->dml2, that creates a
dependency on where dc saves the DML object. This dependency makes it
harder to have multiple co-existing DML objects, which we would like to
have for upcoming functionality.
[How]
- make all DML21 interfaces take in a DML2 object as parameter
- remove all references to context->dml2, use parameter instead
Reviewed-by: Jun Lei
Reviewed-by: Aric Cyr
Acked-by: Roman Li
Signed-off-by: Joshua Aberback
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 6 +++---
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h | 1 +
.../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 2 +-
.../gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 2 +-
.../drm/amd/display/dc/resource/dcn351/dcn351_resource.c| 2 +-
5 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index e2489eaabb20..abf946f089b3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -690,13 +690,13 @@ static void dml2_apply_debug_options(const struct dc *dc,
struct dml2_context *d
}
}
-bool dml2_validate(const struct dc *in_dc, struct dc_state *context, bool
fast_validate)
+bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct
dml2_context *dml2, bool fast_validate)
{
bool out = false;
- if (!(context->bw_ctx.dml2))
+ if (!dml2)
return false;
- dml2_apply_debug_options(in_dc, context->bw_ctx.dml2);
+ dml2_apply_debug_options(in_dc, dml2);
/* Use dml_validate_only for fast_validate path */
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
index 54aff9beb73a..20fd5b8e5117 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
@@ -268,6 +268,7 @@ void dml2_reinit(const struct dc *in_dc,
*/
bool dml2_validate(const struct dc *in_dc,
struct dc_state *context,
+ struct dml2_context *dml2,
bool fast_validate);
/*
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index 0c8dd71148b4..61fd0f2e69fe 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -1799,7 +1799,7 @@ bool dcn32_validate_bandwidth(struct dc *dc,
bool out = false;
if (dc->debug.using_dml2)
- out = dml2_validate(dc, context, fast_validate);
+ out = dml2_validate(dc, context, context->bw_ctx.dml2,
fast_validate);
else
out = dml1_validate(dc, context, fast_validate);
return out;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 479641fedcd4..e0544484e8c0 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -1734,7 +1734,7 @@ static bool dcn35_validate_bandwidth(struct dc *dc,
{
bool out = false;
- out = dml2_validate(dc, context, fast_validate);
+ out = dml2_validate(dc, context, context->bw_ctx.dml2, fast_validate);
if (fast_validate)
return out;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index 07ac9f3130b7..690e1ade361e 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -1714,7 +1714,7 @@ static bool dcn351_validate_bandwidth(struct dc *dc,
{
bool out = false;
- out = dml2_validate(dc, context, fast_validate);
+ out = dml2_validate(dc, context, context->bw_ctx.dml2, fast_validate);
if (fast_validate)
return out;
--
2.34.1
[PATCH 27/43] drm/amd/display: 3.2.279
From: Aric Cyr This version pairs with DMUB FW Release 0.0.211.0 for dcn314, dcn35, dcn351 and brings along the following: - Fix underflow in subvp/non-subvp configs - Fix compiler warnings - Add handling for DC power mode - Add extra logging for DMUB, HUBP and OTG - Add timing pixel encoding for mst mode validation - Expand supported Replay residency mode - Allow HPO PG and RCG for DCN35 - Update pipe topology log to support subvp - Disable Z8 minimum stutter period check for DCN35 - Enable RCO for HDMISTREAMCLK in DCN35 Acked-by: Roman Li Signed-off-by: Aric Cyr Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 4d087137de3b..46be4845ec28 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -51,7 +51,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.278" +#define DC_VER "3.2.279" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.34.1
[PATCH 20/43] drm/amd/display: add root clock control function pointer to fix display corruption
From: "Xi (Alex) Liu"
[Why and how]
External display has corruption because no root clock control function. Add the
function pointer to fix the issue.
Reviewed-by: Daniel Miess
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Xi (Alex) Liu
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index b5f4bae16177..c54f3518c947 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -145,6 +145,7 @@ static const struct hwseq_private_funcs
dcn351_private_funcs = {
//.hubp_pg_control = dcn35_hubp_pg_control,
.enable_power_gating_plane = dcn35_enable_power_gating_plane,
.dpp_root_clock_control = dcn35_dpp_root_clock_control,
+ .dpstream_root_clock_control = dcn35_dpstream_root_clock_control,
.program_all_writeback_pipes_in_tree =
dcn30_program_all_writeback_pipes_in_tree,
.update_odm = dcn35_update_odm,
.set_hdr_multiplier = dcn10_set_hdr_multiplier,
--
2.34.1
[PATCH 23/43] drm/amd/display: Add handling for DC power mode
From: Joshua Aberback
[Why]
Future implementations will require a distinction between AC power and
DC power (wall power and battery power, respectively). To accomplish this,
adding a power mode parameter to certain dc interfaces, and adding a
separate DML2 instance for DC mode validation. Default behaviour unchanged.
Reviewed-by: Jun Lei
Reviewed-by: Aric Cyr
Acked-by: Roman Li
Signed-off-by: Joshua Aberback
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 ++---
drivers/gpu/drm/amd/display/dc/core/dc.c | 37 ++-
.../gpu/drm/amd/display/dc/core/dc_state.c| 29 +--
drivers/gpu/drm/amd/display/dc/dc.h | 13 +--
drivers/gpu/drm/amd/display/dc/dc_state.h | 2 +-
drivers/gpu/drm/amd/display/dc/dc_stream.h| 8
drivers/gpu/drm/amd/display/dc/dc_types.h | 16
.../drm/amd/display/dc/dml2/dml2_wrapper.h| 2 +
.../gpu/drm/amd/display/dc/inc/core_types.h | 3 ++
.../dc/resource/dcn32/dcn32_resource.c| 16 +++-
.../dc/resource/dcn321/dcn321_resource.c | 12 +-
.../dc/resource/dcn35/dcn35_resource.c| 4 +-
.../dc/resource/dcn351/dcn351_resource.c | 4 +-
13 files changed, 120 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 08ca842af727..e9044415bf1f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2629,6 +2629,7 @@ static enum dc_status
amdgpu_dm_commit_zero_streams(struct dc *dc)
int i;
struct dc_stream_state *del_streams[MAX_PIPES];
int del_streams_count = 0;
+ struct dc_commit_streams_params params = {};
memset(del_streams, 0, sizeof(del_streams));
@@ -2655,7 +2656,9 @@ static enum dc_status
amdgpu_dm_commit_zero_streams(struct dc *dc)
goto fail;
}
- res = dc_commit_streams(dc, context->streams, context->stream_count);
+ params.streams = context->streams;
+ params.stream_count = context->stream_count;
+ res = dc_commit_streams(dc, );
fail:
dc_state_release(context);
@@ -2877,6 +2880,7 @@ static int dm_resume(void *handle)
struct dc_state *dc_state;
int i, r, j, ret;
bool need_hotplug = false;
+ struct dc_commit_streams_params commit_params = {};
if (dm->dc->caps.ips_support) {
dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
@@ -2926,7 +2930,9 @@ static int dm_resume(void *handle)
dc_enable_dmub_outbox(adev->dm.dc);
}
- WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams,
dc_state->stream_count));
+ commit_params.streams = dc_state->streams;
+ commit_params.stream_count = dc_state->stream_count;
+ WARN_ON(!dc_commit_streams(dm->dc, _params));
dm_gpureset_commit_state(dm->cached_dc_state, dm);
@@ -2943,7 +2949,7 @@ static int dm_resume(void *handle)
}
/* Recreate dc_state - DC invalidates it when setting power state to
S3. */
dc_state_release(dm_state->context);
- dm_state->context = dc_state_create(dm->dc);
+ dm_state->context = dc_state_create(dm->dc, NULL);
/* TODO: Remove dc_state->dccg, use dc->dccg directly. */
/* Before powering on DC we need to re-initialize DMUB. */
@@ -6802,7 +6808,7 @@ static enum dc_status
dm_validate_stream_and_context(struct dc *dc,
if (!dc_plane_state)
goto cleanup;
- dc_state = dc_state_create(dc);
+ dc_state = dc_state_create(dc, NULL);
if (!dc_state)
goto cleanup;
@@ -8858,6 +8864,7 @@ static void amdgpu_dm_commit_streams(struct
drm_atomic_state *state,
struct drm_connector *connector;
bool mode_set_reset_required = false;
u32 i;
+ struct dc_commit_streams_params params = {dc_state->streams,
dc_state->stream_count};
/* Disable writeback */
for_each_old_connector_in_state(state, connector, old_con_state, i) {
@@ -8994,7 +9001,7 @@ static void amdgpu_dm_commit_streams(struct
drm_atomic_state *state,
dm_enable_per_frame_crtc_master_sync(dc_state);
mutex_lock(>dc_lock);
- WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams,
dc_state->stream_count));
+ WARN_ON(!dc_commit_streams(dm->dc, ));
/* Allow idle optimization when vblank count is 0 for display off */
if (dm->active_vblank_irq_count == 0)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c3510cdd0ec8..f44025eacc0a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1089,8 +1089,7 @@ static bool dc_construct(struct dc *dc,
* is initialized in dc_create_resource_pool
[PATCH 19/43] drm/amd/display: Disable Z8 minimum stutter period check for DCN35
From: Nicholas Kazlauskas
[Why]
The threshold is no longer useful for blocking suboptimal power states
for DCN35 based on real measurement.
[How]
Reduce to the minimum threshold duration, 1us.
Reviewed-by: Gabe Teeger
Acked-by: Roman Li
Signed-off-by: Nicholas Kazlauskas
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index f1efce1bfbec..479641fedcd4 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -764,7 +764,7 @@ static const struct dc_debug_options debug_defaults_drv = {
},
.seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
.enable_z9_disable_interface = true, /* Allow support for the PMFW
interface for disable Z9*/
- .minimum_z8_residency_time = 2100,
+ .minimum_z8_residency_time = 1, /* Always allow when other conditions
are met */
.using_dml2 = true,
.support_eDP1_5 = true,
.enable_hpo_pg_support = false,
--
2.34.1
[PATCH 24/43] drm/amd/display: move build test pattern params as part of pipe resource update for odm
From: Wenjing Liu
[why]
Move built test pattern as part of pipe resource update for odm to ensure we
rebuild
test pattern params every time we have an ODM update
Reviewed-by: George Shen
Acked-by: Roman Li
Signed-off-by: Wenjing Liu
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 24 ---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 7 ++
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 8 +++
.../display/dc/dml2/dml2_dc_resource_mgmt.c | 6 +
.../drm/amd/display/dc/dml2/dml2_wrapper.h| 1 +
5 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f44025eacc0a..5a93278fa246 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3235,14 +3235,6 @@ static bool update_planes_and_stream_state(struct dc *dc,
BREAK_TO_DEBUGGER();
goto fail;
}
-
- for (i = 0; i < context->stream_count; i++) {
- struct pipe_ctx *otg_master =
resource_get_otg_master_for_stream(>res_ctx,
- context->streams[i]);
-
- if (otg_master && otg_master->stream->test_pattern.type
!= DP_TEST_PATTERN_VIDEO_MODE)
-
resource_build_test_pattern_params(>res_ctx, otg_master);
- }
}
update_seamless_boot_flags(dc, context, surface_count, stream);
@@ -3338,12 +3330,26 @@ static void commit_planes_do_stream_update(struct dc
*dc,
}
if (stream_update->pending_test_pattern) {
- dc_link_dp_set_test_pattern(stream->link,
+ /*
+* test pattern params depends on ODM topology
+* changes that we could be applying to front
+* end. Since at the current stage front end
+* changes are not yet applied. We can only
+* apply test pattern in hw based on current
+* state and populate the final test pattern
+* params in new state. If current and new test
+* pattern params are different as result of
+* different ODM topology being used, it will be
+* detected and handle during front end
+* programming update.
+*/
+ dc->link_srv->dp_set_test_pattern(stream->link,
stream->test_pattern.type,
stream->test_pattern.color_space,
stream->test_pattern.p_link_settings,
stream->test_pattern.p_custom_pattern,
stream->test_pattern.cust_pattern_size);
+
resource_build_test_pattern_params(>res_ctx, pipe_ctx);
}
if (stream_update->dpms_off) {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index c4a3484554b0..d48a181d2249 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1457,6 +1457,9 @@ void resource_build_test_pattern_params(struct
resource_context *res_ctx,
controller_color_space = convert_dp_to_controller_color_space(
otg_master->stream->test_pattern.color_space);
+ if (controller_test_pattern == CONTROLLER_DP_TEST_PATTERN_VIDEOMODE)
+ return;
+
odm_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx,
opp_heads);
odm_slice_width = h_active / odm_cnt;
@@ -2325,6 +2328,9 @@ static bool
update_pipe_params_after_odm_slice_count_change(
if (pool->funcs->build_pipe_pix_clk_params)
pool->funcs->build_pipe_pix_clk_params(otg_master);
+
+ if (otg_master->stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE)
+ resource_build_test_pattern_params(>res_ctx,
otg_master);
return result;
}
@@ -5082,6 +5088,7 @@ void resource_init_common_dml2_callbacks(struct dc *dc,
struct dml2_configuratio
{
dml2_options->callbacks.dc = dc;
dml2_options->callbacks.build_scaling_params =
_build_scaling_params;
+ dml2_options->callbacks.build_test_pattern_params =
_build_test_pattern_params;
dml2_options->callbacks.acquire_secondary_pipe_for_mpc_odm =
_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
[PATCH 21/43] drm/amd/display: Add extra DMUB logging to track message timeout
From: Alvin Lee
[Description]
- Add logging for first DMUB inbox message that timed out to diagnostic
data
- It is useful to track the first failed message for debug purposes
because once DMUB becomes hung (typically on a message), it will
remain hung and all subsequent messages. In these cases we're
interested in knowing which is the first message that failed.
Reviewed-by: Josip Pavic
Acked-by: Roman Li
Signed-off-by: Alvin Lee
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c| 10 +-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 17 -
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 1 +
.../gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 1 +
.../gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 2 ++
.../gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 1 +
6 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 9ae0e602e737..34d199b08dd9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -23,6 +23,7 @@
*
*/
+#include "dm_services.h"
#include "dc.h"
#include "dc_dmub_srv.h"
#include "../dmub/dmub_srv.h"
@@ -198,6 +199,11 @@ bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv
*dc_dmub_srv,
if (status != DMUB_STATUS_OK) {
DC_LOG_DEBUG("No reply for DMUB command: status=%d\n",
status);
+ if (!dmub->debug.timeout_occured) {
+ dmub->debug.timeout_occured = true;
+ dmub->debug.timeout_cmd = *cmd_list;
+ dmub->debug.timestamp =
dm_get_timestamp(dc_dmub_srv->ctx);
+ }
dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
return false;
}
@@ -904,6 +910,7 @@ bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv
*dc_dmub_srv, struct dmu
void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
{
struct dmub_diagnostic_data diag_data = {0};
+ uint32_t i;
if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
DC_LOG_ERROR("%s: invalid parameters.", __func__);
@@ -935,7 +942,8 @@ void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv
*dc_dmub_srv)
DC_LOG_DEBUG("scratch [13] : %08x", diag_data.scratch[13]);
DC_LOG_DEBUG("scratch [14] : %08x", diag_data.scratch[14]);
DC_LOG_DEBUG("scratch [15] : %08x", diag_data.scratch[15]);
- DC_LOG_DEBUG("pc : %08x", diag_data.pc);
+ for (i = 0; i < DMUB_PC_SNAPSHOT_COUNT; i++)
+ DC_LOG_DEBUG("pc[%d] : %08x", i,
diag_data.pc[i]);
DC_LOG_DEBUG("unk_fault_addr : %08x",
diag_data.undefined_address_fault_addr);
DC_LOG_DEBUG("inst_fault_addr: %08x",
diag_data.inst_fetch_fault_addr);
DC_LOG_DEBUG("data_fault_addr: %08x",
diag_data.data_write_fault_addr);
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 7785908a6676..662bdb0e5d3d 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -71,6 +71,8 @@
extern "C" {
#endif
+#define DMUB_PC_SNAPSHOT_COUNT 10
+
/* Forward declarations */
struct dmub_srv;
struct dmub_srv_common_regs;
@@ -299,6 +301,17 @@ struct dmub_srv_hw_params {
enum dmub_ips_disable_type disable_ips;
};
+/**
+ * struct dmub_srv_debug - Debug info for dmub_srv
+ * @timeout_occured: Indicates a timeout occured on any message from driver to
dmub
+ * @timeout_cmd: first cmd sent from driver that timed out - subsequent
timeouts are not stored
+ */
+struct dmub_srv_debug {
+ bool timeout_occured;
+ union dmub_rb_cmd timeout_cmd;
+ unsigned long long timestamp;
+};
+
/**
* struct dmub_diagnostic_data - Diagnostic data retrieved from DMCUB for
* debugging purposes, including logging, crash analysis, etc.
@@ -306,7 +319,7 @@ struct dmub_srv_hw_params {
struct dmub_diagnostic_data {
uint32_t dmcub_version;
uint32_t scratch[17];
- uint32_t pc;
+ uint32_t pc[DMUB_PC_SNAPSHOT_COUNT];
uint32_t undefined_address_fault_addr;
uint32_t inst_fetch_fault_addr;
uint32_t data_write_fault_addr;
@@ -317,6 +330,7 @@ struct dmub_diagnostic_data {
uint32_t inbox0_wptr;
uint32_t inbox0_size;
uint32_t gpint_datain0;
+ struct dmub_srv_debug timeout_info;
uint8_t is_dmcub_enabled : 1;
uint8_t is_dmcub_soft_reset : 1;
uint8_t is_dmcub_secure_reset : 1;
@@ -506,6 +520,7 @@ struct dmub_srv {
struct dmub_visual_confirm_color visual_confirm_color;
enum dmub_srv_power_state_type power_state;
+ struct dmub_srv_debug debug;
};
/**
diff --git
[PATCH 14/43] drm/amd/display: Enable RCO for HDMISTREAMCLK in DCN35
From: Daniel Miess
[Why & How]
Enable root clock optimization for HDMISTREAMCLK and only
disable it when it's actively being used.
Reviewed-by: Charlene Liu
Acked-by: Roman Li
Signed-off-by: Daniel Miess
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dc.h| 1 +
.../drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c| 14 --
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 3ed41cf6a59d..b026004b713a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -696,6 +696,7 @@ enum pg_hw_pipe_resources {
PG_OPP,
PG_OPTC,
PG_DPSTREAM,
+ PG_HDMISTREAM,
PG_HW_PIPE_RESOURCES_NUM_ELEMENT
};
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index c2275a8b4ecc..b94a85380d73 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -988,6 +988,9 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct
dc_state *context,
if (!hpo_frl_stream_enc_acquired && !hpo_dp_stream_enc_acquired)
update_state->pg_res_update[PG_HPO] = true;
+ if (hpo_frl_stream_enc_acquired)
+ update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true;
+
update_state->pg_res_update[PG_DWB] = true;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -1125,6 +1128,9 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct
dc_state *context,
if (hpo_frl_stream_enc_acquired || hpo_dp_stream_enc_acquired)
update_state->pg_res_update[PG_HPO] = true;
+ if (hpo_frl_stream_enc_acquired)
+ update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true;
+
}
/**
@@ -1249,7 +1255,7 @@ void dcn35_root_clock_control(struct dc *dc,
if (!pg_cntl)
return;
/*enable root clock first when power up*/
- if (power_on)
+ if (power_on) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
update_state->pg_pipe_res_update[PG_DPP][i]) {
@@ -1260,6 +1266,8 @@ void dcn35_root_clock_control(struct dc *dc,
if
(dc->hwseq->funcs.dpstream_root_clock_control)
dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);
}
+
+ }
for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
if (update_state->pg_pipe_res_update[PG_DSC][i]) {
if (power_on) {
@@ -1272,7 +1280,7 @@ void dcn35_root_clock_control(struct dc *dc,
}
}
/*disable root clock first when power down*/
- if (!power_on)
+ if (!power_on) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
update_state->pg_pipe_res_update[PG_DPP][i]) {
@@ -1283,6 +1291,8 @@ void dcn35_root_clock_control(struct dc *dc,
if
(dc->hwseq->funcs.dpstream_root_clock_control)
dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);
}
+
+ }
}
void dcn35_prepare_bandwidth(
--
2.34.1
[PATCH 18/43] drm/amd/display: Add extra logging for HUBP and OTG
From: Alvin Lee
[Description]
Add extra logging for DCSURF_FLIP_CNTL, DCHUBP_CNTL,
OTG_MASTER_EN, and OTG_DOUBLE_BUFFER_CONTROL for more
debuggability for a system crash.
Reviewed-by: Samson Tam
Acked-by: Roman Li
Signed-off-by: Alvin Lee
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 6 ++
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c | 3 +++
drivers/gpu/drm/amd/display/dc/inc/hw/optc.h | 2 ++
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c | 3 +++
5 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index 09784222cc03..69119b2fdce2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -692,6 +692,7 @@ struct dcn_hubp_state {
uint32_t primary_meta_addr_hi;
uint32_t uclk_pstate_force;
uint32_t hubp_cntl;
+ uint32_t flip_control;
};
struct dcn10_hubp {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index 89c3bf0fe0c9..6bba020ad6fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -1331,6 +1331,12 @@ void hubp2_read_state(struct hubp *hubp)
SWATH_HEIGHT_C, _regs->rq_regs_c.swath_height,
PTE_ROW_HEIGHT_LINEAR_C,
_regs->rq_regs_c.pte_row_height_linear);
+ if (REG(DCHUBP_CNTL))
+ s->hubp_cntl = REG_READ(DCHUBP_CNTL);
+
+ if (REG(DCSURF_FLIP_CONTROL))
+ s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);
+
}
static void hubp2_validate_dml_output(struct hubp *hubp,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
index 75547ce86c09..60a64d290352 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
@@ -455,6 +455,9 @@ void hubp3_read_state(struct hubp *hubp)
if (REG(DCHUBP_CNTL))
s->hubp_cntl = REG_READ(DCHUBP_CNTL);
+ if (REG(DCSURF_FLIP_CONTROL))
+ s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);
+
}
void hubp3_setup(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
index 9a8bf6ec70ea..8d32e525f05a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
@@ -93,6 +93,8 @@ struct dcn_otg_state {
uint32_t vertical_interrupt1_line;
uint32_t vertical_interrupt2_en;
uint32_t vertical_interrupt2_line;
+ uint32_t otg_master_update_lock;
+ uint32_t otg_double_buffer_control;
};
void optc1_read_otg_state(struct optc *optc1, struct dcn_otg_state *s);
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
index 0e8f4f36c87c..f109a101d84f 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
@@ -1383,6 +1383,9 @@ void optc1_read_otg_state(struct optc *optc1,
REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,
OTG_VERTICAL_INTERRUPT2_LINE_START,
>vertical_interrupt2_line);
+
+ s->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK);
+ s->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);
}
bool optc1_get_otg_active_size(struct timing_generator *optc,
--
2.34.1
[PATCH 16/43] drm/amd/display: Skip on writeback when it's not applicable
From: Alex Hung
[WHY]
dynamic memory safety error detector (KASAN) catches and generates error
messages "BUG: KASAN: slab-out-of-bounds" as writeback connector does not
support certain features which are not initialized.
[HOW]
Skip them when connector type is DRM_MODE_CONNECTOR_WRITEBACK.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3199
Reviewed-by: Harry Wentland
Reviewed-by: Rodrigo Siqueira
Acked-by: Roman Li
Signed-off-by: Alex Hung
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d98632f37c0d..08ca842af727 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3047,6 +3047,10 @@ static int dm_resume(void *handle)
/* Do mst topology probing after resuming cached state*/
drm_connector_list_iter_begin(ddev, );
drm_for_each_connector_iter(connector, ) {
+
+ if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
+ continue;
+
aconnector = to_amdgpu_dm_connector(connector);
if (aconnector->dc_link->type != dc_connection_mst_branch ||
aconnector->mst_root)
@@ -5926,6 +5930,9 @@ get_highest_refresh_rate_mode(struct amdgpu_dm_connector
*aconnector,
>base.probed_modes :
>base.modes;
+ if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
+ return NULL;
+
if (aconnector->freesync_vid_base.clock != 0)
return >freesync_vid_base;
@@ -8768,10 +8775,10 @@ static void amdgpu_dm_commit_audio(struct drm_device
*dev,
if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
continue;
+notify:
if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
continue;
-notify:
aconnector = to_amdgpu_dm_connector(connector);
mutex_lock(>dm.audio_lock);
--
2.34.1
[PATCH 17/43] drm/amd/display: Add OTG check for set AV mute
From: "Leo (Hanghong) Ma"
[Why && How]
OTG can be disabled before setting dpms on. Add check to skip wait
when setting AV mute if OTG is disabled.
Reviewed-by: Wenjing Liu
Acked-by: Roman Li
Signed-off-by: Leo (Hanghong) Ma
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 1f3ddee1ec1b..774605a029e8 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -813,7 +813,7 @@ void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool
enable)
enable);
/* Wait for two frame to make sure AV mute is sent out */
- if (enable) {
+ if (enable &&
pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) {
pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
CRTC_STATE_VACTIVE);
pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
CRTC_STATE_VBLANK);
pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
CRTC_STATE_VACTIVE);
--
2.34.1
[PATCH 15/43] drm/amd/display: Allow HPO PG for DCN35
From: Duncan Ma
[Why]
HPO can be power gated unconditionally for
DCN35.
[How]
Set disable flag to false.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Duncan Ma
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 91c6eff79282..f1efce1bfbec 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -721,7 +721,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_dpp_power_gate = true,
.disable_hubp_power_gate = true,
.disable_optc_power_gate = true, /*should the same as above two*/
- .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
+ .disable_hpo_power_gate = false, /*dmubfw force domain25 on*/
.disable_clock_gate = false,
.disable_dsc_power_gate = true,
.vsr_support = true,
--
2.34.1
[PATCH 11/43] drm/amd/display: update pipe topology log to support subvp
From: Wenjing Liu
[why]
There is an ambiguity in subvp pipe topology log. The log doesn't show
subvp relation to main stream and it is not clear that certain stream
is an internal stream for subvp pipes.
[how]
Separate subvp pipe topology logging from main pipe topology. Log main
stream indices instead of the internal stream for subvp pipes.
The following is a sample log showing 2 streams with subvp enabled on
both:
pipe topology update
| plane0 slice0 stream0|
|DPP1OPP1OTG1|
| plane0 slice0 stream1|
|DPP0OPP0OTG0|
|(phantom pipes) |
| plane0 slice0 stream0|
|DPP3OPP3OTG3|
| plane0 slice0 stream1|
|DPP2OPP2OTG2|
||
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Wenjing Liu
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 96 +--
1 file changed, 65 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 601af21b2df9..c4a3484554b0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2193,50 +2193,84 @@ static void resource_log_pipe(struct dc *dc, struct
pipe_ctx *pipe,
}
}
-void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)
+static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state,
+ struct pipe_ctx *otg_master, int stream_idx)
{
- struct pipe_ctx *otg_master;
struct pipe_ctx *opp_heads[MAX_PIPES];
struct pipe_ctx *dpp_pipes[MAX_PIPES];
- int stream_idx, slice_idx, dpp_idx, plane_idx, slice_count, dpp_count;
+ int slice_idx, dpp_idx, plane_idx, slice_count, dpp_count;
bool is_primary;
DC_LOGGER_INIT(dc->ctx->logger);
+ slice_count = resource_get_opp_heads_for_otg_master(otg_master,
+ >res_ctx, opp_heads);
+ for (slice_idx = 0; slice_idx < slice_count; slice_idx++) {
+ plane_idx = -1;
+ if (opp_heads[slice_idx]->plane_state) {
+ dpp_count = resource_get_dpp_pipes_for_opp_head(
+ opp_heads[slice_idx],
+ >res_ctx,
+ dpp_pipes);
+ for (dpp_idx = 0; dpp_idx < dpp_count; dpp_idx++) {
+ is_primary = !dpp_pipes[dpp_idx]->top_pipe ||
+
dpp_pipes[dpp_idx]->top_pipe->plane_state != dpp_pipes[dpp_idx]->plane_state;
+ if (is_primary)
+ plane_idx++;
+ resource_log_pipe(dc, dpp_pipes[dpp_idx],
+ stream_idx, slice_idx,
+ plane_idx, slice_count,
+ is_primary);
+ }
+ } else {
+ resource_log_pipe(dc, opp_heads[slice_idx],
+ stream_idx, slice_idx, plane_idx,
+ slice_count, true);
+ }
+
+ }
+}
+
+static int resource_stream_to_stream_idx(struct dc_state *state,
+ struct dc_stream_state *stream)
+{
+ int i, stream_idx = -1;
+
+ for (i = 0; i < state->stream_count; i++)
+ if (state->streams[i] == stream) {
+ stream_idx = i;
+ break;
+ }
+ return stream_idx;
+}
+
+void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)
+{
+ struct pipe_ctx *otg_master;
+ int stream_idx, phantom_stream_idx;
+ DC_LOGGER_INIT(dc->ctx->logger);
+
DC_LOG_DC("pipe topology update");
DC_LOG_DC(" ");
for (stream_idx = 0; stream_idx < state->stream_count; stream_idx++) {
+ if (state->streams[stream_idx]->is_phantom)
+ continue;
+
otg_master = resource_get_otg_master_for_stream(
>res_ctx, state->streams[stream_idx]);
- if (!otg_master || otg_master->stream_res.tg == NULL) {
- DC_LOG_DC("topology update: otg_master NULL stream_idx
%d!\n", stream_idx);
- return;
- }
- slice_count = resource_get_opp_heads_for_otg_master(otg_master,
- >res_ctx, opp_heads);
- for (slice_idx = 0; slice_idx < slice_count; slice_idx++) {
- plane_idx = -1;
- if (opp_heads[slice_idx]->plane_state) {
- dpp_count = resource_get_dpp_pipes_for_opp_head(
-
[PATCH 08/43] drm/amd/display: FEC overhead should be checked once for mst slot nums
From: Hersen Wu
[Why] Mst slot nums equals to pbn / pbn_div.
Today, pbn_div refers to dm_mst_get_pbn_divider ->
dc_link_bandwidth_kbps. In dp_link_bandwidth_kbps,
which includes effect of FEC overhead already. As
result, we should not include effect of FEC overhead
again while calculating pbn by kpbs_to_peak_pbn
(stream_kbps).
[How] Include FEC overhead within dp_link_bandwidth_kbps.
Remove FEC overhead from kbps_to_peak_pbn.
Reviewed-by: Wayne Lin
Acked-by: Roman Li
Signed-off-by: Hersen Wu
Tested-by: Daniel Wheeler
---
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 37 +--
.../display/amdgpu_dm/amdgpu_dm_mst_types.h | 3 --
2 files changed, 10 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index ad3170b72a47..0b03e659fdf3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -791,25 +791,12 @@ struct dsc_mst_fairness_params {
struct amdgpu_dm_connector *aconnector;
};
-static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link)
-{
- u8 link_coding_cap;
- uint16_t fec_overhead_multiplier_x1000 =
PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B;
-
- link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link);
- if (link_coding_cap == DP_128b_132b_ENCODING)
- fec_overhead_multiplier_x1000 =
PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B;
-
- return fec_overhead_multiplier_x1000;
-}
-
-static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000)
+static int kbps_to_peak_pbn(int kbps)
{
u64 peak_kbps = kbps;
peak_kbps *= 1006;
- peak_kbps *= fec_overhead_multiplier_x1000;
- peak_kbps = div_u64(peak_kbps, 1000 * 1000);
+ peak_kbps = div_u64(peak_kbps, 1000);
return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
}
@@ -910,12 +897,11 @@ static int increase_dsc_bpp(struct drm_atomic_state
*state,
int link_timeslots_used;
int fair_pbn_alloc;
int ret = 0;
- uint16_t fec_overhead_multiplier_x1000 =
get_fec_overhead_multiplier(dc_link);
for (i = 0; i < count; i++) {
if (vars[i + k].dsc_enabled) {
initial_slack[i] =
- kbps_to_peak_pbn(params[i].bw_range.max_kbps,
fec_overhead_multiplier_x1000) - vars[i + k].pbn;
+ kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i
+ k].pbn;
bpp_increased[i] = false;
remaining_to_increase += 1;
} else {
@@ -1011,7 +997,6 @@ static int try_disable_dsc(struct drm_atomic_state *state,
int next_index;
int remaining_to_try = 0;
int ret;
- uint16_t fec_overhead_multiplier_x1000 =
get_fec_overhead_multiplier(dc_link);
for (i = 0; i < count; i++) {
if (vars[i + k].dsc_enabled
@@ -1041,7 +1026,7 @@ static int try_disable_dsc(struct drm_atomic_state *state,
if (next_index == -1)
break;
- vars[next_index].pbn =
kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps,
fec_overhead_multiplier_x1000);
+ vars[next_index].pbn =
kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
ret = drm_dp_atomic_find_time_slots(state,
params[next_index].port->mgr,
params[next_index].port,
@@ -1054,7 +1039,8 @@ static int try_disable_dsc(struct drm_atomic_state *state,
vars[next_index].dsc_enabled = false;
vars[next_index].bpp_x16 = 0;
} else {
- vars[next_index].pbn =
kbps_to_peak_pbn(params[next_index].bw_range.max_kbps,
fec_overhead_multiplier_x1000);
+ vars[next_index].pbn = kbps_to_peak_pbn(
+ params[next_index].bw_range.max_kbps);
ret = drm_dp_atomic_find_time_slots(state,
params[next_index].port->mgr,
params[next_index].port,
@@ -1083,7 +1069,6 @@ static int compute_mst_dsc_configs_for_link(struct
drm_atomic_state *state,
int count = 0;
int i, k, ret;
bool debugfs_overwrite = false;
- uint16_t fec_overhead_multiplier_x1000 =
get_fec_overhead_multiplier(dc_link);
memset(params, 0, sizeof(params));
@@ -1148,7 +1133,7 @@ static int compute_mst_dsc_configs_for_link(struct
drm_atomic_state *state,
/* Try no compression */
for (i = 0; i < count; i++) {
vars[i + k].aconnector = params[i].aconnector;
- vars[i + k].pbn =
[PATCH 13/43] drm/amd/display: Add dummy interface for tracing DCN32 SMU messages
From: George Shen
[Why/How]
Some issues may require a trace of the previous SMU messages from DC to
understand the context and aid in debugging. Actual logging to be
implemented when needed.
Reviewed-by: Josip Pavic
Acked-by: Roman Li
Signed-off-by: George Shen
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 8
.../display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 5 -
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c | 9 +
drivers/gpu/drm/amd/display/dc/dm_services.h | 10 ++
4 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index d9e33c6bccd9..0005f5f8f34f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -52,4 +52,12 @@ void dm_perf_trace_timestamp(const char *func_name, unsigned
int line, struct dc
func_name, line);
}
+void dm_trace_smu_msg(uint32_t msg_id, uint32_t param_in, struct dc_context
*ctx)
+{
+}
+
+void dm_trace_smu_delay(uint32_t delay, struct dc_context *ctx)
+{
+}
+
/ power component interfaces /
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
index bdbf18306698..64c2b88dfc9f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
@@ -54,6 +54,7 @@
*/
static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr,
unsigned int delay_us, unsigned int max_retries)
{
+ const uint32_t initial_max_retries = max_retries;
uint32_t reg = 0;
do {
@@ -69,7 +70,7 @@ static uint32_t dcn30_smu_wait_for_response(struct
clk_mgr_internal *clk_mgr, un
/* handle DALSMC_Result_CmdRejectedBusy? */
- /* Log? */
+ TRACE_SMU_DELAY(delay_us * (initial_max_retries - max_retries),
clk_mgr->base.ctx);
return reg;
}
@@ -89,6 +90,8 @@ static bool dcn30_smu_send_msg_with_param(struct
clk_mgr_internal *clk_mgr, uint
/* Trigger the message transaction by writing the message ID */
REG_WRITE(DAL_MSG_REG, msg_id);
+ TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx);
+
result = dcn30_smu_wait_for_response(clk_mgr, 10, 20);
if (IS_SMU_TIMEOUT(result)) {
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
index df244b175fdb..f2f60478b1a6 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
@@ -49,6 +49,7 @@
*/
static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr,
unsigned int delay_us, unsigned int max_retries)
{
+ const uint32_t initial_max_retries = max_retries;
uint32_t reg = 0;
do {
@@ -62,6 +63,8 @@ static uint32_t dcn32_smu_wait_for_response(struct
clk_mgr_internal *clk_mgr, un
udelay(delay_us);
} while (max_retries--);
+ TRACE_SMU_DELAY(delay_us * (initial_max_retries - max_retries),
clk_mgr->base.ctx);
+
return reg;
}
@@ -79,6 +82,8 @@ static bool dcn32_smu_send_msg_with_param(struct
clk_mgr_internal *clk_mgr, uint
/* Trigger the message transaction by writing the message ID */
REG_WRITE(DAL_MSG_REG, msg_id);
+ TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx);
+
/* Wait for response */
if (dcn32_smu_wait_for_response(clk_mgr, 10, 20) ==
DALSMC_Result_OK) {
if (param_out)
@@ -115,6 +120,8 @@ static uint32_t dcn32_smu_wait_for_response_delay(struct
clk_mgr_internal *clk_m
*total_delay_us += delay_us;
} while (max_retries--);
+ TRACE_SMU_DELAY(*total_delay_us, clk_mgr->base.ctx);
+
return reg;
}
@@ -135,6 +142,8 @@ static bool dcn32_smu_send_msg_with_param_delay(struct
clk_mgr_internal *clk_mgr
/* Trigger the message transaction by writing the message ID */
REG_WRITE(DAL_MSG_REG, msg_id);
+ TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx);
+
/* Wait for response */
if (dcn32_smu_wait_for_response_delay(clk_mgr, 10, 20, _us)
== DALSMC_Result_OK) {
if (param_out)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h
b/drivers/gpu/drm/amd/display/dc/dm_services.h
index d0eed3b4771e..9405c47ee2a9 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -274,6 +274,16 @@ void dm_perf_trace_timestamp(const char *func_name,
unsigned int line, struct dc
#define PERF_TRACE()
[PATCH 10/43] drm/amd/display: Add dmub additional interface support for FAMS
From: Dillon Varone
[WHY]
Update dmub and driver interface for future FAMS revisions.
Reviewed-by: Anthony Koo
Acked-by: Roman Li
Signed-off-by: Dillon Varone
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 6 +-
5 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index af3a26c2656b..1f3ddee1ec1b 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -799,7 +799,7 @@ void dcn30_init_hw(struct dc *dc)
// Get DMCUB capabilities
dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
- dc->caps.dmub_caps.mclk_sw =
dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
+ dc->caps.dmub_caps.mclk_sw =
dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;
}
void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index a760f0c6fe98..9ab475a87545 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -273,7 +273,7 @@ void dcn31_init_hw(struct dc *dc)
// Get DMCUB capabilities
dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
- dc->caps.dmub_caps.mclk_sw =
dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
+ dc->caps.dmub_caps.mclk_sw =
dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;
}
void dcn31_dsc_pg_control(
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 0f522f8a7228..9aea4a088652 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -953,7 +953,7 @@ void dcn32_init_hw(struct dc *dc)
dc->caps.dmub_caps.psr =
dc->ctx->dmub_srv->dmub->feature_caps.psr;
dc->caps.dmub_caps.subvp_psr =
dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;
dc->caps.dmub_caps.gecc_enable =
dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;
- dc->caps.dmub_caps.mclk_sw =
dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
+ dc->caps.dmub_caps.mclk_sw =
dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;
if (dc->ctx->dmub_srv->dmub->fw_version <
DMUB_FW_VERSION(7, 0, 35)) {
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 9499295f4582..c2275a8b4ecc 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -349,7 +349,7 @@ void dcn35_init_hw(struct dc *dc)
if (dc->ctx->dmub_srv) {
dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
dc->caps.dmub_caps.psr =
dc->ctx->dmub_srv->dmub->feature_caps.psr;
- dc->caps.dmub_caps.mclk_sw =
dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
+ dc->caps.dmub_caps.mclk_sw =
dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;
}
if (dc->res_pool->pg_cntl) {
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 3bd9911b6f3a..66eff38b9e80 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -97,6 +97,9 @@
/* Maximum number of planes on any ASIC. */
#define DMUB_MAX_PLANES 6
+/* Maximum number of phantom planes on any ASIC */
+#define DMUB_MAX_PHANTOM_PLANES (DMUB_MAX_PLANES) / 2
+
/* Trace buffer offset for entry */
#define TRACE_BUFFER_ENTRY_OFFSET 16
@@ -466,7 +469,7 @@ struct dmub_feature_caps {
* Max PSR version supported by FW.
*/
uint8_t psr;
- uint8_t fw_assisted_mclk_switch;
+ uint8_t fw_assisted_mclk_switch_ver;
uint8_t reserved[4];
uint8_t subvp_psr_support;
uint8_t gecc_enable;
@@ -4667,6 +4670,7 @@ union dmub_rb_cmd {
* Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
*/
struct dmub_rb_cmd_assr_enable assr_enable;
+
};
/**
--
2.34.1
[PATCH 05/43] drm/amd/display: Toggle additional RCO options in DCN35
From: Daniel Miess
[Why]
With root clock optimization now enabled for DCN35 there
are still RCO registers still not being toggled
[How]
Add in logic to toggle RCO registers for DPPCLK,
DPSTREAMCLK and DSCCLK
Reviewed-by: Charlene Liu
Acked-by: Roman Li
Signed-off-by: Daniel Miess
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c | 207 +-
.../drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h | 3 +-
.../drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c | 69 +-
.../drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h | 9 +-
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 28 +++
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 2 +
.../amd/display/dc/hwss/dcn35/dcn35_init.c| 1 +
.../display/dc/hwss/hw_sequencer_private.h| 4 +
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 4 +
10 files changed, 314 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 6300ae2ea1f7..29fd8daa9d15 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -695,6 +695,7 @@ enum pg_hw_pipe_resources {
PG_MPCC,
PG_OPP,
PG_OPTC,
+ PG_DPSTREAM,
PG_HW_PIPE_RESOURCES_NUM_ELEMENT
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
index f1ba7bb792ea..58dd3c5bbff0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
@@ -49,15 +49,23 @@ static void dcn35_set_dppclk_enable(struct dccg *dccg,
switch (dpp_inst) {
case 0:
REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, enable);
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL6,
DPPCLK0_ROOT_GATE_DISABLE, enable);
break;
case 1:
REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, enable);
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL6,
DPPCLK1_ROOT_GATE_DISABLE, enable);
break;
case 2:
REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, enable);
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL6,
DPPCLK2_ROOT_GATE_DISABLE, enable);
break;
case 3:
REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, enable);
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL6,
DPPCLK3_ROOT_GATE_DISABLE, enable);
break;
default:
break;
@@ -100,6 +108,32 @@ static void dccg35_update_dpp_dto(struct dccg *dccg, int
dpp_inst,
dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
}
+static void dccg35_set_dppclk_root_clock_gating(struct dccg *dccg,
+uint32_t dpp_inst, uint32_t enable)
+{
+ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+ if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
+ return;
+
+ switch (dpp_inst) {
+ case 0:
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE,
enable);
+ break;
+ case 1:
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE,
enable);
+ break;
+ case 2:
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE,
enable);
+ break;
+ case 3:
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE,
enable);
+ break;
+ default:
+ break;
+ }
+}
+
static void dccg35_get_pixel_rate_div(
struct dccg *dccg,
uint32_t otg_inst,
@@ -333,21 +367,67 @@ static void dccg35_set_dpstreamclk(
/* enabled to select one of the DTBCLKs for pipe */
switch (dp_hpo_inst) {
case 0:
- REG_UPDATE_2(DPSTREAMCLK_CNTL,
- DPSTREAMCLK0_EN,
+ REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN,
(src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL,
otg_inst);
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
DPSTREAMCLK0_ROOT_GATE_DISABLE, (src == REFCLK) ? 0 : 1);
break;
case 1:
REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,
(src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL,
otg_inst);
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
DPSTREAMCLK1_ROOT_GATE_DISABLE, (src == REFCLK) ? 0 : 1);
break;
case
[PATCH 12/43] drm/amd/display: Enable DTBCLK DTO earlier in the sequence
From: Sung Joon Kim
[why]
As per programming guide, we need to
enable the virtual pixel clock via DTBCLK
DTO and ungate the clock before we begin
programming OPP/OPTC control registers.
Otherwise, the double-buffered registers
will be left pending until the clocks are enabled.
[how]
Move the DTBCLK DTO programming up to
where we do the legacy DP DTO programming.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Sung Joon Kim
Tested-by: Daniel Wheeler
---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 32 +--
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index f983041ce9a4..87b43cb50c1e 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -873,6 +873,22 @@ enum dc_status dcn20_enable_stream_timing(
return DC_ERROR_UNEXPECTED;
}
+ if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
+ struct dccg *dccg = dc->res_pool->dccg;
+ struct timing_generator *tg = pipe_ctx->stream_res.tg;
+ struct dtbclk_dto_params dto_params = {0};
+
+ if (dccg->funcs->set_dtbclk_p_src)
+ dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst);
+
+ dto_params.otg_inst = tg->inst;
+ dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz
/ 10;
+ dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);
+ dto_params.timing = _ctx->stream->timing;
+ dto_params.ref_dtbclk_khz =
dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
+ dccg->funcs->set_dtbclk_dto(dccg, _params);
+ }
+
if (dc_is_hdmi_tmds_signal(stream->signal)) {
stream->link->phy_state.symclk_ref_cnts.otg = 1;
if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
@@ -959,22 +975,6 @@ enum dc_status dcn20_enable_stream_timing(
pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
}
- if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
- struct dccg *dccg = dc->res_pool->dccg;
- struct timing_generator *tg = pipe_ctx->stream_res.tg;
- struct dtbclk_dto_params dto_params = {0};
-
- if (dccg->funcs->set_dtbclk_p_src)
- dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst);
-
- dto_params.otg_inst = tg->inst;
- dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz
/ 10;
- dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);
- dto_params.timing = _ctx->stream->timing;
- dto_params.ref_dtbclk_khz =
dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
- dccg->funcs->set_dtbclk_dto(dccg, _params);
- }
-
return DC_OK;
}
--
2.34.1
[PATCH 07/43] drm/amd/display: Expand supported Replay residency mode
From: Leon Huang
[Why]
Dmub provides several Replay residency calculation methods,
but current interface only supports either ALPM or PHY mode
[How]
Modify the interface for supporting different types
of Replay residency calculation.
Reviewed-by: Robin Chen
Acked-by: Roman Li
Signed-off-by: Leon Huang
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/inc/link.h | 2 +-
.../amd/display/dc/link/protocols/link_edp_panel_control.c | 7 +--
.../amd/display/dc/link/protocols/link_edp_panel_control.h | 2 +-
3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link.h
b/drivers/gpu/drm/amd/display/dc/inc/link.h
index bf29fc58ea6a..7ab8ba5e23ed 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link.h
@@ -288,7 +288,7 @@ struct link_service {
struct dc_link *link, uint32_t coasting_vtotal);
bool (*edp_replay_residency)(const struct dc_link *link,
unsigned int *residency, const bool is_start,
- const bool is_alpm);
+ const enum pr_residency_mode mode);
bool (*edp_set_replay_power_opt_and_coasting_vtotal)(struct dc_link
*link,
const unsigned int *power_opts, uint32_t
coasting_vtotal);
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 0682dbbad448..689c5fb44e86 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -1056,7 +1056,7 @@ bool edp_set_coasting_vtotal(struct dc_link *link,
uint32_t coasting_vtotal)
}
bool edp_replay_residency(const struct dc_link *link,
- unsigned int *residency, const bool is_start, const bool is_alpm)
+ unsigned int *residency, const bool is_start, const enum
pr_residency_mode mode)
{
struct dc *dc = link->ctx->dc;
struct dmub_replay *replay = dc->res_pool->replay;
@@ -1065,8 +1065,11 @@ bool edp_replay_residency(const struct dc_link *link,
if (!dc_get_edp_link_panel_inst(dc, link, _inst))
return false;
+ if (!residency)
+ return false;
+
if (replay != NULL && link->replay_settings.replay_feature_enabled)
- replay->funcs->replay_residency(replay, panel_inst, residency,
is_start, is_alpm);
+ replay->funcs->replay_residency(replay, panel_inst, residency,
is_start, mode);
else
*residency = 0;
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
index eee8a4db6f85..cb6d95cc36e4 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
@@ -61,7 +61,7 @@ bool edp_send_replay_cmd(struct dc_link *link,
union dmub_replay_cmd_set *cmd_data);
bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal);
bool edp_replay_residency(const struct dc_link *link,
- unsigned int *residency, const bool is_start, const bool is_alpm);
+ unsigned int *residency, const bool is_start, const enum
pr_residency_mode mode);
bool edp_get_replay_state(const struct dc_link *link, uint64_t *state);
bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,
const unsigned int *power_opts, uint32_t coasting_vtotal);
--
2.34.1
[PATCH 06/43] drm/amd/display: Decouple dcn35 and dcn351 dmub firmware
From: Roman Li [Why] dcn351 dmub fw was decoupled from dcn35. [How] Add dcn351 dmub fw load path. Reviewed-by: Rodrigo Siqueira Acked-by: Roman Li Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ef546932f6c9..d98632f37c0d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -148,6 +148,9 @@ MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin" MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB); +#define FIRMWARE_DCN_351_DMUB "amdgpu/dcn_3_5_1_dmcub.bin" +MODULE_FIRMWARE(FIRMWARE_DCN_351_DMUB); + /* Number of bytes in PSP header for firmware. */ #define PSP_HEADER_BYTES 0x100 @@ -4820,9 +4823,11 @@ static int dm_init_microcode(struct amdgpu_device *adev) fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; break; case IP_VERSION(3, 5, 0): - case IP_VERSION(3, 5, 1): fw_name_dmub = FIRMWARE_DCN_35_DMUB; break; + case IP_VERSION(3, 5, 1): + fw_name_dmub = FIRMWARE_DCN_351_DMUB; + break; default: /* ASIC doesn't support DMUB. */ return 0; -- 2.34.1
[PATCH 09/43] drm/amd/display: handle invalid connector indices
From: Joshua Aberback
[Why]
The function to count the number of valid connectors does not
guarantee that the first n indices are valid, only that there
exist n valid indices. When invalid indices are present, this
results in later valid connectors being missed, as processing
would end after checking n indices.
[How]
- count valid indices separately from total indices examined
- add explicit definition of MAX_LINKS
Reviewed-by: Dillon Varone
Acked-by: Roman Li
Signed-off-by: Joshua Aberback
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 1 +
.../gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c | 4 ++--
8 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 5ee87965a078..bb4f3bd7532e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -503,7 +503,7 @@ static void dcn2_notify_link_rate_change(struct clk_mgr
*clk_mgr_base, struct dc
clk_mgr->cur_phyclk_req_table[link->link_index] =
link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
- for (i = 0; i < MAX_PIPES * 2; i++) {
+ for (i = 0; i < MAX_LINKS; i++) {
if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index e3e1940198a9..f65bb4c21b7d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -548,7 +548,7 @@ static void rn_notify_link_rate_change(struct clk_mgr
*clk_mgr_base, struct dc_l
clk_mgr->cur_phyclk_req_table[link->link_index] =
link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
- for (i = 0; i < MAX_PIPES * 2; i++) {
+ for (i = 0; i < MAX_LINKS; i++) {
if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index 3271c8c7905d..4cb0db0ed92f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -474,7 +474,7 @@ static void dcn30_notify_link_rate_change(struct clk_mgr
*clk_mgr_base, struct d
clk_mgr->cur_phyclk_req_table[link->link_index] =
link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
- for (i = 0; i < MAX_PIPES * 2; i++) {
+ for (i = 0; i < MAX_LINKS; i++) {
if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 667655d0e5b9..c3510cdd0ec8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -212,7 +212,8 @@ static bool create_links(
connectors_num,
num_virtual_links);
- for (i = 0; i < connectors_num; i++) {
+ // condition loop on link_count to allow skipping invalid indices
+ for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) {
struct link_init_data link_init_params = {0};
struct dc_link *link;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 29fd8daa9d15..3ed41cf6a59d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1327,7 +1327,7 @@ struct dc {
struct dc_phy_addr_space_config vm_pa_config;
uint8_t link_count;
- struct dc_link *links[MAX_PIPES * 2];
+ struct dc_link *links[MAX_LINKS];
struct link_service *link_srv;
struct dc_state *current_state;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index f4d4a68c91dc..4ba18ea57aad 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -349,7 +349,7 @@ struct clk_mgr_internal {
enum
[PATCH 03/43] drm/amd/display: fix underflow in some two display subvp/non-subvp configs
From: Samson Tam
[Why]
In two display configuration, switching between subvp and non-subvp
may cause underflow because it moves an existing pipe between
displays
[How]
Create helper function for applying pipe split flags
Apply pipe split flags prior to deciding on subvp
During subvp check, do not merge pipes, so it can retain previous
pipe configuration
Add check for prev odm pipe in subvp check
For single display subvp case, use same odm policy for phantom pipes
as main subvp pipe
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Samson Tam
Tested-by: Daniel Wheeler
---
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 259 ++
.../dc/resource/dcn32/dcn32_resource.c| 70 -
2 files changed, 199 insertions(+), 130 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index a0a65e099104..8c0e1ab29aa9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -180,6 +180,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
.urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
};
+static bool dcn32_apply_merge_split_flags_helper(struct dc *dc, struct
dc_state *context,
+ bool *repopulate_pipes, int *split, bool *merge);
+
void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
{
/* defaults */
@@ -622,7 +625,7 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,
* to combine this with SubVP can cause issues with the
scheduling).
* - Not TMZ surface
*/
- if (pipe->plane_state && !pipe->top_pipe &&
!dcn32_is_center_timing(pipe) &&
+ if (pipe->plane_state && !pipe->top_pipe &&
!pipe->prev_odm_pipe && !dcn32_is_center_timing(pipe) &&
!(pipe->stream->timing.pix_clk_100hz / 1 >
DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) &&
(!dcn32_is_psr_capable(pipe) ||
(context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) &&
dc_state_get_pipe_subvp_type(context, pipe) ==
SUBVP_NONE &&
@@ -1425,13 +1428,14 @@ static bool is_test_pattern_enabled(
return false;
}
-static void dcn32_full_validate_bw_helper(struct dc *dc,
+static bool dcn32_full_validate_bw_helper(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int *vlevel,
int *split,
bool *merge,
- int *pipe_cnt)
+ int *pipe_cnt,
+ bool *repopulate_pipes)
{
struct vba_vars_st *vba = >bw_ctx.dml.vba;
unsigned int dc_pipe_idx = 0;
@@ -1461,6 +1465,12 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
vba->VoltageLevel = *vlevel;
}
+ /* Apply split and merge flags before checking for subvp */
+ if (!dcn32_apply_merge_split_flags_helper(dc, context,
repopulate_pipes, split, merge))
+ return false;
+ memset(split, 0, MAX_PIPES * sizeof(int));
+ memset(merge, 0, MAX_PIPES * sizeof(bool));
+
/* Conditions for setting up phantom pipes for SubVP:
* 1. Not force disable SubVP
* 2. Full update (i.e. !fast_validate)
@@ -1475,19 +1485,7 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] ==
dm_dram_clock_change_unsupported ||
dc->debug.force_subvp_mclk_switch)) {
- dcn32_merge_pipes_for_subvp(dc, context);
- memset(merge, 0, MAX_PIPES * sizeof(bool));
-
vlevel_temp = *vlevel;
- /* to re-initialize viewport after the pipe merge */
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe_ctx =
>res_ctx.pipe_ctx[i];
-
- if (!pipe_ctx->plane_state || !pipe_ctx->stream)
- continue;
-
- resource_build_scaling_params(pipe_ctx);
- }
while (!found_supported_config &&
dcn32_enough_pipes_for_subvp(dc, context) &&
dcn32_assign_subvp_pipe(dc, context, _pipe_idx)) {
@@ -1576,8 +1574,6 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
* add phantom pipes. If pipe split (ODM / MPC) is
required, both the main
* and phantom pipes will be split in the regular pipe
splitting sequence.
*/
- memset(split, 0, MAX_PIPES * sizeof(int));
- memset(merge, 0, MAX_PIPES * sizeof(bool));
*vlevel =
[PATCH 01/43] drm/amd/display: Fix compiler redefinition warnings for certain configs
From: Mounika Adhuri
[why & how]
Modified definitions of 1 function and 2 structs to remove warnings on
certain specific compiler configurations due to redefinition.
Reviewed-by: Martin Leung
Acked-by: Roman Li
Signed-off-by: Mounika Adhuri
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 4 ++--
drivers/gpu/drm/amd/display/include/grph_object_id.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 35c631c22934..17b404cb1155 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -249,7 +249,7 @@ static bool dce110_enable_display_power_gating(
return false;
}
-static void build_prescale_params(struct ipp_prescale_params *prescale_params,
+static void dce110_prescale_params(struct ipp_prescale_params *prescale_params,
const struct dc_plane_state *plane_state)
{
prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
@@ -291,7 +291,7 @@ dce110_set_input_transfer_func(struct dc *dc, struct
pipe_ctx *pipe_ctx,
tf = _state->in_transfer_func;
- build_prescale_params(_params, plane_state);
+ dce110_prescale_params(_params, plane_state);
ipp->funcs->ipp_program_prescale(ipp, _params);
if (!plane_state->gamma_correction.is_identity &&
diff --git a/drivers/gpu/drm/amd/display/include/grph_object_id.h
b/drivers/gpu/drm/amd/display/include/grph_object_id.h
index c6bbd262f1ac..08ee0350b31f 100644
--- a/drivers/gpu/drm/amd/display/include/grph_object_id.h
+++ b/drivers/gpu/drm/amd/display/include/grph_object_id.h
@@ -226,8 +226,8 @@ enum dp_alt_mode {
struct graphics_object_id {
uint32_t id:8;
- uint32_t enum_id:4;
- uint32_t type:4;
+ enum object_enum_id enum_id;
+ enum object_type type;
uint32_t reserved:16; /* for padding. total size should be u32 */
};
--
2.34.1
[PATCH 04/43] drm/amd/display: optimize dml2 pipe resource allocation order
From: Wenjing Liu
[why]
There could be cases that we are transition from MPC to ODM combine.
In this case if we map pipes before unmapping MPC pipes, we might
temporarly run out of pipes. The change reorders pipe resource
allocation. So we unmapping pipes before mapping new pipes.
Reviewed-by: Dillon Varone
Acked-by: Roman Li
Signed-off-by: Wenjing Liu
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 2 +
.../display/dc/dml2/dml2_dc_resource_mgmt.c | 126 --
.../amd/display/dc/dml2/dml2_internal_types.h | 11 ++
.../drm/amd/display/dc/dml2/dml2_wrapper.h| 2 +
4 files changed, 97 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index dd0428024173..601af21b2df9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -5052,7 +5052,9 @@ void resource_init_common_dml2_callbacks(struct dc *dc,
struct dml2_configuratio
dml2_options->callbacks.update_pipes_for_stream_with_slice_count =
_update_pipes_for_stream_with_slice_count;
dml2_options->callbacks.update_pipes_for_plane_with_slice_count =
_update_pipes_for_plane_with_slice_count;
dml2_options->callbacks.get_mpc_slice_index =
_get_mpc_slice_index;
+ dml2_options->callbacks.get_mpc_slice_count =
_get_mpc_slice_count;
dml2_options->callbacks.get_odm_slice_index =
_get_odm_slice_index;
+ dml2_options->callbacks.get_odm_slice_count =
_get_odm_slice_count;
dml2_options->callbacks.get_opp_head = _get_opp_head;
dml2_options->callbacks.get_otg_master_for_stream =
_get_otg_master_for_stream;
dml2_options->callbacks.get_opp_heads_for_otg_master =
_get_opp_heads_for_otg_master;
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
index b64e0160d482..27d9da8ad7c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
@@ -793,7 +793,7 @@ static void map_pipes_for_plane(struct dml2_context *ctx,
struct dc_state *state
free_unused_pipes_for_plane(ctx, state, plane, >pipe_pool,
stream->stream_id, plane_index);
}
-static unsigned int get_mpc_factor(struct dml2_context *ctx,
+static unsigned int get_target_mpc_factor(struct dml2_context *ctx,
struct dc_state *state,
const struct dml_display_cfg_st *disp_cfg,
struct dml2_dml_to_dc_pipe_mapping *mapping,
@@ -822,7 +822,7 @@ static unsigned int get_mpc_factor(struct dml2_context *ctx,
return mpc_factor;
}
-static unsigned int get_odm_factor(
+static unsigned int get_target_odm_factor(
const struct dml2_context *ctx,
struct dc_state *state,
const struct dml_display_cfg_st *disp_cfg,
@@ -849,79 +849,117 @@ static unsigned int get_odm_factor(
return 1;
}
+static unsigned int get_source_odm_factor(const struct dml2_context *ctx,
+ struct dc_state *state,
+ const struct dc_stream_state *stream)
+{
+ struct pipe_ctx *otg_master =
ctx->config.callbacks.get_otg_master_for_stream(>res_ctx, stream);
+
+ return ctx->config.callbacks.get_odm_slice_count(otg_master);
+}
+
+static unsigned int get_source_mpc_factor(const struct dml2_context *ctx,
+ struct dc_state *state,
+ const struct dc_plane_state *plane)
+{
+ struct pipe_ctx *dpp_pipes[MAX_PIPES];
+ int dpp_pipe_count =
ctx->config.callbacks.get_dpp_pipes_for_plane(plane,
+ >res_ctx, dpp_pipes);
+
+ ASSERT(dpp_pipe_count > 0);
+ return ctx->config.callbacks.get_mpc_slice_count(dpp_pipes[0]);
+}
+
+
static void populate_mpc_factors_for_stream(
struct dml2_context *ctx,
const struct dml_display_cfg_st *disp_cfg,
struct dml2_dml_to_dc_pipe_mapping *mapping,
struct dc_state *state,
unsigned int stream_idx,
- unsigned int odm_factor,
- unsigned int mpc_factors[MAX_PIPES])
+ struct dml2_pipe_combine_factor odm_factor,
+ struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES])
{
const struct dc_stream_status *status =
>stream_status[stream_idx];
int i;
- for (i = 0; i < status->plane_count; i++)
- if (odm_factor == 1)
- mpc_factors[i] = get_mpc_factor(
- ctx, state, disp_cfg, mapping, status,
- state->streams[stream_idx], i);
- else
- mpc_factors[i] = 1;
+ for (i = 0; i < status->plane_count; i++) {
+ mpc_factors[i].source = get_source_mpc_factor(ctx, state,
[PATCH 02/43] drm/amd/display: Add timing pixel encoding for mst mode validation
From: Hersen Wu
[Why] Mode pbn is not calculated correctly because timing pixel encoding is
not checked within convert_dc_color_depth_into_bpc.
[How] Get mode kbps from dc_bandwidth_in_kbps_from_timing, then calculate
pbn by kbps_to_peak_pbn.
Reviewed-by: Wayne Lin
Acked-by: Roman Li
Signed-off-by: Hersen Wu
Tested-by: Daniel Wheeler
---
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 35 ---
1 file changed, 30 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 941e96f100f4..ad3170b72a47 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1601,7 +1601,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
struct amdgpu_dm_connector *aconnector,
struct dc_stream_state *stream)
{
- int bpp, pbn, branch_max_throughput_mps = 0;
+ int pbn, branch_max_throughput_mps = 0;
struct dc_link_settings cur_link_settings;
unsigned int end_to_end_bw_in_kbps = 0;
unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0;
@@ -1651,11 +1651,36 @@ enum dc_status dm_dp_mst_is_port_support_mode(
}
}
} else {
- /* check if mode could be supported within full_pbn */
- bpp =
convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
- pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10,
bpp << 4);
- if (pbn > aconnector->mst_output_port->full_pbn)
+ /* Check if mode could be supported within max slot
+* number of current mst link and full_pbn of mst links.
+*/
+ int pbn_div, slot_num, max_slot_num;
+ enum dc_link_encoding_format link_encoding;
+ uint16_t fec_overhead_multiplier_x1000 =
+ get_fec_overhead_multiplier(stream->link);
+ uint32_t stream_kbps =
+ dc_bandwidth_in_kbps_from_timing(>timing,
+
dc_link_get_highest_encoding_format(stream->link));
+
+ pbn = kbps_to_peak_pbn(stream_kbps,
fec_overhead_multiplier_x1000);
+ pbn_div = dm_mst_get_pbn_divider(stream->link);
+ slot_num = DIV_ROUND_UP(pbn, pbn_div);
+
+ link_encoding =
dc_link_get_highest_encoding_format(stream->link);
+ if (link_encoding == DC_LINK_ENCODING_DP_8b_10b)
+ max_slot_num = 63;
+ else if (link_encoding == DC_LINK_ENCODING_DP_128b_132b)
+ max_slot_num = 64;
+ else {
+ DRM_DEBUG_DRIVER("Invalid link encoding format\n");
return DC_FAIL_BANDWIDTH_VALIDATE;
+ }
+
+ if (slot_num > max_slot_num ||
+ pbn > aconnector->mst_output_port->full_pbn) {
+ DRM_DEBUG_DRIVER("Mode can not be supported within mst
links!");
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+ }
}
/* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
--
2.34.1
[PATCH 00/43] DC Patches Apr 1, 2024
From: Roman Li This DC patchset brings improvements in multiple areas. In summary, we have: - Fix underflow in subvp/non-subvp configs - Fix compiler warnings - Add handling for DC power mode - Add extra logging for DMUB, HUBP and OTG - Add timing pixel encoding for mst mode validation - Expand supported Replay residency mode - Allow HPO PG and RCG for DCN35 - Update pipe topology log to support subvp - Disable Z8 minimum stutter period check for DCN35 - Enable RCO for HDMISTREAMCLK in DCN35 Cc: Daniel Wheeler Alex Hung (1): drm/amd/display: Skip on writeback when it's not applicable Alvin Lee (2): drm/amd/display: Add extra logging for HUBP and OTG drm/amd/display: Add extra DMUB logging to track message timeout Aric Cyr (2): drm/amd/display: Fix compiler warnings on high compiler warning levels drm/amd/display: 3.2.279 Daniel Miess (2): drm/amd/display: Toggle additional RCO options in DCN35 drm/amd/display: Enable RCO for HDMISTREAMCLK in DCN35 Dillon Varone (1): drm/amd/display: Add dmub additional interface support for FAMS Duncan Ma (1): drm/amd/display: Allow HPO PG for DCN35 Eric Bernstein (1): drm/amd/display: Fix MPCC DTN logging George Shen (1): drm/amd/display: Add dummy interface for tracing DCN32 SMU messages Hersen Wu (2): drm/amd/display: Add timing pixel encoding for mst mode validation drm/amd/display: FEC overhead should be checked once for mst slot nums Joshua Aberback (3): drm/amd/display: handle invalid connector indices drm/amd/display: remove context->dml2 dependency from DML21 wrapper drm/amd/display: Add handling for DC power mode Leo (Hanghong) Ma (1): drm/amd/display: Add OTG check for set AV mute Leon Huang (1): drm/amd/display: Expand supported Replay residency mode Mounika Adhuri (1): drm/amd/display: Fix compiler redefinition warnings for certain configs Nicholas Kazlauskas (1): drm/amd/display: Disable Z8 minimum stutter period check for DCN35 Rodrigo Siqueira (15): drm/amd/display: Initialize DP ref clk with the correct clock drm/amd/display: Set alpha enable to 0 for some specific formats drm/amd/display: Enable cur_rom_en even if cursor degamma is not enabled drm/amd/display: Add some missing debug registers drm/amd/display: Update DSC compute parameter calculation drm/amd/display: Drop legacy code drm/amd/display: Add missing registers drm/amd/display: Remove redundant RESERVE0 and RESERVE1 drm/amd/display: Add missing SFB and OPP_SF drm/amd/display: Initialize debug variable data drm/amd/display: Add WBSCL ram coefficient for writeback drm/amd/display: Add code comments clock and encode code drm/amd/display: Includes adjustments drm/amd/display: Add color logs for dcn20 drm/amd/display: Enable FGCG for DCN351 Roman Li (2): drm/amd/display: Decouple dcn35 and dcn351 dmub firmware drm/amd/display: Allow RCG for Static Screen + LVP for DCN35 Samson Tam (1): drm/amd/display: fix underflow in some two display subvp/non-subvp configs Sung Joon Kim (1): drm/amd/display: Enable DTBCLK DTO earlier in the sequence Wenjing Liu (3): drm/amd/display: optimize dml2 pipe resource allocation order drm/amd/display: update pipe topology log to support subvp drm/amd/display: move build test pattern params as part of pipe resource update for odm Xi (Alex) Liu (1): drm/amd/display: add root clock control function pointer to fix display corruption .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 37 ++- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 66 +++-- .../display/amdgpu_dm/amdgpu_dm_mst_types.h | 3 - .../display/amdgpu_dm/amdgpu_dm_services.c| 8 + .../drm/amd/display/dc/bios/bios_parser2.c| 2 - .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 4 +- .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +- .../dc/clk_mgr/dcn201/dcn201_clk_mgr.c| 11 + .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 5 +- .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 2 +- .../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 5 +- .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c| 3 +- .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 3 +- .../dc/clk_mgr/dcn316/dcn316_clk_mgr.c| 3 +- .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c | 9 + drivers/gpu/drm/amd/display/dc/core/dc.c | 64 +++-- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 105 +-- .../gpu/drm/amd/display/dc/core/dc_state.c| 29 +- drivers/gpu/drm/amd/display/dc/dc.h | 19 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 12 +- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 13 +- drivers/gpu/drm/amd/display/dc/dc_state.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_stream.h| 8 - drivers/gpu/drm/amd/display/dc/dc_types.h | 16 ++ .../drm/amd/display/dc/dce/dce_mem_input.h| 1 + drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 1 +
[PATCH IP-REVIEW] drm/amd/display: Update dcn351 to latest dcn35 config
From: Sung Joon Kim
[why & how]
There were some fixes in dcn35 that need
to be ported over to dcn351 to prevent any
regression.
Signed-off-by: Sung Joon Kim
Reviewed-by: Liu, Xi (Alex)
---
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c| 9 ++---
drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c | 2 +-
.../gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c | 11 ---
3 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
index b624640..b3ffab7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
@@ -402,6 +402,8 @@ void dcn351_update_bw_bounding_box_fpu(struct dc *dc,
clock_limits[i].socclk_mhz;
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
clk_table->entries[i].memclk_mhz *
clk_table->entries[i].wck_ratio;
+
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
+ clock_limits[i].dtbclk_mhz;
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels
=
clk_table->num_entries;
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
@@ -414,6 +416,8 @@ void dcn351_update_bw_bounding_box_fpu(struct dc *dc,
clk_table->num_entries;
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels
=
clk_table->num_entries;
+
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels
=
+ clk_table->num_entries;
}
}
@@ -613,6 +617,7 @@ void dcn351_decide_zstate_support(struct dc *dc, struct
dc_state *context)
if (context->res_ctx.pipe_ctx[i].plane_state)
plane_count++;
}
+
/*dcn351 does not support z9/z10*/
if (context->stream_count == 0 || plane_count == 0) {
support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;
@@ -626,11 +631,9 @@ void dcn351_decide_zstate_support(struct dc *dc, struct
dc_state *context)
dc->debug.minimum_z8_residency_time > 0 ?
dc->debug.minimum_z8_residency_time : 1000;
bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod >
(double)minmum_z8_residency;
-
/*for psr1/psr-su, we allow z8 and z10 based on latency, for
replay with IPS enabled, it will enter ips2*/
-if (is_pwrseq0 && (is_psr || is_replay))
+ if (is_pwrseq0 && (is_psr || is_replay))
support = allow_z8 ? allow_z8 :
DCN_ZSTATE_SUPPORT_DISALLOW;
-
}
context->bw_ctx.bw.dcn.clk.zstate_support = support;
}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index ab17fa1..670255c 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -67,7 +67,7 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
.prepare_bandwidth = dcn35_prepare_bandwidth,
.optimize_bandwidth = dcn35_optimize_bandwidth,
.update_bandwidth = dcn20_update_bandwidth,
- .set_drr = dcn10_set_drr,
+ .set_drr = dcn35_set_drr,
.get_position = dcn10_get_position,
.set_static_screen_control = dcn35_set_static_screen_control,
.setup_stereo = dcn10_setup_stereo,
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index 2dfd73d..fe13c89 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -700,6 +700,8 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_dcc = DCC_ENABLE,
.disable_dpp_power_gate = true,
.disable_hubp_power_gate = true,
+ .disable_optc_power_gate = true, /*should the same as above two*/
+ .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
.disable_clock_gate = false,
.disable_dsc_power_gate = true,
.vsr_support = true,
@@ -742,12 +744,13 @@ static const struct dc_debug_options debug_defaults_drv =
{
},
.seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
.enable_z9_disable_interface = true, /* Allow support for the PMFW
interface for disable Z9*/
+ .minimum_z8_residency_time = 2100,
.using_dml2 = true,
.support_eDP1_5 = true,
.enable_hpo_pg_support
[PATCH 2/3] drm/amd: Add a DC debug mask for IPS
From: Roman Li
For debugging IPS-related issues, expose a new debug mask
that allows to disable IPS.
Usage:
amdgpu.dcdebugmask=0x800
Signed-off-by: Roman Li
Tested-by: Mark Broadworth
---
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index da9b670fec86..a89d93154ddb 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -259,6 +259,7 @@ enum DC_DEBUG_MASK {
DC_ENABLE_DML2 = 0x100,
DC_DISABLE_PSR_SU = 0x200,
DC_DISABLE_REPLAY = 0x400,
+ DC_DISABLE_IPS = 0x800,
};
enum amd_dpm_forced_level;
--
2.34.1
[PATCH 3/3] drm/amd/display: "Enable IPS by default"
From: Roman Li [Why] IPS was temporary disabled due to instability. It was fixed in dmub firmware and with: - "drm/amd/display: Add IPS checks before dcn register access" - "drm/amd/display: Disable ips before dc interrupt setting" [How] Enable IPS by default. Disable IPS if 0x800 bit set in amdgpu.dcdebugmask module params Signed-off-by: Roman Li Tested-by: Mark Broadworth --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 41994a60e2cd..9d909c09a14f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1719,7 +1719,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; - init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; +if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) + init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; init_data.flags.disable_ips_in_vpb = 1; -- 2.34.1
[PATCH 1/3] drm/amd/display: Disable ips before dc interrupt setting
From: Roman Li
[Why]
While in IPS2 an access to dcn registers is not allowed.
If interrupt results in dc call, we should disable IPS.
[How]
Safeguard register access in IPS2 by disabling idle optimization
before calling dc interrupt setting api.
Signed-off-by: Roman Li
Tested-by: Mark Broadworth
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 58b880acb087..3390f0d8420a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -711,7 +711,7 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
{
bool st;
enum dc_irq_source irq_source;
-
+ struct dc *dc = adev->dm.dc;
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
if (!acrtc) {
@@ -729,6 +729,9 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
st = (state == AMDGPU_IRQ_STATE_ENABLE);
+ if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
+ dc_allow_idle_optimizations(dc, false);
+
dc_interrupt_set(adev->dm.dc, irq_source, st);
return 0;
}
--
2.34.1
[PATCH 10/12] drm/amd/display: Replay + IPS + ABM in Full Screen VPB
From: ChunTao Tso
[Why]
Because ABM will wait VStart to start getting histogram data,
it will cause we can't enter IPS while full screnn video playing.
[How]
Modify the panel refresh rate to the maximun multiple of current
refresh rate.
Reviewed-by: Dennis Chan
Acked-by: Roman Li
Signed-off-by: ChunTao Tso
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 5 ++
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 46 +++
.../amd/display/modules/power/power_helpers.c | 5 ++
.../amd/display/modules/power/power_helpers.h | 1 +
4 files changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index b08ccb8c68bc..9900dda2eef5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -1034,6 +1034,7 @@ enum replay_FW_Message_type {
Replay_Msg_Not_Support = -1,
Replay_Set_Timing_Sync_Supported,
Replay_Set_Residency_Frameupdate_Timer,
+ Replay_Set_Pseudo_VTotal,
};
union replay_error_status {
@@ -1089,6 +1090,10 @@ struct replay_settings {
uint16_t coasting_vtotal_table[PR_COASTING_TYPE_NUM];
/* Maximum link off frame count */
enum replay_link_off_frame_count_level link_off_frame_count_level;
+ /* Replay pseudo vtotal for abm + ips on full screen video which can
improve ips residency */
+ uint16_t abm_with_ips_on_full_screen_video_pseudo_vtotal;
+ /* Replay last pseudo vtotal set to DMUB */
+ uint16_t last_pseudo_vtotal;
};
/* To split out "global" and "per-panel" config settings.
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index bcd3c361cca5..e699731ee68e 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -2895,6 +2895,10 @@ enum dmub_cmd_replay_type {
* Set Residency Frameupdate Timer.
*/
DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6,
+ /**
+* Set pseudo vtotal
+*/
+ DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7,
};
/**
@@ -3077,6 +3081,26 @@ struct dmub_cmd_replay_set_timing_sync_data {
uint8_t pad[2];
};
+/**
+ * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL
command.
+ */
+struct dmub_cmd_replay_set_pseudo_vtotal {
+ /**
+* Panel Instance.
+* Panel isntance to identify which replay_state to use
+* Currently the support is only for 0 or 1
+*/
+ uint8_t panel_inst;
+ /**
+* Source Vtotal that Replay + IPS + ABM full screen video src vtotal
+*/
+ uint16_t vtotal;
+ /**
+* Explicit padding to 4 byte boundary.
+*/
+ uint8_t pad;
+};
+
/**
* Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
*/
@@ -3157,6 +3181,20 @@ struct dmub_rb_cmd_replay_set_timing_sync {
struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data;
};
+/**
+ * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
+ */
+struct dmub_rb_cmd_replay_set_pseudo_vtotal {
+ /**
+* Command header.
+*/
+ struct dmub_cmd_header header;
+ /**
+* Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
+*/
+ struct dmub_cmd_replay_set_pseudo_vtotal data;
+};
+
/**
* Data passed from driver to FW in
DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
*/
@@ -3208,6 +3246,10 @@ union dmub_replay_cmd_set {
* Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER
command data.
*/
struct dmub_cmd_replay_frameupdate_timer_data timer_data;
+ /**
+* Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data.
+*/
+ struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data;
};
/**
@@ -4359,6 +4401,10 @@ union dmub_rb_cmd {
* Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER
command.
*/
struct dmub_rb_cmd_replay_set_frameupdate_timer
replay_set_frameupdate_timer;
+ /**
+* Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
+*/
+ struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal;
};
/**
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index ad98e504c00d..e304e8435fb8 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -980,6 +980,11 @@ void set_replay_coasting_vtotal(struct dc_link *link,
link->replay_settings.coasting_vtotal_table[type] = vtotal;
}
+void set_replay_ips_full_screen_video_src_vtotal(struct dc_link *link,
uint16_t vtotal)
+{
+ link->replay_settings.abm_with_ips_on_full_screen_video_pseudo_vtotal =
vtotal;
+}
+
void
[PATCH 09/12] drm/amd/display: turn off windowed Mpo ODM feature for dcn321
From: Wenjing Liu
[why]
It has been found a regression caused by enabling this feature during ODM to
MPC combine switch when user is resizing video window. The transition is
only needed when the feature is enabled. During the transition driver will
temporary switch to use max dppclk level through SMU set hard min interface.
The interface times out and fail to configure the max dpp clock level, which
caused
system issue as the desired clock can't be set. We will continue investigating
the issue and root cause the issue where max dppclk level can't be reached.
But for now we have to disable this feature as this feature will cause us to
hit this
problem in common use cases during video playback unfortunately. The issue
is dcn321 specific so it won't impact other dcn revisions.
Reviewed-by: Martin Leung
Acked-by: Roman Li
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
index 74412e5f03fe..6f832bf278cf 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
@@ -1760,6 +1760,7 @@ static bool dcn321_resource_construct(
dc->caps.color.mpc.ocsc = 1;
dc->config.dc_mode_clk_limit_support = true;
+ dc->config.enable_windowed_mpo_odm = false;
/* read VBIOS LTTPR caps */
{
if (ctx->dc_bios->funcs->get_lttpr_caps) {
--
2.34.1
[PATCH 03/12] drm/amd/display: Add usb4_bw_alloc_support flag
From: Peichen Huang
[Why]
dc should have a flag for DM to enable usb4_bw_alloc in dptx
[How]
- Add usb4_bw_alloc_support flag in dc_config
Reviewed-by: Wayne Lin
Reviewed-by: Meenakshikumar Somasundaram
Acked-by: Roman Li
Signed-off-by: Peichen Huang
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../drm/amd/display/dc/link/link_detection.c | 18 ++
.../gpu/drm/amd/display/dc/link/link_dpms.c | 58 +++
3 files changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 432ae08462e4..e338576f95a9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -435,6 +435,7 @@ struct dc_config {
bool enable_auto_dpm_test_logs;
unsigned int disable_ips;
unsigned int disable_ips_in_vpb;
+ bool usb4_bw_alloc_support;
};
enum visual_confirm {
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index 24153b0df503..b8c4a04dd175 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -41,6 +41,7 @@
#include "protocols/link_dp_dpia.h"
#include "protocols/link_dp_phy.h"
#include "protocols/link_dp_training.h"
+#include "protocols/link_dp_dpia_bw.h"
#include "accessories/link_dp_trace.h"
#include "link_enc_cfg.h"
@@ -991,6 +992,23 @@ static bool detect_link_and_local_sink(struct dc_link
*link,
if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
link->reported_link_cap.link_rate >
LINK_RATE_HIGH3)
link->reported_link_cap.link_rate =
LINK_RATE_HIGH3;
+
+ /*
+* If this is DP over USB4 link then we need to:
+* - Enable BW ALLOC support on DPtx if applicable
+*/
+ if (dc->config.usb4_bw_alloc_support) {
+ if
(link_dp_dpia_set_dptx_usb4_bw_alloc_support(link)) {
+ /* update with non reduced link cap if
bw allocation mode is supported */
+ if
(link->dpia_bw_alloc_config.nrd_max_link_rate &&
+
link->dpia_bw_alloc_config.nrd_max_lane_count) {
+
link->reported_link_cap.link_rate =
+
link->dpia_bw_alloc_config.nrd_max_link_rate;
+
link->reported_link_cap.lane_count =
+
link->dpia_bw_alloc_config.nrd_max_lane_count;
+ }
+ }
+ }
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 3cbfbf8d107e..a72de44a5747 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -2197,6 +2197,64 @@ static enum dc_status enable_link(
static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream,
int bw)
{
+ struct dc_link *link = stream->sink->link;
+ int req_bw = bw;
+
+ DC_LOGGER_INIT(link->ctx->logger);
+
+ if (!link->dpia_bw_alloc_config.bw_alloc_enabled)
+ return false;
+
+ if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+ int sink_index = 0;
+ int i = 0;
+
+ for (i = 0; i < link->sink_count; i++) {
+ if (link->remote_sinks[i] == NULL)
+ continue;
+
+ if (stream->sink->sink_id !=
link->remote_sinks[i]->sink_id)
+ req_bw +=
link->dpia_bw_alloc_config.remote_sink_req_bw[i];
+ else
+ sink_index = i;
+ }
+
+ link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw;
+ }
+
+ /* get dp overhead for dp tunneling */
+ link->dpia_bw_alloc_config.dp_overhead =
link_dp_dpia_get_dp_overhead_in_dp_tunneling(link);
+ req_bw += link->dpia_bw_alloc_config.dp_overhead;
+
+ if (link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw)) {
+ if (req_bw <= link->dpia_bw_alloc_config.allocated_bw) {
+ DC_LOG_DEBUG("%s, Success in allocate bw for link(%d),
allocated_bw(%d), dp_overhead(%d)\n",
+ __func__, link->link_index,
link->dpia_bw_alloc_config.allocated_bw,
+ link->dpia_bw_alloc_config.dp_overhead);
+ } else {
+ // Cannot get the required
[PATCH 08/12] drm/amd/display: Add GART memory support for dmcub
From: Fudongwang
[Why]
In dump file, GART memory can be accessed while frame buffer cannot.
[How]
Add GART memory support for dmcub.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Fudongwang
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 19 +++-
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 106 --
3 files changed, 71 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a9a57ba2b256..7905f5e2da05 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2120,6 +2120,16 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
const struct dmcub_firmware_header_v1_0 *hdr;
enum dmub_asic dmub_asic;
enum dmub_status status;
+ static enum dmub_window_memory_type
window_memory_type[DMUB_WINDOW_TOTAL] = {
+ DMUB_WINDOW_MEMORY_TYPE_FB,
//DMUB_WINDOW_0_INST_CONST
+ DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_1_STACK
+ DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_2_BSS_DATA
+ DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_3_VBIOS
+ DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_4_MAILBOX
+ DMUB_WINDOW_MEMORY_TYPE_FB,
//DMUB_WINDOW_5_TRACEBUFF
+ DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_6_FW_STATE
+ DMUB_WINDOW_MEMORY_TYPE_FB
//DMUB_WINDOW_7_SCRATCH_MEM
+ };
int r;
switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
@@ -2217,7 +2227,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
adev->dm.dmub_fw->data +
le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
PSP_HEADER_BYTES;
- region_params.is_mailbox_in_inbox = false;
+ region_params.window_memory_type = window_memory_type;
status = dmub_srv_calc_region_info(dmub_srv, _params,
_info);
@@ -2245,6 +2255,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr;
memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr;
memory_params.region_info = _info;
+ memory_params.window_memory_type = window_memory_type;
adev->dm.dmub_fb_info =
kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index c78c9224ab60..410420683f31 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -78,6 +78,16 @@ struct dmub_srv_dcn31_regs;
struct dmcub_trace_buf_entry;
+struct dmcub_inbox1_buf {
+ union dmub_rb_cmd cmd[DMUB_RB_MAX_ENTRY];
+};
+
+/* enum dmub_window_memory_type - memory location type specification for
windows */
+enum dmub_window_memory_type {
+ DMUB_WINDOW_MEMORY_TYPE_FB = 0,
+ DMUB_WINDOW_MEMORY_TYPE_GART
+};
+
/* enum dmub_status - return code for dmcub functions */
enum dmub_status {
DMUB_STATUS_OK = 0,
@@ -203,7 +213,7 @@ struct dmub_srv_region_params {
uint32_t vbios_size;
const uint8_t *fw_inst_const;
const uint8_t *fw_bss_data;
- bool is_mailbox_in_inbox;
+ const enum dmub_window_memory_type *window_memory_type;
};
/**
@@ -223,7 +233,7 @@ struct dmub_srv_region_params {
*/
struct dmub_srv_region_info {
uint32_t fb_size;
- uint32_t inbox_size;
+ uint32_t gart_size;
uint8_t num_regions;
struct dmub_region regions[DMUB_WINDOW_TOTAL];
};
@@ -239,9 +249,10 @@ struct dmub_srv_region_info {
struct dmub_srv_memory_params {
const struct dmub_srv_region_info *region_info;
void *cpu_fb_addr;
- void *cpu_inbox_addr;
+ void *cpu_gart_addr;
uint64_t gpu_fb_addr;
- uint64_t gpu_inbox_addr;
+ uint64_t gpu_gart_addr;
+ const enum dmub_window_memory_type *window_memory_type;
};
/**
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 9ad738805320..71eee58d86a1 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -417,58 +417,44 @@ void dmub_srv_destroy(struct dmub_srv *dmub)
dmub_memset(dmub, 0, sizeof(*dmub));
}
+static uint32_t dmub_srv_calc_regions_for_memory_type(const struct
dmub_srv_region_params *params,
+ struct dmub_srv_region_info *out,
+ const uint32_t *window_sizes,
+ enum dmub_window_memory_type memory_type)
+{
+ uint32_t i, top = 0;
+
+ for (i = 0; i < DMUB_WINDOW_TOTAL; ++i) {
+ if (params->window_memory_type[i] ==
[PATCH 12/12] drm/amd/display: Promote DAL to 3.2.269
From: Aric Cyr - FW Release 0.0.201.0 - Fix resizing video window for dcn321 - Fix timing bandwidth calculation for HDMI - Fix null-deref in dml2 assigned pipe search - Add GART memory support for dmcub - Add power_state and pme_pending flag - Add usb4_bw_alloc_support flag - Revert "Rework DC Z10 restore Acked-by: Roman Li Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index cb1899772426..8ef322b6c724 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -51,7 +51,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.268" +#define DC_VER "3.2.269" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.34.1
[PATCH 07/12] drm/amd/display: Revert "Rework DC Z10 restore"
From: Charlene Liu
This reverts commit 080a7e9d7dc5a18401d0569a36d55e133ed10cf8.
It caused intermittent hangs when enabling IPS on static screen.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +--
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 9 -
.../gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 ++
3 files changed, 7 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index af83ec23f3a0..aa7c02ba948e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1836,8 +1836,8 @@ static enum dc_status dc_commit_state_no_check(struct dc
*dc, struct dc_state *c
struct dc_state *old_state;
bool subvp_prev_use = false;
- dc_allow_idle_optimizations(dc, false);
dc_z10_restore(dc);
+ dc_allow_idle_optimizations(dc, false);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *old_pipe =
>current_state->res_ctx.pipe_ctx[i];
@@ -3376,9 +3376,6 @@ static void commit_planes_for_stream_fast(struct dc *dc,
int i, j;
struct pipe_ctx *top_pipe_to_program = NULL;
struct dc_stream_status *stream_status = NULL;
- if (dc->caps.ips_support)
- dc_allow_idle_optimizations(dc, false);
-
dc_z10_restore(dc);
top_pipe_to_program = resource_get_otg_master_for_stream(
@@ -3506,9 +3503,6 @@ static void commit_planes_for_stream(struct dc *dc,
// dc->current_state anymore, so we have to cache it before we apply
// the new SubVP context
subvp_prev_use = false;
- if (dc->caps.ips_support)
- dc_allow_idle_optimizations(dc, false);
-
dc_z10_restore(dc);
if (update_type == UPDATE_TYPE_FULL)
wait_for_outstanding_hw_updates(dc, context);
@@ -4692,9 +4686,6 @@ void dc_set_power_state(
case DC_ACPI_CM_POWER_STATE_D0:
dc_state_construct(dc, dc->current_state);
- if (dc->caps.ips_support)
- dc_allow_idle_optimizations(dc, false);
-
dc_z10_restore(dc);
dc->hwss.init_hw(dc);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 23f4f3c070cb..54670e0b1518 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -309,6 +309,7 @@ bool dc_stream_set_cursor_attributes(
stream->cursor_attributes = *attributes;
+ dc_z10_restore(dc);
/* disable idle optimizations while updating cursor */
if (dc->idle_optimizations_allowed) {
dc_allow_idle_optimizations(dc, false);
@@ -380,14 +381,12 @@ bool dc_stream_set_cursor_position(
}
dc = stream->ctx->dc;
+ dc_z10_restore(dc);
/* disable idle optimizations if enabling cursor */
- if (dc->idle_optimizations_allowed &&
- (!stream->cursor_position.enable ||
dc->debug.exit_idle_opt_for_cursor_updates ||
-dc->caps.ips_support) &&
- position->enable) {
+ if (dc->idle_optimizations_allowed && (!stream->cursor_position.enable
|| dc->debug.exit_idle_opt_for_cursor_updates)
+ && position->enable) {
dc_allow_idle_optimizations(dc, false);
- dc_z10_restore(dc);
reset_idle_optimizations = true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index da4f98de9b82..8b6c49622f3b 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -708,6 +708,8 @@ void dcn35_z10_restore(const struct dc *dc)
if (dc->debug.disable_z10)
return;
+ dc_dmub_srv_apply_idle_power_optimizations(dc, false);
+
dcn31_z10_restore(dc);
}
--
2.34.1
[PATCH 11/12] drm/amd/display: [FW Promotion] Release 0.0.201.0
From: Anthony Koo
- Add debug flag for Replay IPS visual confirm
- Remove unused debug flags that should not
be controlled inside Replay FSM
Acked-by: Roman Li
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index e699731ee68e..89717076933e 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -403,17 +403,12 @@ union replay_debug_flags {
/**
* 0x400 (bit 10)
-* @force_disable_ips1: Force disable IPS1 state
+* @enable_ips_visual_confirm: Enable IPS visual confirm when
entering IPS
+* If we enter IPS2, the Visual confirm bar will change to
yellow
*/
- uint32_t force_disable_ips1 : 1;
+ uint32_t enable_ips_visual_confirm : 1;
- /**
-* 0x800 (bit 11)
-* @force_disable_ips2: Force disable IPS2 state
-*/
- uint32_t force_disable_ips2 : 1;
-
- uint32_t reserved : 20;
+ uint32_t reserved : 21;
} bitfields;
uint32_t u32All;
--
2.34.1
[PATCH 02/12] drm/amd/display: Promote DAL to 3.2.268
From: Aric Cyr Acked-by: Roman Li Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 1d052742d4c7..432ae08462e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -51,7 +51,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.267" +#define DC_VER "3.2.268" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.34.1
[PATCH 04/12] drm/amd/display: Add NULL-checks in dml2 assigned pipe search
From: Allen Pan
[Why]
NULL-deref regression after:
"drm/amd/display: Fix dml2 assigned pipe search"
[How]
Add verification for potential NULLs
Fixes: 133e813d5044 ("drm/amd/display: Fix dml2 assigned pipe search")
Reviewed-by: Charlene Liu
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Gabe Teeger
Signed-off-by: Allen Pan
---
.../display/dc/dml2/dml2_dc_resource_mgmt.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
index a0ce681b26c6..a52c594e1ba4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
@@ -146,19 +146,24 @@ static unsigned int find_pipes_assigned_to_plane(struct
dml2_context *ctx,
for (i = 0; i < ctx->config.dcn_pipe_count; i++) {
struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
- if (!pipe->stream)
+ if (!pipe->plane_state || !pipe->stream)
continue;
get_plane_id(ctx, state, pipe->plane_state,
pipe->stream->stream_id,
ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[pipe->pipe_idx],
_id_assigned_to_pipe);
- if (pipe->plane_state && plane_id_assigned_to_pipe == plane_id
&& !pipe->top_pipe && !pipe->prev_odm_pipe) {
+ if (plane_id_assigned_to_pipe == plane_id &&
!pipe->prev_odm_pipe
+ && (!pipe->top_pipe ||
pipe->top_pipe->plane_state != pipe->plane_state)) {
while (pipe) {
- struct pipe_ctx *mpo_pipe = pipe;
-
- while (mpo_pipe) {
- pipes[num_found++] = mpo_pipe->pipe_idx;
- mpo_pipe = mpo_pipe->bottom_pipe;
+ struct pipe_ctx *mpc_pipe = pipe;
+
+ while (mpc_pipe) {
+ pipes[num_found++] = mpc_pipe->pipe_idx;
+ mpc_pipe = mpc_pipe->bottom_pipe;
+ if (!mpc_pipe)
+ break;
+ if (mpc_pipe->plane_state !=
pipe->plane_state)
+ mpc_pipe = NULL;
}
pipe = pipe->next_odm_pipe;
}
--
2.34.1
[PATCH 05/12] drm/amd/display: Add IPS checks before dcn register access
From: Roman Li
[Why]
With IPS enabled a system hangs once PSR is active.
PSR active triggers transition to IPS2 state.
While in IPS2 an access to dcn registers results in hard hang.
Existing check doesn't cover for PSR sequence.
[How]
Safeguard register access by disabling idle optimization in atomic commit
and crtc scanout. It will be re-enabled on next vblank.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Roman Li
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c| 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f9e41006ac87..a9a57ba2b256 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -272,6 +272,7 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device
*adev, int crtc,
{
u32 v_blank_start, v_blank_end, h_position, v_position;
struct amdgpu_crtc *acrtc = NULL;
+ struct dc *dc = adev->dm.dc;
if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
return -EINVAL;
@@ -284,6 +285,9 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device
*adev, int crtc,
return 0;
}
+ if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
+ dc_allow_idle_optimizations(dc, false);
+
/*
* TODO rework base driver to use values directly.
* for now parse it back into reg-format
@@ -9010,16 +9014,8 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
trace_amdgpu_dm_atomic_commit_tail_begin(state);
- if (dm->dc->caps.ips_support) {
- for_each_oldnew_connector_in_state(state, connector,
old_con_state, new_con_state, i) {
- if (new_con_state->crtc &&
- new_con_state->crtc->state->active &&
-
drm_atomic_crtc_needs_modeset(new_con_state->crtc->state)) {
-
dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
- break;
- }
- }
- }
+ if (dm->dc->caps.ips_support && dm->dc->idle_optimizations_allowed)
+ dc_allow_idle_optimizations(dm->dc, false);
drm_atomic_helper_update_legacy_modeset_state(dev, state);
drm_dp_mst_atomic_wait_for_dependencies(state);
--
2.34.1
[PATCH 06/12] drm/amd/display: add power_state and pme_pending flag
From: Muhammad Ahmed
[what]
Adding power_state to dc.h and pme_pending flag to clk_mgr_internal.h
Reviewed-by: Charlene Liu
Acked-by: Roman Li
Signed-off-by: Muhammad Ahmed
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index e338576f95a9..cb1899772426 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1069,6 +1069,7 @@ struct dc {
} scratch;
struct dml2_configuration_options dml2_options;
+ enum dc_acpi_cm_power_state power_state;
};
enum frame_buffer_mode {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index e668cc21cd28..f4d4a68c91dc 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -356,6 +356,7 @@ struct clk_mgr_internal {
long long wm_range_table_addr;
bool dpm_present;
+ bool pme_trigger_pending;
};
struct clk_mgr_internal_funcs {
--
2.34.1
[PATCH 01/12] drm/amd/display: Fix timing bandwidth calculation for HDMI
From: "Leo (Hanghong) Ma"
[Why && How]
The current bandwidth calculation for timing doesn't account for
certain HDMI modes overhead which leads to DSC can't be enabled.
Add support to calculate the actual bandwidth for these HDMI modes.
Reviewed-by: Chris Park
Acked-by: Roman Li
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 811474f4419b..fb4db3158e8f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -942,6 +942,7 @@ struct dc_crtc_timing {
uint32_t hdmi_vic;
uint32_t rid;
uint32_t fr_index;
+ uint32_t frl_uncompressed_video_bandwidth_in_kbps;
enum dc_timing_3d_format timing_3d_format;
enum dc_color_depth display_color_depth;
enum dc_pixel_encoding pixel_encoding;
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 0df6c55eb326..ac41f9c0a283 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -137,6 +137,11 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
if (link_encoding == DC_LINK_ENCODING_DP_128b_132b)
kbps = apply_128b_132b_stream_overhead(timing, kbps);
+ if (link_encoding == DC_LINK_ENCODING_HDMI_FRL &&
+ timing->vic == 0 && timing->hdmi_vic == 0 &&
+ timing->frl_uncompressed_video_bandwidth_in_kbps != 0)
+ kbps = timing->frl_uncompressed_video_bandwidth_in_kbps;
+
return kbps;
}
--
2.34.1
[PATCH 00/12] DC Patches January 18, 2024
From: Roman Li This DC patchset brings improvements in multiple areas. In summary, we highlight: * Add power_state/pme_pending flag/usb4_bw_alloc_support flags * Add GART memory support * Improvements for HDMI, IPS, DML2 and others Allen Pan (1): drm/amd/display: Add NULL-checks in dml2 assigned pipe search Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.201.0 Aric Cyr (2): drm/amd/display: Promote DAL to 3.2.268 drm/amd/display: Promote DAL to 3.2.269 Charlene Liu (1): drm/amd/display: Revert "Rework DC Z10 restore" ChunTao Tso (1): drm/amd/display: Replay + IPS + ABM in Full Screen VPB Fudongwang (1): drm/amd/display: Add GART memory support for dmcub Leo (Hanghong) Ma (1): drm/amd/display: Fix timing bandwidth calculation for HDMI Muhammad Ahmed (1): drm/amd/display: add power_state and pme_pending flag Peichen Huang (1): drm/amd/display: Add usb4_bw_alloc_support flag Roman Li (1): drm/amd/display: Add IPS checks before dcn register access Wenjing Liu (1): drm/amd/display: turn off windowed Mpo ODM feature for dcn321 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 +++-- drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +- .../gpu/drm/amd/display/dc/core/dc_stream.c | 9 +- drivers/gpu/drm/amd/display/dc/dc.h | 4 +- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 + drivers/gpu/drm/amd/display/dc/dc_types.h | 5 + .../display/dc/dml2/dml2_dc_resource_mgmt.c | 19 ++-- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 5 + .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 + .../amd/display/dc/inc/hw/clk_mgr_internal.h | 1 + .../drm/amd/display/dc/link/link_detection.c | 18 +++ .../gpu/drm/amd/display/dc/link/link_dpms.c | 58 ++ .../dc/resource/dcn321/dcn321_resource.c | 1 + drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 19 +++- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 59 -- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 106 -- .../amd/display/modules/power/power_helpers.c | 5 + .../amd/display/modules/power/power_helpers.h | 1 + 18 files changed, 244 insertions(+), 109 deletions(-) -- 2.34.1
[PATCH] drm/amd/display: Disable IPS by default
From: Roman Li [Why] Instability is observed on DCN35 if idle power optimization is enabled. [How] Disable IPS until issue is resolved. Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2845c884398e..2cabe1b463bc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1710,6 +1710,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; + init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; + /* Enable DWB for tested platforms only */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) init_data.num_virtual_links = 1; -- 2.17.1
[PATCH v2 23/24] drm/amd/display: Read before writing Backlight Mode Set Register
From: Iswara Nagulendran
[HOW]
Reading the value from
DP_EDP_BACKLIGHT_MODE_SET_REGISTER, DPCD 0x721
before setting the
BP_EDP_PANEL_LUMINANC_CONTROL_ENABLE bit
to ensure there are no accidental overwrites.
Reviewed-by: Sreeja Golui
Reviewed-by: Harry Vanzylldejong
Acked-by: Roman Li
Signed-off-by: Iswara Nagulendran
---
.../amd/display/dc/link/protocols/link_edp_panel_control.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 86f97ddcc595..e32a7974a4bc 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -182,7 +182,7 @@ bool edp_set_backlight_level_nits(struct dc_link *link,
_control, 1) != DC_OK)
return false;
} else {
- const uint8_t backlight_enable =
DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE;
+ uint8_t backlight_enable = 0;
struct target_luminance_value *target_luminance = NULL;
//if target luminance value is greater than 24 bits, clip the
value to 24 bits
@@ -191,6 +191,11 @@ bool edp_set_backlight_level_nits(struct dc_link *link,
target_luminance = (struct target_luminance_value
*)_millinits;
+ core_link_read_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+ _enable, sizeof(uint8_t));
+
+ backlight_enable |= DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE;
+
if (core_link_write_dpcd(link,
DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
_enable,
sizeof(backlight_enable)) != DC_OK)
--
2.34.1
[PATCH v2 20/24] drm/amd/display: Fix shaper using bad LUT params
From: Ilya Bakoulin
[Why]
LUT params are not cleared after setting blend TF, which can lead to
same params being used for the shaper, if the shaper func is bypassed.
[How]
Set lut_params to NULL after program_1dlut.
Reviewed-by: Krunoslav Kovac
Acked-by: Roman Li
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index e837554b8a28..1b9f21fd4f17 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -494,6 +494,7 @@ bool dcn32_set_mcm_luts(
}
}
result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
+ lut_params = NULL;
// Shaper
if (plane_state->in_shaper_func) {
--
2.34.1
[PATCH v2 22/24] drm/amd/display: Disable SYMCLK32_SE RCO on DCN314
From: Michael Strauss
[WHY]
Currently causes some DP link layer failures, backing out until
the failures are root caused.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 2d7436f2ea82..48bd56ca729b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -916,7 +916,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.hdmistream = true,
.hdmichar = true,
.dpstream = true,
- .symclk32_se = true,
+ .symclk32_se = false,
.symclk32_le = true,
.symclk_fe = true,
.physymclk = true,
--
2.34.1
[PATCH v2 19/24] drm/amd/display: add null check for invalid opps
From: Samson Tam
[Why]
In cases where number of pipes available is less
than num_opp, there will opp instances that are
null
[How]
Add null check to skip over these opp instances
Fixes: 9e241124fe13 ("drm/amd/display: Update OPP counter from new interface")
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c4962cc4bb93..52e8528aedbe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3574,7 +3574,8 @@ static void wait_for_outstanding_hw_updates(struct dc
*dc, const struct dc_state
mpcc_inst = hubp->inst;
// MPCC inst is equal to pipe index in practice
for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
- if
(dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
+ if ((dc->res_pool->opps[opp_inst] != NULL) &&
+
(dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) {
dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
break;
--
2.34.1
[PATCH v2 17/24] drm/amd/display: fix num_ways overflow error
From: Samson Tam
[Why]
Helper function calculates num_ways using 32-bit. But is
returned as 8-bit. If num_ways exceeds 8-bit, then it
reports back the incorrect num_ways and erroneously
uses MALL when it should not
[How]
Make returned value 32-bit and convert after it checks
against caps.cache_num_ways, which is under 8-bit
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 68dc99034eba..2173d84e4953 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -217,7 +217,7 @@ static bool dcn32_check_no_memory_request_for_cab(struct dc
*dc)
static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state
*ctx)
{
int i;
- uint8_t num_ways = 0;
+ uint32_t num_ways = 0;
uint32_t mall_ss_size_bytes = 0;
mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes;
@@ -247,7 +247,8 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc
*dc, struct dc_state *c
bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
{
union dmub_rb_cmd cmd;
- uint8_t ways, i;
+ uint8_t i;
+ uint32_t ways;
int j;
bool mall_ss_unsupported = false;
struct dc_plane_state *plane = NULL;
@@ -307,7 +308,7 @@ bool dcn32_apply_idle_power_optimizations(struct dc *dc,
bool enable)
cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
cmd.cab.header.sub_type =
DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
cmd.cab.header.payload_bytes = sizeof(cmd.cab)
- sizeof(cmd.cab.header);
- cmd.cab.cab_alloc_ways = ways;
+ cmd.cab.cab_alloc_ways = (uint8_t)ways;
dm_execute_dmub_cmd(dc->ctx, ,
DM_DMUB_WAIT_TYPE_NO_WAIT);
--
2.34.1
[PATCH v2 24/24] drm/amd/display: add interface to query SubVP status
From: Aurabindo Pillai
[Why]
To enable automated testing through IGT, expose an API that is
accessible through debugfs to query current status of SubVP feature.
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 3 ++-
4 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 1259d6351c50..13a177d34376 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -3645,7 +3645,9 @@ static int capabilities_show(struct seq_file *m, void
*unused)
struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
struct dc *dc = adev->dm.dc;
bool mall_supported = dc->caps.mall_size_total;
+ bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;
unsigned int mall_in_use = false;
+ unsigned int subvp_in_use = dc->cap_funcs.get_subvp_en(dc,
dc->current_state);
struct hubbub *hubbub = dc->res_pool->hubbub;
if (hubbub->funcs->get_mall_en)
@@ -3653,6 +3655,8 @@ static int capabilities_show(struct seq_file *m, void
*unused)
seq_printf(m, "mall supported: %s, enabled: %s\n",
mall_supported ? "yes" : "no", mall_in_use ? "yes" :
"no");
+ seq_printf(m, "sub-viewport supported: %s, enabled: %s\n",
+ subvp_supported ? "yes" : "no", subvp_in_use ? "yes"
: "no");
return 0;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index aa4684be1d62..e6e6377a8ce3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -382,6 +382,7 @@ struct dc_cap_funcs {
bool (*get_dcc_compression_cap)(const struct dc *dc,
const struct dc_dcc_surface_param *input,
struct dc_surface_dcc_cap *output);
+ bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
};
struct link_training_settings;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 0e1d395a9340..89b072447dba 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1993,7 +1993,8 @@ int dcn32_populate_dml_pipes_from_context(
}
static struct dc_cap_funcs cap_funcs = {
- .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+ .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
+ .get_subvp_en = dcn32_subvp_in_use,
};
void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 9f6186be7cd8..be953cf8103d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1570,7 +1570,8 @@ static void dcn321_destroy_resource_pool(struct
resource_pool **pool)
}
static struct dc_cap_funcs cap_funcs = {
- .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+ .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
+ .get_subvp_en = dcn32_subvp_in_use,
};
static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params
*bw_params)
--
2.34.1
[PATCH v2 21/24] drm/amd/display: 3.2.256
From: Aric Cyr DC v3.2.256 Summary: * Fixes null-deref regression after "drm/amd/display: Update OPP counter from new interface" * Fixes display flashing when VSR and HDR enabled on dcn32 * Fixes dcn3x intermittent hangs due to FPO * Fixes MST Multi-Stream light up on dcn35 * Fixes green screen on DCN31x when DVI and HDMI monitors attached * Adds DML2 improvements * Adds idle power optimization improvements * Accommodates panels with lower nit backlight * Updates SDP VSC colorimetry from DP test automation request * Reverts "drm/amd/display: allow edp updates for virtual signal" Acked-by: Roman Li Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 47b767fb1ee8..aa4684be1d62 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -49,7 +49,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.255" +#define DC_VER "3.2.256" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.34.1
[PATCH v2 18/24] drm/amd/display: Update FAMS sequence for DCN30 & DCN32
From: Alvin Lee
Provide DCN32 specific sequence and update DCN30 sequence
Reviewed-by: Samson Tam
Acked-by: Roman Li
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 2 +-
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 21 ++---
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 31 +++
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 3 ++
4 files changed, 38 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
index 90f061edb64c..427cfc8c24a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
@@ -60,7 +60,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
.pipe_control_lock = dcn20_pipe_control_lock,
.interdependent_update_lock = dcn10_lock_all_pipes,
.cursor_lock = dcn10_cursor_lock,
- .prepare_bandwidth = dcn30_prepare_bandwidth,
+ .prepare_bandwidth = dcn32_prepare_bandwidth,
.optimize_bandwidth = dcn20_optimize_bandwidth,
.update_bandwidth = dcn20_update_bandwidth,
.set_drr = dcn10_set_drr,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 9247a8ed5570..fd8a8c10a201 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -997,11 +997,7 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
void dcn30_prepare_bandwidth(struct dc *dc,
struct dc_state *context)
{
- bool p_state_change_support =
context->bw_ctx.bw.dcn.clk.p_state_change_support;
- /* Any transition into an FPO config should disable MCLK switching
first to avoid
-* driver and FW P-State synchronization issues.
-*/
- if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||
dc->clk_mgr->clks.fw_based_mclk_switching) {
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching &&
!dc->clk_mgr->clks.fw_based_mclk_switching) {
dc->optimized_required = true;
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
}
@@ -1012,20 +1008,9 @@ void dcn30_prepare_bandwidth(struct dc *dc,
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr,
dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries
- 1].memclk_mhz);
dcn20_prepare_bandwidth(dc, context);
- /*
-* enabled -> enabled: do not disable
-* enabled -> disabled: disable
-* disabled -> enabled: don't care
-* disabled -> disabled: don't care
-*/
- if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
- dc_dmub_srv_p_state_delegate(dc, false, context);
- if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||
dc->clk_mgr->clks.fw_based_mclk_switching) {
- /* After disabling P-State, restore the original value to
ensure we get the correct P-State
-* on the next optimize. */
- context->bw_ctx.bw.dcn.clk.p_state_change_support =
p_state_change_support;
- }
+ if (!dc->clk_mgr->clks.fw_based_mclk_switching)
+ dc_dmub_srv_p_state_delegate(dc, false, context);
}
void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 2173d84e4953..e837554b8a28 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -50,6 +50,7 @@
#include "dce/dmub_hw_lock_mgr.h"
#include "dcn32/dcn32_resource.h"
#include "link.h"
+#include "../dcn20/dcn20_hwseq.h"
#define DC_LOGGER_INIT(logger)
@@ -1677,3 +1678,33 @@ bool dcn32_is_pipe_topology_transition_seamless(struct
dc *dc,
return is_seamless;
}
+
+void dcn32_prepare_bandwidth(struct dc *dc,
+ struct dc_state *context)
+{
+ bool p_state_change_support =
context->bw_ctx.bw.dcn.clk.p_state_change_support;
+ /* Any transition into an FPO config should disable MCLK switching
first to avoid
+* driver and FW P-State synchronization issues.
+*/
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||
dc->clk_mgr->clks.fw_based_mclk_switching) {
+ dc->optimized_required = true;
+ context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
+ }
+
+ if (dc->clk_mgr->dc_mode_softmax_enabled)
+ if (dc->clk_mgr->clks.dramclk_khz <=
dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
+ context->bw_ctx.bw.dcn.clk.dramclk_khz >
dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
+ dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr,
[PATCH v2 16/24] drm/amd/display: Add prefix for plane functions
From: Rodrigo Siqueira
This commit adds the amdgpu_dm_plane_ prefix for all functions in the
amdgpu_dm_plane.c. This change enables an easy way to filter code paths
via ftrace.
Reviewed-by: Aurabindo Pillai
Acked-by: Roman Li
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 542 +-
.../amd/display/amdgpu_dm/amdgpu_dm_plane.h | 2 +-
3 files changed, 275 insertions(+), 271 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 23088ddac649..cc0c819506cf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -10144,7 +10144,7 @@ static int dm_update_plane_state(struct dc *dc,
/* Block top most plane from being a video plane */
if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
- if
(is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
+ if
(amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) &&
*is_top_most_overlay)
return -EINVAL;
*is_top_most_overlay = false;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 03df26bd8e83..116121e647ca 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -139,7 +139,7 @@ void amdgpu_dm_plane_fill_blending_from_plane_state(const
struct drm_plane_state
}
}
-static void add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap,
uint64_t mod)
+static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size,
uint64_t *cap, uint64_t mod)
{
if (!*mods)
return;
@@ -164,12 +164,12 @@ static void add_modifier(uint64_t **mods, uint64_t *size,
uint64_t *cap, uint64_
*size += 1;
}
-static bool modifier_has_dcc(uint64_t modifier)
+static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier)
{
return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
}
-static unsigned int modifier_gfx9_swizzle_mode(uint64_t modifier)
+static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t
modifier)
{
if (modifier == DRM_FORMAT_MOD_LINEAR)
return 0;
@@ -177,8 +177,8 @@ static unsigned int modifier_gfx9_swizzle_mode(uint64_t
modifier)
return AMD_FMT_MOD_GET(TILE, modifier);
}
-static void fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
-uint64_t tiling_flags)
+static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union
dc_tiling_info *tiling_info,
+uint64_t
tiling_flags)
{
/* Fill GFX8 params */
if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) ==
DC_ARRAY_2D_TILED_THIN1) {
@@ -209,8 +209,8 @@ static void fill_gfx8_tiling_info_from_flags(union
dc_tiling_info *tiling_info,
AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
}
-static void fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
- union dc_tiling_info *tiling_info)
+static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct
amdgpu_device *adev,
+ union
dc_tiling_info *tiling_info)
{
/* Fill GFX9 params */
tiling_info->gfx9.num_pipes =
@@ -230,9 +230,9 @@ static void fill_gfx9_tiling_info_from_device(const struct
amdgpu_device *adev,
tiling_info->gfx9.num_pkrs =
adev->gfx.config.gb_addr_config_fields.num_pkrs;
}
-static void fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device
*adev,
- union dc_tiling_info *tiling_info,
- uint64_t modifier)
+static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct
amdgpu_device *adev,
+ union
dc_tiling_info *tiling_info,
+ uint64_t
modifier)
{
unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS,
modifier);
unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS,
modifier);
@@ -241,7 +241,7 @@ static void fill_gfx9_tiling_info_from_modifier(const
struct amdgpu_device *adev
pipes_log2 = min(5u, mod_pipe_xor_bits);
- fill_gfx9_tiling_info_from_device(adev, tiling_info);
+ amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info);
if (!IS_AMD_FMT_MOD(modifier))
return;
@@ -258,13 +258,13 @@ static void fill_gfx9_tiling_info_from_modifier(const
[PATCH v2 15/24] drm/amd/display: Add prefix to amdgpu crtc functions
From: Rodrigo Siqueira
The ftrace debug feature allows filtering functions based on a prefix,
which can be helpful in some complex debug scenarios. The driver can
benefit more from this feature if the function name follows some
patterns; for this reason, this commit adds the prefix amdgpu_dm_crtc_
to all the functions that do not have it in the amdgpu_dm_crtc.c file.
Reviewed-by: Aurabindo Pillai
Acked-by: Roman Li
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 48 +--
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 440fc0869a34..611849e3bf91 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -95,7 +95,7 @@ bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state)
dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
}
-static void vblank_control_worker(struct work_struct *work)
+static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
{
struct vblank_control_work *vblank_work =
container_of(work, struct vblank_control_work, work);
@@ -144,7 +144,7 @@ static void vblank_control_worker(struct work_struct *work)
kfree(vblank_work);
}
-static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
+static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
{
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
@@ -184,7 +184,7 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool
enable)
if (!work)
return -ENOMEM;
- INIT_WORK(>work, vblank_control_worker);
+ INIT_WORK(>work, amdgpu_dm_crtc_vblank_control_worker);
work->dm = dm;
work->acrtc = acrtc;
work->enable = enable;
@@ -202,15 +202,15 @@ static inline int dm_set_vblank(struct drm_crtc *crtc,
bool enable)
int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
{
- return dm_set_vblank(crtc, true);
+ return amdgpu_dm_crtc_set_vblank(crtc, true);
}
void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
{
- dm_set_vblank(crtc, false);
+ amdgpu_dm_crtc_set_vblank(crtc, false);
}
-static void dm_crtc_destroy_state(struct drm_crtc *crtc,
+static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
struct dm_crtc_state *cur = to_dm_crtc_state(state);
@@ -226,7 +226,7 @@ static void dm_crtc_destroy_state(struct drm_crtc *crtc,
kfree(state);
}
-static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc)
+static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc
*crtc)
{
struct dm_crtc_state *state, *cur;
@@ -266,12 +266,12 @@ static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
kfree(crtc);
}
-static void dm_crtc_reset_state(struct drm_crtc *crtc)
+static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc)
{
struct dm_crtc_state *state;
if (crtc->state)
- dm_crtc_destroy_state(crtc, crtc->state);
+ amdgpu_dm_crtc_destroy_state(crtc, crtc->state);
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (WARN_ON(!state))
@@ -291,12 +291,12 @@ static int amdgpu_dm_crtc_late_register(struct drm_crtc
*crtc)
/* Implemented only the options currently available for the driver */
static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
- .reset = dm_crtc_reset_state,
+ .reset = amdgpu_dm_crtc_reset_state,
.destroy = amdgpu_dm_crtc_destroy,
.set_config = drm_atomic_helper_set_config,
.page_flip = drm_atomic_helper_page_flip,
- .atomic_duplicate_state = dm_crtc_duplicate_state,
- .atomic_destroy_state = dm_crtc_destroy_state,
+ .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state,
+ .atomic_destroy_state = amdgpu_dm_crtc_destroy_state,
.set_crc_source = amdgpu_dm_crtc_set_crc_source,
.verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
.get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
@@ -309,11 +309,11 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs =
{
#endif
};
-static void dm_crtc_helper_disable(struct drm_crtc *crtc)
+static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc)
{
}
-static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
+static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state
*new_crtc_state)
{
struct drm_atomic_state *state = new_crtc_state->state;
struct drm_plane *plane;
@@ -345,8 +345,8 @@ static int count_crtc_active_planes(struct drm_crtc_state
[PATCH v2 14/24] drm/amd/display: Correct enum typo
From: Rodrigo Siqueira
This commit just replaces dc_interrupt_po*r*larity with its correct
name, which is dc_interrupt_polarity.
Reviewed-by: Aurabindo Pillai
Acked-by: Roman Li
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/irq_types.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h
b/drivers/gpu/drm/amd/display/dc/irq_types.h
index 530c2578db40..93354bff456a 100644
--- a/drivers/gpu/drm/amd/display/dc/irq_types.h
+++ b/drivers/gpu/drm/amd/display/dc/irq_types.h
@@ -178,7 +178,7 @@ enum dc_interrupt_context {
INTERRUPT_CONTEXT_NUMBER
};
-enum dc_interrupt_porlarity {
+enum dc_interrupt_polarity {
INTERRUPT_POLARITY_DEFAULT = 0,
INTERRUPT_POLARITY_LOW = INTERRUPT_POLARITY_DEFAULT,
INTERRUPT_POLARITY_HIGH,
@@ -199,12 +199,12 @@ struct dc_interrupt_params {
/* The polarity *change* which will trigger an interrupt.
* If 'requested_polarity == INTERRUPT_POLARITY_BOTH', then
* 'current_polarity' must be initialised. */
- enum dc_interrupt_porlarity requested_polarity;
+ enum dc_interrupt_polarity requested_polarity;
/* If 'requested_polarity == INTERRUPT_POLARITY_BOTH',
* 'current_polarity' should contain the current state, which means
* the interrupt will be triggered when state changes from what is,
* in 'current_polarity'. */
- enum dc_interrupt_porlarity current_polarity;
+ enum dc_interrupt_polarity current_polarity;
enum dc_irq_source irq_source;
enum dc_interrupt_context int_context;
};
--
2.34.1
[PATCH v2 11/24] drm/amd/display: Fix HDMI framepack 3D test issue
From: Sung Joon Kim
[why]
Bandwidth validation failure on framepack tests.
Need to double pixel clock when 3D format is
framepack. Also for HDMI displays, we need to
keep the ITC flag to 1 by default.
[how]
Double the pixel clock when using framepack 3D format.
Set hdmi ITC bit to 1.
Reviewed-by: Charlene Liu
Acked-by: Roman Li
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 97f402123fbb..f0e437f8ea3f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -4228,7 +4228,7 @@ static void set_avi_info_frame(
switch (stream->content_type) {
case DISPLAY_CONTENT_TYPE_NO_DATA:
hdmi_info.bits.CN0_CN1 = 0;
- hdmi_info.bits.ITC = 0;
+ hdmi_info.bits.ITC = 1;
break;
case DISPLAY_CONTENT_TYPE_GRAPHICS:
hdmi_info.bits.CN0_CN1 = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index e5ccd2887c94..adf835279d6b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -569,6 +569,8 @@ static void
populate_dml_timing_cfg_from_stream_state(struct dml_timing_cfg_st *
out->RefreshRate[location] = ((in->timing.pix_clk_100hz * 100) /
in->timing.h_total) / in->timing.v_total;
out->VFrontPorch[location] = in->timing.v_front_porch;
out->PixelClock[location] = in->timing.pix_clk_100hz / 1.00;
+ if (in->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
+ out->PixelClock[location] *= 2;
out->HTotal[location] = in->timing.h_total;
out->VTotal[location] = in->timing.v_total;
out->Interlace[location] = in->timing.flags.INTERLACE;
--
2.34.1
[PATCH v2 13/24] drm/amd/display: Set emulated sink type to HDMI accordingly.
From: Alex Hung [WHY & HOW] Virtual sink is not audio-capable and this causes kms_hdmi_inject's inject-audio to fail. Set it to HDMI according to EDID. Reviewed-by: Chao-kai Wang Acked-by: Roman Li Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 02eca0856eca..23088ddac649 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6593,6 +6593,9 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) return; } + if (drm_detect_hdmi_monitor(edid)) + init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; + aconnector->edid = edid; aconnector->dc_em_sink = dc_link_add_remote_sink( -- 2.34.1
