[PATCH 21/21] drm/amd/display: Ignore First MST Sideband Message Return Error
From: Fangzhi Zuo
[why]
First MST sideband message returns AUX_RET_ERROR_HPD_DISCON
on certain intel platform. Aux transaction considered failure
if HPD unexpected pulled low. The actual aux transaction success
in such case, hence do not return error.
[how]
Not returning error when AUX_RET_ERROR_HPD_DISCON detected
on the first sideband message.
Cc: sta...@vger.kernel.org # 4.18+
Signed-off-by: Fangzhi Zuo
Acked-by: Solomon Chiu
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 27 +++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 8 ++
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 17
3 files changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 476fe60f4b7d..e203d75834de 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -72,6 +72,7 @@
#include
#include
#include
+#include
#include
#include
@@ -1400,6 +1401,29 @@ static bool dm_should_disable_stutter(struct pci_dev
*pdev)
return false;
}
+static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
+ {
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+ DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
+ },
+ },
+ {}
+};
+
+void retrieve_dmi_info(struct amdgpu_display_manager *dm)
+{
+ const struct dmi_system_id *dmi_id;
+
+ dm->aux_hpd_discon_quirk = false;
+
+ dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
+ if (dmi_id) {
+ dm->aux_hpd_discon_quirk = true;
+ DRM_INFO("aux_hpd_discon_quirk attached\n");
+ }
+}
+
static int amdgpu_dm_init(struct amdgpu_device *adev)
{
struct dc_init_data init_data;
@@ -1531,6 +1555,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
INIT_LIST_HEAD(>dm.da_list);
+
+ retrieve_dmi_info(>dm);
+
/* Display Core create. */
adev->dm.dc = dc_create(_data);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index e04e6b3f609f..33d66d4897dc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -547,6 +547,14 @@ struct amdgpu_display_manager {
* last successfully applied backlight values.
*/
u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP];
+
+ /**
+* @aux_hpd_discon_quirk:
+*
+* quirk for hpd discon while aux is on-going.
+* occurred on certain intel platform
+*/
+ bool aux_hpd_discon_quirk;
};
enum dsc_clock_force_state {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 8237029cedf5..168d5676b657 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -56,6 +56,8 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
ssize_t result = 0;
struct aux_payload payload;
enum aux_return_code_type operation_result;
+ struct amdgpu_device *adev;
+ struct ddc_service *ddc;
if (WARN_ON(msg->size > 16))
return -E2BIG;
@@ -74,6 +76,21 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, ,
_result);
+ /*
+* w/a on certain intel platform where hpd is unexpected to pull low
during
+* 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
+* aux transaction is succuess in such case, therefore bypass the error
+*/
+ ddc = TO_DM_AUX(aux)->ddc_service;
+ adev = ddc->ctx->driver_context;
+ if (adev->dm.aux_hpd_discon_quirk) {
+ if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &&
+ operation_result == AUX_RET_ERROR_HPD_DISCON) {
+ result = 0;
+ operation_result = AUX_RET_SUCCESS;
+ }
+ }
+
if (payload.write && result >= 0)
result = msg->size;
--
2.25.1
[PATCH 20/21] drm/amd/display: 3.2.194
From: Aric Cyr This version brings along following fixes: - Fixes for MST, MPO, PSRSU, DP 2.0, Freesync and others - Add register offsets of NBI and DCN. - Improvement of ALPM - Removing assert statement for Linux DM - Re-implementing ARGB16161616 pixel format Acked-by: Solomon Chiu Signed-off-by: Aric Cyr Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 89a3cc8f9274..7c42377f0aae 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.193" +#define DC_VER "3.2.194" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.25.1
[PATCH 19/21] drm/amd/display: Fix wrong reference
From: Rodrigo Siqueira
We recently introduced a commit that caused a compilation warning
because we tried to print a struct as an unsigned int. This commit
address this issue by adding the missing field.
Fixes: "drm/amd/display: add system info table log"
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index c2a5ab3e5f2f..09fbb7ad5362 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -2079,7 +2079,7 @@ static enum bp_result bios_parser_get_encoder_cap_info(
record = get_encoder_cap_record(bp, object);
if (!record)
return BP_RESULT_NORECORD;
- DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x",
record->encodercaps, object_id);
+ DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x",
record->encodercaps, object_id.id);
info->DP_HBR2_CAP = (record->encodercaps &
ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
@@ -2961,10 +2961,10 @@ static enum bp_result construct_integrated_info(
i,
info->ext_disp_conn_info.path[i].device_tag,
info->ext_disp_conn_info.path[i].device_acpi_enum,
-
info->ext_disp_conn_info.path[i].device_connector_id,
+
info->ext_disp_conn_info.path[i].device_connector_id.id,
info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index,
info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index,
-
info->ext_disp_conn_info.path[i].ext_encoder_obj_id,
+
info->ext_disp_conn_info.path[i].ext_encoder_obj_id.id,
info->ext_disp_conn_info.path[i].caps
);
}
--
2.25.1
[PATCH 18/21] drm/amd/display: Fix lag when moving windowed MPO across display using ODM 2:1 combine
From: Samson Tam
[Why]
With single display odm 2:1 policy, when moving windowed MPO across
the display, we experience a momentary lag when we move between the
centre of the display and the right half of the display. This is
caused by the MPO pipe being reallocated when it crosses this
boundary
[How]
Handle two cases:
1. if the head pipe has a MPO pipe already allocated in the old
context, then use that pipe if it is available in the current
context
2. if the head pipe is on the left side, check the right side to
see if it has a MPO pipe already allocated. If so, don't use
that pipe if it is selected as the idle pipe in the current
context
Add new function pointer called .acquire_idle_pipe_for_head_pipe
that will pass in the head pipe and handle case 1
Add find_idle_secondary_pipe_check_mpo() to handle case 2
if we don't hit case 1.
In dc_add_plane_to_context(), start with head pipe and check
case 1 and 2 in call acquire_free_pipe_for_head().
If we are on the right side of the display, check case 1
again by passing in right side pipe as the new head in
call acquire_free_pipe_for_head().
Reviewed-by: Dmytro Laktyushkin
Reviewed-by: Ariel Bernstein
Acked-by: Solomon Chiu
Signed-off-by: Samson Tam
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 32 +--
.../gpu/drm/amd/display/dc/inc/core_types.h | 27
2 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 9db50ed5460b..2a701c583332 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1397,8 +1397,12 @@ static struct pipe_ctx *acquire_free_pipe_for_head(
* to acquire an idle one to satisfy the request
*/
- if (!pool->funcs->acquire_idle_pipe_for_layer)
- return NULL;
+ if (!pool->funcs->acquire_idle_pipe_for_layer) {
+ if (!pool->funcs->acquire_idle_pipe_for_head_pipe_in_layer)
+ return NULL;
+ else
+ return
pool->funcs->acquire_idle_pipe_for_head_pipe_in_layer(context, pool,
head_pipe->stream, head_pipe);
+ }
return pool->funcs->acquire_idle_pipe_for_layer(context, pool,
head_pipe->stream);
}
@@ -1448,6 +1452,8 @@ bool dc_add_plane_to_context(
struct resource_pool *pool = dc->res_pool;
struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
struct dc_stream_status *stream_status = NULL;
+ struct pipe_ctx *prev_right_head = NULL;
+ struct pipe_ctx *free_right_pipe = NULL;
DC_LOGGER_INIT(stream->ctx->logger);
for (i = 0; i < context->stream_count; i++)
@@ -1507,6 +1513,28 @@ bool dc_add_plane_to_context(
free_pipe->pipe_idx,
tail_pipe->next_odm_pipe ?
tail_pipe->next_odm_pipe->pipe_idx : -1);
+ /*
+* We want to avoid the case where the right
side already has a pipe assigned to
+* it and is different from free_pipe ( which
would cause trigger a pipe
+* reallocation ).
+* Check the old context to see if the right
side already has a pipe allocated
+* - If not, continue to use free_pipe
+* - If the right side already has a pipe, use
that pipe instead if its available
+*/
+ prev_right_head =
>current_state->res_ctx.pipe_ctx[tail_pipe->next_odm_pipe->pipe_idx];
+ if ((prev_right_head->bottom_pipe) &&
(free_pipe->pipe_idx != prev_right_head->bottom_pipe->pipe_idx)) {
+ free_right_pipe =
acquire_free_pipe_for_head(context, pool, tail_pipe->next_odm_pipe);
+ if (free_right_pipe) {
+ free_pipe->stream = NULL;
+ memset(_pipe->stream_res,
0, sizeof(struct stream_resource));
+ memset(_pipe->plane_res,
0, sizeof(struct plane_resource));
+ free_pipe->plane_state = NULL;
+ free_pipe->pipe_idx = 0;
+ free_right_pipe->plane_state =
plane_state;
+ free_pipe = free_right_pipe;
+ }
+ }
+
free_pipe-
[PATCH 17/21] drm/amd/display: Add NBIO reg offsets to DC
From: Aurabindo Pillai
[Why]
Add a field to store the NBIO IP offset for use with runtime offset
calculation
Reviewed-by: Rodrigo Siqueira
Acked-by: Solomon Chiu
Signed-off-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
4 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 78ba2762fe9d..476fe60f4b7d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1528,6 +1528,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
init_data.flags.enable_mipi_converter_optimization = true;
init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
+ init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
INIT_LIST_HEAD(>dm.da_list);
/* Display Core create. */
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 6039b3487d4f..7453ec54420b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -863,6 +863,7 @@ static bool dc_construct_ctx(struct dc *dc,
dc_ctx->dc_stream_id_count = 0;
dc_ctx->dce_environment = init_params->dce_environment;
dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets;
+ dc_ctx->nbio_reg_offsets = init_params->nbio_reg_offsets;
/* Create logger */
@@ -1243,6 +1244,7 @@ struct dc *dc_create(const struct dc_init_data
*init_params)
}
dc->dcn_reg_offsets = init_params->dcn_reg_offsets;
+ dc->nbio_reg_offsets = init_params->nbio_reg_offsets;
/* Populate versioning information */
dc->versions.dc_ver = DC_VER;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index faa22580852b..89a3cc8f9274 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -810,6 +810,7 @@ struct dc {
struct vm_helper *vm_helper;
uint32_t *dcn_reg_offsets;
+ uint32_t *nbio_reg_offsets;
};
enum frame_buffer_mode {
@@ -857,6 +858,7 @@ struct dc_init_data {
* before them.
*/
uint32_t *dcn_reg_offsets;
+ uint32_t *nbio_reg_offsets;
};
struct dc_callback_init {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 077a93e81561..ad9041472cca 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -877,6 +877,7 @@ struct dc_context {
struct cp_psp cp_psp;
#endif
uint32_t *dcn_reg_offsets;
+ uint32_t *nbio_reg_offsets;
};
/* DSC DPCD capabilities */
--
2.25.1
[PATCH 16/21] drm/amd/display: Add DCN reg offsets to DC
From: Harry Wentland
[Why]
Add a field to store the DCN IP offset for use with runtime offset
calculation
This offset is indexed using reg*_BASE_IDX for the corresponding
group of registers. For example, address of DIG_BE_CNTL instance 0 is
calculated like: dcn_reg_offsets[regDIG0_DIG_BE_CNTL_BASE_IDX] +
regDIG0_DIG_BE_CNTL.
{dcn,nbio}_reg_offsets are used only for the ASICs for which runtime
initializaion of offsets are enabled through the modified SR* macros
that contain an additional REG_STRUCT element in the macro definition.
DCN3.5+ will fail dc_create() if {dcn,nbio}_reg_offsets are null. They
are applicable starting with DCN32/321 and are not used for ASICs
upstreamed before them. ASICs before DCN32/321 will not contain any
computation that involves {dcn,nbio}_reg_offsets. For them, the
address/offset computation is done during compile time.
This is evident from the BASE_INNER definition for compile time vs run
time initialization:
Compile time init: #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
Run time init: #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
BASE_INNER macro is local to each dcnxx_resource.c and hence different
ASICs can have either runtime or compile time initialization of offsets.
The computation of offset is done for registers all at once during
driver load and hence it does not introduce any performance overhead
during normal operation.
Reviewed-by: Rodrigo Siqueira
Acked-by: Solomon Chiu
Signed-off-by: Harry Wentland
Signed-off-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
drivers/gpu/drm/amd/display/dc/dc.h | 10 ++
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +-
4 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 000d34a7b6b4..78ba2762fe9d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1527,6 +1527,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
init_data.flags.enable_mipi_converter_optimization = true;
+ init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
+
INIT_LIST_HEAD(>dm.da_list);
/* Display Core create. */
adev->dm.dc = dc_create(_data);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 03bf4be81ea3..6039b3487d4f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -862,6 +862,7 @@ static bool dc_construct_ctx(struct dc *dc,
dc_ctx->dc_sink_id_count = 0;
dc_ctx->dc_stream_id_count = 0;
dc_ctx->dce_environment = init_params->dce_environment;
+ dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets;
/* Create logger */
@@ -1241,6 +1242,8 @@ struct dc *dc_create(const struct dc_init_data
*init_params)
dc->versions.dmcu_version =
dc->res_pool->dmcu->dmcu_version;
}
+ dc->dcn_reg_offsets = init_params->dcn_reg_offsets;
+
/* Populate versioning information */
dc->versions.dc_ver = DC_VER;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 1dca016b5782..faa22580852b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -808,6 +808,8 @@ struct dc {
const char *build_id;
struct vm_helper *vm_helper;
+
+ uint32_t *dcn_reg_offsets;
};
enum frame_buffer_mode {
@@ -847,6 +849,14 @@ struct dc_init_data {
struct dpcd_vendor_signature vendor_signature;
bool force_smu_not_present;
+ /*
+* IP offset for run time initializaion of register addresses
+*
+* DCN3.5+ will fail dc_create() if these fields are null for them.
They are
+* applicable starting with DCN32/321 and are not used for ASICs
upstreamed
+* before them.
+*/
+ uint32_t *dcn_reg_offsets;
};
struct dc_callback_init {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 7e595310a4b8..077a93e81561 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -876,7 +876,7 @@ struct dc_context {
#ifdef CONFIG_DRM_AMD_DC_HDCP
struct cp_psp cp_psp;
#endif
-
+ uint32_t *dcn_reg_offsets;
};
/* DSC DPCD capabilities */
--
2.25.1
[PATCH 15/21] drm/amd/display: add system info table log
From: Charlene Liu
[why]
insert log for debug use.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
Signed-off-by: Charlene Liu
Tested-by: Daniel Wheeler
---
.../drm/amd/display/dc/bios/bios_parser2.c| 30 +++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 6f514d92b401..c2a5ab3e5f2f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -2079,6 +2079,7 @@ static enum bp_result bios_parser_get_encoder_cap_info(
record = get_encoder_cap_record(bp, object);
if (!record)
return BP_RESULT_NORECORD;
+ DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x",
record->encodercaps, object_id);
info->DP_HBR2_CAP = (record->encodercaps &
ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
@@ -2098,6 +2099,7 @@ static enum bp_result bios_parser_get_encoder_cap_info(
ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0;
info->DP_IS_USB_C = (record->encodercaps &
ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
+ DC_LOG_BIOS("\t info->DP_IS_USB_C %d", info->DP_IS_USB_C);
return BP_RESULT_OK;
}
@@ -2944,7 +2946,35 @@ static enum bp_result construct_integrated_info(
if (result != BP_RESULT_OK)
return result;
+ else {
+ // Log each external path
+ for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
+ if (info->ext_disp_conn_info.path[i].device_tag != 0)
+ DC_LOG_BIOS("integrated_info:For EXTERNAL
DISPLAY PATH %d --\n"
+ "DEVICE_TAG: 0x%x\n"
+ "DEVICE_ACPI_ENUM: 0x%x\n"
+ "DEVICE_CONNECTOR_ID: 0x%x\n"
+ "EXT_AUX_DDC_LUT_INDEX: %d\n"
+ "EXT_HPD_PIN_LUT_INDEX: %d\n"
+ "EXT_ENCODER_OBJ_ID: 0x%x\n"
+ "Encoder CAPS: 0x%x\n",
+ i,
+
info->ext_disp_conn_info.path[i].device_tag,
+
info->ext_disp_conn_info.path[i].device_acpi_enum,
+
info->ext_disp_conn_info.path[i].device_connector_id,
+
info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index,
+
info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index,
+
info->ext_disp_conn_info.path[i].ext_encoder_obj_id,
+
info->ext_disp_conn_info.path[i].caps
+ );
+ }
+ // Log the Checksum and Voltage Swing
+ DC_LOG_BIOS("Integrated info table CHECKSUM: %d\n"
+ "Integrated info table
FIX_DP_VOLTAGE_SWING: %d\n",
+ info->ext_disp_conn_info.checksum,
+
info->ext_disp_conn_info.fixdpvoltageswing);
+ }
/* Sort voltage table from low to high*/
for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
for (j = i; j > 0; --j) {
--
2.25.1
[PATCH 14/21] drm/amd/display: Grab dc_lock before detecting link
From: Wayne Lin
[Why & How]
There is chance we change dc state while calling dc_link_detect().
As the result of that, grab the dm.dc_lock before detecting link.
Reviewed-by: Hersen Wu
Acked-by: Solomon Chiu
Signed-off-by: Wayne Lin
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 85 ---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 11 ++-
2 files changed, 63 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index de1c139ae279..000d34a7b6b4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2716,10 +2716,13 @@ static int dm_resume(void *handle)
if (!dc_link_detect_sink(aconnector->dc_link,
_connection_type))
DRM_ERROR("KMS: Failed to detect connector\n");
- if (aconnector->base.force && new_connection_type ==
dc_connection_none)
+ if (aconnector->base.force && new_connection_type ==
dc_connection_none) {
emulated_link_detect(aconnector->dc_link);
- else
+ } else {
+ mutex_lock(>dc_lock);
dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
+ mutex_unlock(>dc_lock);
+ }
if (aconnector->fake_enable && aconnector->dc_link->local_sink)
aconnector->fake_enable = false;
@@ -3050,6 +3053,7 @@ static void handle_hpd_irq_helper(struct
amdgpu_dm_connector *aconnector)
#ifdef CONFIG_DRM_AMD_DC_HDCP
struct dm_connector_state *dm_con_state =
to_dm_connector_state(connector->state);
#endif
+ bool ret = false;
if (adev->dm.disable_hpd_irq)
return;
@@ -3081,16 +3085,20 @@ static void handle_hpd_irq_helper(struct
amdgpu_dm_connector *aconnector)
if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
drm_kms_helper_connector_hotplug_event(connector);
+ } else {
+ mutex_lock(>dm.dc_lock);
+ ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
+ mutex_unlock(>dm.dc_lock);
+ if (ret) {
+ amdgpu_dm_update_connector_after_detect(aconnector);
- } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
- amdgpu_dm_update_connector_after_detect(aconnector);
-
- drm_modeset_lock_all(dev);
- dm_restore_drm_connector_state(dev, connector);
- drm_modeset_unlock_all(dev);
+ drm_modeset_lock_all(dev);
+ dm_restore_drm_connector_state(dev, connector);
+ drm_modeset_unlock_all(dev);
- if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
- drm_kms_helper_connector_hotplug_event(connector);
+ if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
+
drm_kms_helper_connector_hotplug_event(connector);
+ }
}
mutex_unlock(>hpd_lock);
@@ -3285,19 +3293,25 @@ static void handle_hpd_rx_irq(void *param)
drm_modeset_unlock_all(dev);
drm_kms_helper_connector_hotplug_event(connector);
- } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
+ } else {
+ bool ret = false;
- if (aconnector->fake_enable)
- aconnector->fake_enable = false;
+ mutex_lock(>dm.dc_lock);
+ ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
+ mutex_unlock(>dm.dc_lock);
- amdgpu_dm_update_connector_after_detect(aconnector);
+ if (ret) {
+ if (aconnector->fake_enable)
+ aconnector->fake_enable = false;
+
amdgpu_dm_update_connector_after_detect(aconnector);
- drm_modeset_lock_all(dev);
- dm_restore_drm_connector_state(dev, connector);
- drm_modeset_unlock_all(dev);
+ drm_modeset_lock_all(dev);
+ dm_restore_drm_connector_state(dev, connector);
+ drm_modeset_unlock_all(dev);
- drm_kms_helper_connector_hotplug_event(connector);
+
drm_kms_helper_connector_hotplug_event(connector);
+ }
}
}
#ifdef CONFIG_DRM_AMD_DC_HDCP
@@ -4302,23 +4316,3
[PATCH 13/21] drm/amd/display: Re-implementing ARGB16161616 pixel format as 22
From: Wellenreiter Ethan [Why] ABGR16161616 colour format was added to dcn10/20/30, and set any ARGB16161616 to the same value as it (26). As such, the HDR10 Green Point y value was too far off of the EDID stated value for DisplayPort. [How] Added back the pixel format as 22 for ARGB16161616 for dcn10/20/30. Reviewed-by: Reza Amini Acked-by: Solomon Chiu Signed-off-by: Wellenreiter Ethan Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 2 ++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 3 +++ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 2 ++ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 3 +++ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 2 ++ 5 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index db7ca4b0cdb9..d4a6504dfe00 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -361,6 +361,8 @@ void dpp1_cnv_setup ( select = INPUT_CSC_SELECT_ICSC; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + pixel_format = 22; + break; case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: pixel_format = 26; /* ARGB16161616_UNORM */ break; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c index 564e061ccb58..b54c12400323 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c @@ -278,6 +278,9 @@ void hubp1_program_pixel_format( SURFACE_PIXEL_FORMAT, 10); break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 22); + break; case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/ REG_UPDATE(DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c index eaa7032f0f1a..ea1f14af0db7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c @@ -166,6 +166,8 @@ static void dpp2_cnv_setup ( select = DCN2_ICSC_SELECT_ICSC_A; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + pixel_format = 22; + break; case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: pixel_format = 26; /* ARGB16161616_UNORM */ break; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c index 9570c2118ccc..936af65381ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c @@ -463,6 +463,9 @@ void hubp2_program_pixel_format( SURFACE_PIXEL_FORMAT, 10); break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 22); + break; case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/ REG_UPDATE(DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c index 3c77949b8110..787b852eeaf2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c @@ -244,6 +244,8 @@ void dpp3_cnv_setup ( select = INPUT_CSC_SELECT_ICSC; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + pixel_format = 22; + break; case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: pixel_format = 26; /* ARGB16161616_UNORM */ break; -- 2.25.1
[PATCH 12/21] drm/amd/display: 3.2.193
From: Aric Cyr Acked-by: Solomon Chiu Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index a0812849794e..1dca016b5782 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.192" +#define DC_VER "3.2.193" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.25.1
[PATCH 11/21] drm/amd/display: update DML1 logic for unbounded req handling
From: "Lei, Jun"
[why]
Unbounded request logic in resource/DML has some issues where
unbounded request is being enabled incorrectly. SW today enables
unbounded request unconditionally in hardware, on the assumption
that HW can always support it in single pipe scenarios.
This worked until now because the same assumption is made in DML.
A new DML update is needed to fix a bug, where there are single
pipe scenarios where unbounded cannot be enabled, and this change
in DML needs to be ported in, and dcn32 resource logic fixed.
[how]
First, dcn32_resource should program unbounded req in HW according
to unbounded req enablement output from DML, as opposed to DML input
Second, port in DML1 update which disables unbounded req in some
scenarios to fix an issue with poor stutter performance
Reviewed-by: Nevenko Stupar
Reviewed-by: Dmytro Laktyushkin
Acked-by: Solomon Chiu
Signed-off-by: Jun Lei
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 9 +
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 9 +
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 95edca4c085b..607172542242 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -110,6 +110,7 @@ dml_get_attr_func(return_bw, mode_lib->vba.ReturnBW);
dml_get_attr_func(tcalc, mode_lib->vba.TCalc);
dml_get_attr_func(fraction_of_urgent_bandwidth,
mode_lib->vba.FractionOfUrgentBandwidth);
dml_get_attr_func(fraction_of_urgent_bandwidth_imm_flip,
mode_lib->vba.FractionOfUrgentBandwidthImmediateFlip);
+
dml_get_attr_func(cstate_max_cap_mode,
mode_lib->vba.DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
dml_get_attr_func(comp_buffer_size_kbytes,
mode_lib->vba.CompressedBufferSizeInkByte);
dml_get_attr_func(pixel_chunk_size_in_kbyte,
mode_lib->vba.PixelChunkSizeInKByte);
@@ -120,6 +121,11 @@ dml_get_attr_func(min_meta_chunk_size_in_byte,
mode_lib->vba.MinMetaChunkSizeByt
dml_get_attr_func(fclk_watermark, mode_lib->vba.Watermark.FCLKChangeWatermark);
dml_get_attr_func(usr_retraining_watermark,
mode_lib->vba.Watermark.USRRetrainingWatermark);
+dml_get_attr_func(comp_buffer_reserved_space_kbytes,
mode_lib->vba.CompBufReservedSpaceKBytes);
+dml_get_attr_func(comp_buffer_reserved_space_64bytes,
mode_lib->vba.CompBufReservedSpace64B);
+dml_get_attr_func(comp_buffer_reserved_space_zs,
mode_lib->vba.CompBufReservedSpaceZs);
+dml_get_attr_func(unbounded_request_enabled,
mode_lib->vba.UnboundedRequestEnabled);
+
#define dml_get_pipe_attr_func(attr, var) double get_##attr(struct
display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned
int num_pipes, unsigned int which_pipe) \
{\
unsigned int which_plane; \
@@ -842,6 +848,9 @@ static void fetch_pipe_params(struct display_mode_lib
*mode_lib)
mode_lib->vba.SynchronizeTimingsFinal =
pipes[0].pipe.dest.synchronize_timings;
mode_lib->vba.DCCProgrammingAssumesScanDirectionUnknownFinal = false;
+
+ mode_lib->vba.DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment
= 0;
+
mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting;
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
if (pipes[k].pipe.src.unbounded_req_mode == 0)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 10ff536ef2a4..acb9434fb955 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -67,6 +67,10 @@ dml_get_attr_decl(min_pixel_chunk_size_in_byte);
dml_get_attr_decl(min_meta_chunk_size_in_byte);
dml_get_attr_decl(fclk_watermark);
dml_get_attr_decl(usr_retraining_watermark);
+dml_get_attr_decl(comp_buffer_reserved_space_kbytes);
+dml_get_attr_decl(comp_buffer_reserved_space_64bytes);
+dml_get_attr_decl(comp_buffer_reserved_space_zs);
+dml_get_attr_decl(unbounded_request_enabled);
#define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib
*mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes,
unsigned int which_pipe)
@@ -470,6 +474,7 @@ struct vba_vars_st {
bool XFCEnabled[DC__NUM_DPP__MAX];
bool ScalerEnabled[DC__NUM_DPP__MAX];
unsigned int VBlankNom[DC__NUM_DPP__MAX];
+ bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment;
// Intermediates/Informational
bool ImmediateFlipSupport;
@@ -513,6 +518,10 @@ struct vba_vars_st {
double StutterPeriodBestCase;
Watermarks Watermark;
bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
+ unsigned int CompBufReservedSpaceKBytes;
+ unsigned int CompBufReservedSpace64B;
+ unsigned int CompBufReservedSpaceZs;
+ bool CompBufRe
[PATCH 10/21] drm/amd/display: Reduce SCDC Status Flags Definition
From: Chris Park
[Why]
Status flags definition is reduced to read
less bytes in SCDC transaction for status update.
[How]
Reduce definition of reserved bytes from 3 to 1
for status update.
Reviewed-by: Charlene Liu
Acked-by: Solomon Chiu
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index b13a516ba0f2..d01d2eeed813 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -93,16 +93,13 @@ union hdmi_scdc_update_read_data {
};
union hdmi_scdc_status_flags_data {
- uint8_t byte[2];
+ uint8_t byte;
struct {
uint8_t CLOCK_DETECTED:1;
uint8_t CH0_LOCKED:1;
uint8_t CH1_LOCKED:1;
uint8_t CH2_LOCKED:1;
uint8_t RESERVED:4;
- uint8_t RESERVED2:8;
- uint8_t RESERVED3:8;
-
} fields;
};
@@ -770,7 +767,7 @@ void dal_ddc_service_read_scdc_data(struct ddc_service
*ddc_service)
sizeof(scramble_status));
offset = HDMI_SCDC_STATUS_FLAGS;
dal_ddc_service_query_ddc_data(ddc_service, slave_address,
- , sizeof(offset), status_data.byte,
+ , sizeof(offset), _data.byte,
sizeof(status_data.byte));
}
}
--
2.25.1
[PATCH 09/21] drm/amd/display: make enable link independent from verified link caps
From: Wenjing Liu
[why]
Ideally link capability should be independent from the link
configuration that we decide to use in enable link. Otherwise if link
capability is changed after validation has completed, we could end up
enabling a link configuration with invalid configuration. This would
lead to over link bandwidth subscription or in the extreme case
causes us to enable HPO link to a DIO stream.
[how]
Add a new struct in pipe ctx called link config. This structure will
contain link configuration to enable a link. It will be populated
during map pool resources after we validate link bandwidth. Remove
the reference of verified link cap during enable link process and
use link config in pipe ctx instead.
Reviewed-by: George Shen
Acked-by: Solomon Chiu
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_debug.c| 2 +
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 27 +--
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 45 +++
.../gpu/drm/amd/display/dc/core/dc_resource.c | 10 ++---
.../gpu/drm/amd/display/dc/inc/core_status.h | 1 +
.../gpu/drm/amd/display/dc/inc/core_types.h | 10 +
.../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 +-
7 files changed, 44 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 283957dbdf93..69f1c2b89a57 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -424,6 +424,8 @@ char *dc_status_to_str(enum dc_status status)
return "No link encoder resource";
case DC_FAIL_DP_PAYLOAD_ALLOCATION:
return "Fail dp payload allocation";
+ case DC_FAIL_DP_LINK_BANDWIDTH:
+ return "Insufficient DP link bandwidth";
case DC_ERROR_UNEXPECTED:
return "Unexpected error";
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index dbdeda60e9e2..65269cd8cb78 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1969,7 +1969,8 @@ static enum dc_status enable_link_dp(struct dc_state
*state,
enum dc_status status;
bool skip_video_pattern;
struct dc_link *link = stream->link;
- struct dc_link_settings link_settings = {0};
+ const struct dc_link_settings *link_settings =
+ _ctx->link_config.dp_link_settings;
bool fec_enable;
int i;
bool apply_seamless_boot_optimization = false;
@@ -1986,9 +1987,6 @@ static enum dc_status enable_link_dp(struct dc_state
*state,
}
}
- /* get link settings for video mode timing */
- decide_link_settings(stream, _settings);
-
/* Train with fallback when enabling DPIA link. Conventional links are
* trained with fallback during sink detection.
*/
@@ -1999,7 +1997,7 @@ static enum dc_status enable_link_dp(struct dc_state
*state,
* Temporary w/a to get DP2.0 link rates to work with SST.
* TODO DP2.0 - Workaround: Remove w/a if and when the issue is
resolved.
*/
- if (dp_get_link_encoding_format(_settings) ==
DP_128b_132b_ENCODING &&
+ if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING
&&
pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
link->dc->debug.set_mst_en_for_sst) {
dp_enable_mst_on_sink(link, true);
@@ -2012,11 +2010,11 @@ static enum dc_status enable_link_dp(struct dc_state
*state,
link->dc->hwss.edp_wait_for_hpd_ready(link, true);
}
- if (dp_get_link_encoding_format(_settings) ==
DP_128b_132b_ENCODING) {
+ if (dp_get_link_encoding_format(link_settings) ==
DP_128b_132b_ENCODING) {
/* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
} else {
pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
- link_settings.link_rate *
LINK_RATE_REF_FREQ_IN_KHZ;
+ link_settings->link_rate *
LINK_RATE_REF_FREQ_IN_KHZ;
if (state->clk_mgr && !apply_seamless_boot_optimization)
state->clk_mgr->funcs->update_clocks(state->clk_mgr,
state, false);
@@ -2032,16 +2030,15 @@ static enum dc_status enable_link_dp(struct dc_state
*state,
skip_video_pattern = true;
- if (link_settings.link_rate == LINK_RATE_LOW)
+ if (link_settings->link_rate == LINK_RATE_LOW)
skip_video_pattern = false;
- if (perform_link_training_with_retries(_settings,
+
[PATCH 08/21] drm/amd/display: Fix black screen when disabling Freesync in OSD
From: Ilya Bakoulin
[Why]
Black screen encountered when disabling Freesync through OSD on some
displays.
[How]
Set the should_disable flag when new top pipe has no plane state to
ensure that pipes get cleaned up.
Reviewed-by: Chris Park
Acked-by: Solomon Chiu
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a448696ee8f2..6b37c653f45e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1085,6 +1085,16 @@ static void disable_dangling_plane(struct dc *dc, struct
dc_state *context)
dc->current_state->stream_count !=
context->stream_count)
should_disable = true;
+ if (old_stream &&
!dc->current_state->res_ctx.pipe_ctx[i].top_pipe) {
+ struct pipe_ctx *old_pipe, *new_pipe;
+
+ old_pipe = >current_state->res_ctx.pipe_ctx[i];
+ new_pipe = >res_ctx.pipe_ctx[i];
+
+ if (old_pipe->plane_state && !new_pipe->plane_state)
+ should_disable = true;
+ }
+
if (should_disable && old_stream) {
dc_rem_all_planes_for_stream(dc, old_stream,
dangling_context);
disable_all_writeback_pipes_for_stream(dc, old_stream,
dangling_context);
--
2.25.1
[PATCH 05/21] drm/amd/display: Fix windowed MPO video with ODM combine for DCN32
From: Samson Tam
[Why]
In single display configuration, windowed MPO does not work
with ODM combine.
[How]
For ODM + MPO window on one half of ODM, only 3 pipes should
be allocated and scaling parameters adjusted to handle this case.
Otherwise, we use 4 pipes.
Move copy_surface_update_to_plane() before dc_add_plane_to_context()
so that it gets the updated rect information when setting up
the pipes.
Add dc_check_boundary_crossing_for_windowed_mpo_with_odm() to force
a full update when we cross a boundary requiring us to reconfigure
the number of pipes between 3 and 4 pipes.
Set config.enable_windowed_mpo_odm to true when we have the
debug.enable_single_display_2to1_odm_policy set to true.
Don't fail validating ODM with windowed MPO if
config.enable_windowed_mpo_odm is true.
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 94 ++
.../gpu/drm/amd/display/dc/core/dc_resource.c | 115 ++
2 files changed, 188 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e13bf66f70e0..a448696ee8f2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2415,6 +2415,96 @@ static enum surface_update_type
check_update_surfaces_for_stream(
return overall_type;
}
+static bool dc_check_is_fullscreen_video(struct rect src, struct rect
clip_rect)
+{
+ int view_height, view_width, clip_x, clip_y, clip_width, clip_height;
+
+ view_height = src.height;
+ view_width = src.width;
+
+ clip_x = clip_rect.x;
+ clip_y = clip_rect.y;
+
+ clip_width = clip_rect.width;
+ clip_height = clip_rect.height;
+
+ /* check for centered video accounting for off by 1 scaling truncation
*/
+ if ((view_height - clip_y - clip_height <= clip_y + 1) &&
+ (view_width - clip_x - clip_width <= clip_x + 1) &&
+ (view_height - clip_y - clip_height >= clip_y - 1) &&
+ (view_width - clip_x - clip_width >= clip_x - 1)) {
+
+ /* when OS scales up/down to letter box, it may end up
+* with few blank pixels on the border due to truncating.
+* Add offset margin to account for this
+*/
+ if (clip_x <= 4 || clip_y <= 4)
+ return true;
+ }
+
+ return false;
+}
+
+static enum surface_update_type
check_boundary_crossing_for_windowed_mpo_with_odm(struct dc *dc,
+ struct dc_surface_update *srf_updates, int surface_count,
+ enum surface_update_type update_type)
+{
+ enum surface_update_type new_update_type = update_type;
+ int i, j;
+ struct pipe_ctx *pipe = NULL;
+ struct dc_stream_state *stream;
+
+ /* Check that we are in windowed MPO with ODM
+* - look for MPO pipe by scanning pipes for first pipe matching
+* surface that has moved ( position change )
+* - MPO pipe will have top pipe
+* - check that top pipe has ODM pointer
+*/
+ if ((surface_count > 1) && dc->config.enable_windowed_mpo_odm) {
+ for (i = 0; i < surface_count; i++) {
+ if (srf_updates[i].surface &&
srf_updates[i].scaling_info
+ &&
srf_updates[i].surface->update_flags.bits.position_change) {
+
+ for (j = 0; j < dc->res_pool->pipe_count; j++) {
+ if (srf_updates[i].surface ==
dc->current_state->res_ctx.pipe_ctx[j].plane_state) {
+ pipe =
>current_state->res_ctx.pipe_ctx[j];
+ stream = pipe->stream;
+ break;
+ }
+ }
+
+ if (pipe && pipe->top_pipe &&
(get_num_odm_splits(pipe->top_pipe) > 0) && stream
+ &&
!dc_check_is_fullscreen_video(stream->src,
srf_updates[i].scaling_info->clip_rect)) {
+ struct rect old_clip_rect,
new_clip_rect;
+ bool old_clip_rect_left,
old_clip_rect_right, old_clip_rect_middle;
+ bool new_clip_rect_left,
new_clip_rect_right, new_clip_rect_middle;
+
+ old_clip_rect =
srf_updates[i].surface->clip_rect;
+ new_clip_rect =
srf_updates[i].scaling_info->clip_rect;
+
+ old_clip_rect_left = ((old_clip
[PATCH 06/21] drm/amd/display: Clear edid when unplug mst connector
From: Wayne Lin [Why] When unplug one sst monitor from a mst hub and plug in the same port with another sst monitor, we don't read the corresponding edid. That's because we detect there is already an edid stored in aconnector->edid which is a stale one. [How] Clean up aconnector->edid when unplug mst connector. Reviewed-by: Hersen Wu Acked-by: Solomon Chiu Signed-off-by: Wayne Lin --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index ee5d6fa34a6b..8237029cedf5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -160,6 +160,7 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) dc_sink_release(dc_sink); aconnector->dc_sink = NULL; + aconnector->edid = NULL; } drm_modeset_unlock(>mst_mgr.base.lock); } @@ -411,6 +412,7 @@ dm_dp_mst_detect(struct drm_connector *connector, dc_sink_release(aconnector->dc_sink); aconnector->dc_sink = NULL; + aconnector->edid = NULL; } return connection_status; -- 2.25.1
[PATCH 07/21] drm/amd/display: Disable PSRSU when DSC enabled on the specific sink
From: Robin Chen
[Why]
Some specific sink is not able to support PSRSU when DSC is turned on.
For this case, fall-back to use PSR1.
Reviewed-by: Anthony Koo
Acked-by: Solomon Chiu
Signed-off-by: Robin Chen
---
.../amd/display/modules/power/power_helpers.c | 33 ++-
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index bc239d38c3c7..235259d6c5a1 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -794,33 +794,34 @@ bool dmcu_load_iram(struct dmcu *dmcu,
*/
bool is_psr_su_specific_panel(struct dc_link *link)
{
- if (link->dpcd_caps.edp_rev >= DP_EDP_14) {
- if (link->dpcd_caps.psr_info.psr_version >=
DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
- return true;
+ bool isPSRSUSupported = false;
+ struct dpcd_caps *dpcd_caps = >dpcd_caps;
+
+ if (dpcd_caps->edp_rev >= DP_EDP_14) {
+ if (dpcd_caps->psr_info.psr_version >=
DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
+ isPSRSUSupported = true;
/*
* Some panels will report PSR capabilities over additional
DPCD bits.
* Such panels are approved despite reporting only PSR v3, as
long as
* the additional bits are reported.
*/
- if (link->dpcd_caps.psr_info.psr_version <
DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)
- return false;
-
- if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) {
+ if (dpcd_caps->sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) {
/*
-* FIXME:
* This is the temporary workaround to disable PSRSU
when system turned on
-* DSC function on the sepcific sink. Once the PSRSU +
DSC is fixed, this
-* condition should be removed.
+* DSC function on the sepcific sink.
*/
- if
(link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)
- return false;
-
- if (link->dpcd_caps.psr_info.force_psrsu_cap == 0x1)
- return true;
+ if (dpcd_caps->psr_info.psr_version <
DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)
+ isPSRSUSupported = false;
+ else if
(dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
+ ((dpcd_caps->sink_dev_id_str[1] == 0x08 &&
dpcd_caps->sink_dev_id_str[0] == 0x08) ||
+ (dpcd_caps->sink_dev_id_str[1] == 0x08 &&
dpcd_caps->sink_dev_id_str[0] == 0x07)))
+ isPSRSUSupported = false;
+ else if (dpcd_caps->psr_info.force_psrsu_cap == 0x1)
+ isPSRSUSupported = true;
}
}
- return false;
+ return isPSRSUSupported;
}
/**
--
2.25.1
[PATCH 04/21] drm/amd/display: Removing assert statements for Linux
From: Saaem Rizvi
[WHY]
Assert statements causing several bugs on Linux DM
[HOW]
Removing assert statement for Linux DM
(ASSERT(result == VBIOSSMC_Result_OK)). Also adding
logging statements for setting dcfclk.
Reviewed-by: Gabe Teeger
Acked-by: Solomon Chiu
Signed-off-by: Saaem Rizvi
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 8 ++--
.../gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c| 7 ++-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 8 ++--
.../gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c| 8 ++--
.../gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c| 8 ++--
5 files changed, 30 insertions(+), 9 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index 4137394a6ace..27fbe906682f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -101,9 +101,9 @@ static int rn_vbios_smu_send_msg_with_param(struct
clk_mgr_internal *clk_mgr,
uint32_t result;
result = rn_smu_wait_for_response(clk_mgr, 10, 20);
- ASSERT(result == VBIOSSMC_Result_OK);
- smu_print("SMU response after wait: %d\n", result);
+ if (result != VBIOSSMC_Result_OK)
+ smu_print("SMU Response was not OK. SMU response after wait
received is: %d\n", result);
if (result == VBIOSSMC_Status_BUSY) {
return -1;
@@ -188,6 +188,10 @@ int rn_vbios_smu_set_hard_min_dcfclk(struct
clk_mgr_internal *clk_mgr, int reque
VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
khz_to_mhz_ceil(requested_dcfclk_khz));
+#ifdef DBG
+ smu_print("actual_dcfclk_set_mhz %d is set to : %d\n",
actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
+#endif
+
return actual_dcfclk_set_mhz * 1000;
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
index d8f03328558b..e4f96b6fd79d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
@@ -102,7 +102,8 @@ static int dcn301_smu_send_msg_with_param(struct
clk_mgr_internal *clk_mgr,
result = dcn301_smu_wait_for_response(clk_mgr, 10, 20);
- smu_print("SMU response after wait: %d\n", result);
+ if (result != VBIOSSMC_Result_OK)
+ smu_print("SMU Response was not OK. SMU response after wait
received is: %d\n", result);
if (result == VBIOSSMC_Status_BUSY) {
return -1;
@@ -179,6 +180,10 @@ int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal
*clk_mgr, int request
VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
khz_to_mhz_ceil(requested_dcfclk_khz));
+#ifdef DBG
+ smu_print("actual_dcfclk_set_mhz %d is set to : %d\n",
actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
+#endif
+
return actual_dcfclk_set_mhz * 1000;
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
index 6a17f7ed4d01..090b2c02aee1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -108,9 +108,9 @@ static int dcn31_smu_send_msg_with_param(struct
clk_mgr_internal *clk_mgr,
uint32_t result;
result = dcn31_smu_wait_for_response(clk_mgr, 10, 20);
- ASSERT(result == VBIOSSMC_Result_OK);
- smu_print("SMU response after wait: %d\n", result);
+ if (result != VBIOSSMC_Result_OK)
+ smu_print("SMU Response was not OK. SMU response after wait
received is: %d\n", result);
if (result == VBIOSSMC_Status_BUSY) {
return -1;
@@ -202,6 +202,10 @@ int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal
*clk_mgr, int requeste
VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
khz_to_mhz_ceil(requested_dcfclk_khz));
+#ifdef DBG
+ smu_print("actual_dcfclk_set_mhz %d is set to : %d\n",
actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
+#endif
+
return actual_dcfclk_set_mhz * 1000;
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
index 74a78fda62fb..925d6e13620e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
@@ -136,9 +136,9 @@ static int dcn315_smu_send_msg_with_param(
uint32_t result;
result = dcn315_smu_wait_for_response(clk_mgr, 10, 20);
- ASSERT(result == VBIOSSMC_Re
[PATCH 03/21] drm/amd/display: Helper function for ALPM initialization
From: muansari
[WHY]
Needed a helper function for ALPM DPCD initialization
[HOW]
Refactoring to put ALPM initialization in a helper function
Reviewed-by: Anthony Koo
Acked-by: Solomon Chiu
Signed-off-by: Muhammad Ansari
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 27 ---
drivers/gpu/drm/amd/display/dc/dc_link.h | 2 ++
2 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 335ca5b14fa7..dbdeda60e9e2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2734,6 +2734,22 @@ static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
}
+bool dc_power_alpm_dpcd_enable(struct dc_link *link, bool enable)
+{
+ bool ret = false;
+ union dpcd_alpm_configuration alpm_config;
+
+ if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
+ memset(_config, 0, sizeof(alpm_config));
+
+ alpm_config.bits.ENABLE = (enable ? true : false);
+ ret = dm_helpers_dp_write_dpcd(link->ctx, link,
+ DP_RECEIVER_ALPM_CONFIG, _config.raw,
+ sizeof(alpm_config.raw));
+ }
+ return ret;
+}
+
/enable_link***/
static enum dc_status enable_link(
struct dc_state *state,
@@ -3228,7 +3244,6 @@ bool dc_link_setup_psr(struct dc_link *link,
unsigned int panel_inst;
/* updateSinkPsrDpcdConfig*/
union dpcd_psr_configuration psr_configuration;
- union dpcd_alpm_configuration alpm_configuration;
union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
@@ -3284,15 +3299,7 @@ bool dc_link_setup_psr(struct dc_link *link,
sizeof(psr_configuration.raw));
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
- memset(_configuration, 0, sizeof(alpm_configuration));
-
- alpm_configuration.bits.ENABLE = 1;
- dm_helpers_dp_write_dpcd(
- link->ctx,
- link,
- DP_RECEIVER_ALPM_CONFIG,
- _configuration.raw,
- sizeof(alpm_configuration.raw));
+ dc_power_alpm_dpcd_enable(link, true);
psr_context->su_granularity_required =
psr_config->su_granularity_required;
psr_context->su_y_granularity =
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 29c0040a6dd4..023774b94da3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -320,6 +320,8 @@ bool dc_link_setup_psr(struct dc_link *dc_link,
const struct dc_stream_state *stream, struct psr_config
*psr_config,
struct psr_context *psr_context);
+bool dc_power_alpm_dpcd_enable(struct dc_link *link, bool enable);
+
void dc_link_get_psr_residency(const struct dc_link *link, uint32_t
*residency);
void dc_link_blank_all_dp_displays(struct dc *dc);
--
2.25.1
[PATCH 02/21] drm/amd/display: Check for DP2.0 when checking ODM combine
From: Wesley Chalmers
[WHY]
Certain DP 2.0 modes may fail validation if DP 2.0 is not considered for
ODM combine.
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
Signed-off-by: Wesley Chalmers
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 448fbbcdf88a..8d4c1cf1b8f3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -4310,6 +4310,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
if (v->ODMCombinePolicy ==
dm_odm_combine_policy_none
|| !(v->Output[k] == dm_dp ||
+v->Output[k] == dm_dp2p0 ||
v->Output[k] == dm_edp)) {
v->ODMCombineEnablePerState[i][k] =
dm_odm_combine_mode_disabled;
v->PlaneRequiredDISPCLK =
v->PlaneRequiredDISPCLKWithoutODMCombine;
--
2.25.1
[PATCH 01/21] drm/amd/display: Exit SubVP if MPO in use
From: "Lee, Alvin"
[Description]
Exit SubVP if MPO is in use since SubVP + MPO together is not supported.
- Don't add SubVP at validation time if we see MPO is in use
Issues fixed in the SubVP / MPO transition:
1. Enable phantom pipes in post unlock function to prevent underflow
when an active pipe is being transitioned to be a phantom pipe (VTG
updates take place right away). Also must wait for VUPDATE of the main
pipe to complete first
2. Don't wait for MPCC idle when transitioning a phantom pipe to an
actual pipe. MPCC_STATUS is never asserted due to OTG being off for
phantom pipes
3. When transitioning an active pipe to phantom, program DET right away
(same as disabling the pipe) or the DET update will only take when
the phantom pipe is enabled which can cause DET allocation errors.
4. For K1/K2 programming of phantom pipes, use same settings as the
main pipe. Also don't program K1 / K2 = 0xF ever since the field is only
1 / 2 bits wide.
Reviewed-by: Jun Lei
Acked-by: Solomon Chiu
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 27 +--
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +-
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 72 +--
4 files changed, 92 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 89a2f6749239..e13bf66f70e0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3208,15 +3208,21 @@ static void commit_planes_for_stream(struct dc *dc,
if (should_lock_all_pipes &&
dc->hwss.interdependent_update_lock) {
dc->hwss.interdependent_update_lock(dc, context, false);
+ } else {
+ dc->hwss.pipe_control_lock(dc, top_pipe_to_program,
false);
+ }
+ dc->hwss.post_unlock_program_front_end(dc, context);
+
+ /* Since phantom pipe programming is moved to
post_unlock_program_front_end,
+* move the SubVP lock to after the phantom pipes have been
setup
+*/
+ if (should_lock_all_pipes &&
dc->hwss.interdependent_update_lock) {
if (dc->hwss.subvp_pipe_control_lock)
dc->hwss.subvp_pipe_control_lock(dc, context,
false, should_lock_all_pipes, NULL, subvp_prev_use);
} else {
- dc->hwss.pipe_control_lock(dc, top_pipe_to_program,
false);
if (dc->hwss.subvp_pipe_control_lock)
dc->hwss.subvp_pipe_control_lock(dc, context,
false, should_lock_all_pipes, NULL, subvp_prev_use);
}
-
- dc->hwss.post_unlock_program_front_end(dc, context);
return;
}
@@ -3346,12 +3352,8 @@ static void commit_planes_for_stream(struct dc *dc,
if (should_lock_all_pipes &&
dc->hwss.interdependent_update_lock) {
dc->hwss.interdependent_update_lock(dc, context, false);
- if (dc->hwss.subvp_pipe_control_lock)
- dc->hwss.subvp_pipe_control_lock(dc, context,
false, should_lock_all_pipes, NULL, subvp_prev_use);
} else {
dc->hwss.pipe_control_lock(dc, top_pipe_to_program,
false);
- if (dc->hwss.subvp_pipe_control_lock)
- dc->hwss.subvp_pipe_control_lock(dc, context,
false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
}
if ((update_type != UPDATE_TYPE_FAST) &&
stream->update_flags.bits.dsc_changed)
@@ -3385,6 +3387,17 @@ static void commit_planes_for_stream(struct dc *dc,
if (update_type != UPDATE_TYPE_FAST)
dc->hwss.post_unlock_program_front_end(dc, context);
+ /* Since phantom pipe programming is moved to
post_unlock_program_front_end,
+* move the SubVP lock to after the phantom pipes have been
setup
+*/
+ if (should_lock_all_pipes &&
dc->hwss.interdependent_update_lock) {
+ if (dc->hwss.subvp_pipe_control_lock)
+ dc->hwss.subvp_pipe_control_lock(dc, context,
false, should_lock_all_pipes, NULL, subvp_prev_use);
+ } else {
+ if (dc->hwss.subvp_pipe_control_lock)
+ dc->hwss.subvp_pipe_control_lock(dc, context,
false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
+ }
+
// Fire manual trigger only when bottom plane is flipped
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_
[PATCH 00/21] DC Patches July 11, 2022
This DC patchset brings improvements in multiple areas. In summary, we highlight: - Fixes for MST, MPO, PSRSU, DP 2.0, Freesync and others - Add register offsets of NBI and DCN. - Improvement of ALPM - Removing assert statement for Linux DM - Re-implementing ARGB16161616 pixel format Aric Cyr (2): drm/amd/display: 3.2.193 drm/amd/display: 3.2.194 Aurabindo Pillai (1): drm/amd/display: Add NBIO reg offsets to DC Charlene Liu (1): drm/amd/display: add system info table log Chris Park (1): drm/amd/display: Reduce SCDC Status Flags Definition Fangzhi Zuo (1): drm/amd/display: Ignore First MST Sideband Message Return Error Harry Wentland (1): drm/amd/display: Add DCN reg offsets to DC Ilya Bakoulin (1): drm/amd/display: Fix black screen when disabling Freesync in OSD Lee, Alvin (1): drm/amd/display: Exit SubVP if MPO in use Lei, Jun (1): drm/amd/display: update DML1 logic for unbounded req handling Robin Chen (1): drm/amd/display: Disable PSRSU when DSC enabled on the specific sink Rodrigo Siqueira (1): drm/amd/display: Fix wrong reference Saaem Rizvi (1): drm/amd/display: Removing assert statements for Linux Samson Tam (2): drm/amd/display: Fix windowed MPO video with ODM combine for DCN32 drm/amd/display: Fix lag when moving windowed MPO across display using ODM 2:1 combine Wayne Lin (2): drm/amd/display: Clear edid when unplug mst connector drm/amd/display: Grab dc_lock before detecting link Wellenreiter, Ethan (1): drm/amd/display: Re-implementing ARGB16161616 pixel format as 22 Wenjing Liu (1): drm/amd/display: make enable link independent from verified link caps Wesley Chalmers (1): drm/amd/display: Check for DP2.0 when checking ODM combine muansari (1): drm/amd/display: Helper function for ALPM initialization .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 115 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 8 + .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 11 +- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 19 +++ .../drm/amd/display/dc/bios/bios_parser2.c| 30 .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 8 +- .../display/dc/clk_mgr/dcn301/dcn301_smu.c| 7 +- .../amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 8 +- .../display/dc/clk_mgr/dcn315/dcn315_smu.c| 8 +- .../display/dc/clk_mgr/dcn316/dcn316_smu.c| 8 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 136 ++- .../gpu/drm/amd/display/dc/core/dc_debug.c| 2 + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 54 +++--- .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 7 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 45 ++--- .../gpu/drm/amd/display/dc/core/dc_resource.c | 157 ++ drivers/gpu/drm/amd/display/dc/dc.h | 16 +- drivers/gpu/drm/amd/display/dc/dc_link.h | 2 + drivers/gpu/drm/amd/display/dc/dc_types.h | 3 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 2 + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 3 + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +- .../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 2 + .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 3 + .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 72 +++- .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 2 + .../dc/dml/dcn31/display_mode_vba_31.c| 1 + .../drm/amd/display/dc/dml/display_mode_vba.c | 9 + .../drm/amd/display/dc/dml/display_mode_vba.h | 9 + .../gpu/drm/amd/display/dc/inc/core_status.h | 1 + .../gpu/drm/amd/display/dc/inc/core_types.h | 37 + .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 +- .../amd/display/modules/power/power_helpers.c | 33 ++-- 33 files changed, 660 insertions(+), 164 deletions(-) -- 2.25.1
[PATCH 12/12] drm/amd/display: 3.2.174
From: Aric Cyr This version brings along following fixes: - add debug option to bypass ssinfo from bios. - Refactor fixed VS logic for non-transparent mode - add cable ID support for usb c connector - clear remote dc_sink when stop mst - Ignore Transitional Invalid Link Rate Error Message - Fix wrong resolution with DP/VGA adapter - Refactor PSR DPCD caps detection - Set compbuf size to min at prep prevent overbook crb - lock/un-lock cursor if odm pipe split used - OVT Update on InfoFrame and Mode Management Acked-by: Solomon Chiu Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index c5a36c81d0b8..55d43d642b38 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.173" +#define DC_VER "3.2.174" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.25.1
[PATCH 11/12] drm/amd/display: add debug option to bypass ssinfo from bios.
From: Charlene Liu
[Why]
add debug option to bypass ssinfo from bios.
Reviewed-by: Chris Park
Acked-by: Solomon Chiu
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 2 ++
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 2 ++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
3 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index b210f8e9d592..dfba6138f538 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -374,6 +374,8 @@ void dce_clock_read_ss_info(struct clk_mgr_internal
*clk_mgr_dce)
clk_mgr_dce->dprefclk_ss_percentage =
info.spread_spectrum_percentage;
}
+ if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss)
+ clk_mgr_dce->dprefclk_ss_percentage = 0;
}
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index e17c9938cee5..59fdd7f0d609 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -697,6 +697,8 @@ void dcn31_clk_mgr_construct(
clk_mgr->base.base.dprefclk_khz = 60;
clk_mgr->base.dccg->ref_dtbclk_khz = 60;
dce_clock_read_ss_info(_mgr->base);
+ /*if bios enabled SS, driver needs to adjust dtb clock, only enable
with correct bios*/
+ //clk_mgr->base.dccg->ref_dtbclk_khz =
dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal,
clk_mgr->base.base.dprefclk_khz);
clk_mgr->base.base.bw_params = _bw_params;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 9fa87a426f9c..c5a36c81d0b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -709,6 +709,7 @@ struct dc_debug_options {
union dpia_debug_options dpia_debug;
#endif
bool apply_vendor_specific_lttpr_wa;
+ bool ignore_dpref_ss;
};
struct gpu_info_soc_bounding_box_v1_0;
--
2.25.1
[PATCH 10/12] drm/amd/display: [FW Promotion] Release 0.0.105.0
From: Anthony Koo Acked-by: Solomon Chiu Signed-off-by: Anthony Koo --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index bc889492f9d7..d906ae8099b3 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -47,10 +47,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0x1422ef84 +#define DMUB_FW_VERSION_GIT_HASH 0x5fb9349b #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 104 +#define DMUB_FW_VERSION_REVISION 105 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 -- 2.25.1
[PATCH 09/12] drm/amd/display: Refactor fixed VS logic for non-transparent mode
From: "Shen, George"
[Why]
All fixed VS/PE link training sequence should be refactored
into a separate function outside of the standard link training
sequence. This includes the sequence for non-transparent
mode.
[How]
Isolate link training sequence for fixed VS/PE non-transparent
mode into a separate function.
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
Signed-off-by: George Shen
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 102 +-
1 file changed, 97 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index bfd0e48d67a5..5688b15ca9e6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2301,7 +2301,96 @@ static enum link_training_result
dp_perform_128b_132b_link_training(
return result;
}
-static enum link_training_result
dc_link_dp_perform_fixed_vs_pe_training_sequence(
+static enum link_training_result
perform_fixed_vs_pe_nontransparent_training_sequence(
+ struct dc_link *link,
+ const struct link_resource *link_res,
+ struct link_training_settings *lt_settings)
+{
+ enum link_training_result status = LINK_TRAINING_SUCCESS;
+ uint8_t lane = 0;
+ uint8_t toggle_rate = 0x6;
+ uint8_t target_rate = 0x6;
+ bool apply_toggle_rate_wa = false;
+ uint8_t repeater_cnt;
+ uint8_t repeater_id;
+
+ /* Fixed VS/PE specific: Force CR AUX RD Interval to at least 16ms */
+ if (lt_settings->cr_pattern_time < 16000)
+ lt_settings->cr_pattern_time = 16000;
+
+ /* Fixed VS/PE specific: Toggle link rate */
+ apply_toggle_rate_wa = (link->vendor_specific_lttpr_link_rate_wa ==
target_rate);
+ target_rate = get_dpcd_link_rate(_settings->link_settings);
+ toggle_rate = (target_rate == 0x6) ? 0xA : 0x6;
+
+ if (apply_toggle_rate_wa)
+ lt_settings->link_settings.link_rate = toggle_rate;
+
+ if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
+ start_clock_recovery_pattern_early(link, link_res, lt_settings,
DPRX);
+
+ /* 1. set link rate, lane count and spread. */
+ dpcd_set_link_settings(link, lt_settings);
+
+ /* Fixed VS/PE specific: Toggle link rate back*/
+ if (apply_toggle_rate_wa) {
+ core_link_write_dpcd(
+ link,
+ DP_LINK_BW_SET,
+ _rate,
+ 1);
+ }
+
+ link->vendor_specific_lttpr_link_rate_wa = target_rate;
+
+ if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
+
+ /* 2. perform link training (set link training done
+* to false is done as well)
+*/
+ repeater_cnt =
dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
+
+ for (repeater_id = repeater_cnt; (repeater_id > 0 && status ==
LINK_TRAINING_SUCCESS);
+ repeater_id--) {
+ status = perform_clock_recovery_sequence(link,
link_res, lt_settings, repeater_id);
+
+ if (status != LINK_TRAINING_SUCCESS) {
+ repeater_training_done(link, repeater_id);
+ break;
+ }
+
+ status = perform_channel_equalization_sequence(link,
+ link_res,
+ lt_settings,
+ repeater_id);
+
+ repeater_training_done(link, repeater_id);
+
+ if (status != LINK_TRAINING_SUCCESS)
+ break;
+
+ for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
+ lt_settings->dpcd_lane_settings[lane].raw = 0;
+
lt_settings->hw_lane_settings[lane].VOLTAGE_SWING = 0;
+
lt_settings->hw_lane_settings[lane].PRE_EMPHASIS = 0;
+ }
+ }
+ }
+
+ if (status == LINK_TRAINING_SUCCESS) {
+ status = perform_clock_recovery_sequence(link, link_res,
lt_settings, DPRX);
+ if (status == LINK_TRAINING_SUCCESS) {
+ status = perform_channel_equalization_sequence(link,
+ link_res,
+
lt_settings,
+ DPRX);
+ }
+ }
+
+ return status;
+}
+
+static enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
struct dc_lin
[PATCH 08/12] drm/amd/display: add cable ID support for usb c connector
From: Wenjing Liu
[how]
Call to DMUB to retrieve usb c cable ID data from PD firmware.
If cable id is retrieved from DMUB, skip reading cable ID from RX.
Reviewed-by: George Shen
Acked-by: Solomon Chiu
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 100 --
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 2 +-
drivers/gpu/drm/amd/display/dc/dc_link.h | 8 +-
.../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 40 +++
7 files changed, 117 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 1d6b6ed3f24c..34ca1ffcf4d1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1305,7 +1305,7 @@ static bool detect_link_and_local_sink(struct dc_link
*link,
*/
link->dongle_max_pix_clk = 0;
- dc_link_dp_clear_rx_status(link);
+ dc_link_clear_dprx_states(link);
}
LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid
same=%d\n",
@@ -1986,7 +1986,7 @@ static enum dc_status enable_link_dp(struct dc_state
*state,
msleep(post_oui_delay);
// similarly, mode switch can cause loss of cable ID
- dpcd_update_cable_id(link);
+ dpcd_write_cable_id_to_dprx(link);
skip_video_pattern = true;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index bc6161f52bfa..bfd0e48d67a5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -51,6 +51,13 @@ static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
#include "link_dpcd.h"
+#ifndef MAX
+#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
+#endif
+#ifndef MIN
+#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
+#endif
+
/* maximum pre emphasis level allowed for each voltage swing level*/
static const enum dc_pre_emphasis
voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
@@ -2986,11 +2993,11 @@ static enum dc_link_rate get_cable_max_link_rate(struct
dc_link *link)
{
enum dc_link_rate cable_max_link_rate = LINK_RATE_HIGH3;
- if (link->dpcd_caps.cable_attributes.bits.UHBR10_20_CAPABILITY &
DP_UHBR20)
+ if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR20)
cable_max_link_rate = LINK_RATE_UHBR20;
- else if (link->dpcd_caps.cable_attributes.bits.UHBR13_5_CAPABILITY)
+ else if (link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY)
cable_max_link_rate = LINK_RATE_UHBR13_5;
- else if (link->dpcd_caps.cable_attributes.bits.UHBR10_20_CAPABILITY &
DP_UHBR10)
+ else if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR10)
cable_max_link_rate = LINK_RATE_UHBR10;
return cable_max_link_rate;
@@ -5051,11 +5058,52 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
return is_lttpr_present;
}
+static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id
*cable_id)
+{
+ union dmub_rb_cmd cmd;
+
+ if (!link->ctx->dmub_srv ||
+ link->ep_type != DISPLAY_ENDPOINT_PHY ||
+ link->link_enc->features.flags.bits.DP_IS_USB_C == 0)
+ return false;
+
+ memset(, 0, sizeof(cmd));
+ cmd.cable_id.header.type = DMUB_CMD_GET_USBC_CABLE_ID;
+ cmd.cable_id.header.payload_bytes = sizeof(cmd.cable_id.data);
+ cmd.cable_id.data.input.phy_inst = resource_transmitter_to_phy_idx(
+ link->dc, link->link_enc->transmitter);
+ if (dc_dmub_srv_cmd_with_reply_data(link->ctx->dmub_srv, ) &&
+ cmd.cable_id.header.ret_status == 1)
+ cable_id->raw = cmd.cable_id.data.output_raw;
-static bool is_usbc_connector(struct dc_link *link)
+ return cmd.cable_id.header.ret_status == 1;
+}
+
+static union dp_cable_id intersect_cable_id(
+ union dp_cable_id *a, union dp_cable_id *b)
{
- return link->link_enc &&
- link->link_enc->features.flags.bits.DP_IS_USB_C;
+ union dp_cable_id out;
+
+ out.bits.UHBR10_20_CAPABILITY = MIN(a->bits.UHBR10_20_CAPABILITY,
+ b->bits.UHBR10_20_CAPABILITY);
+ out.bits.UHBR13_5_CAPABILITY = MIN(a->bits.UHBR13_5_CAPABILITY,
+ b->bits.UHBR13_5_CAPABILITY);
+ out.bits.CABLE_TYPE = MAX(a->bits.CABLE_TYPE, b->bits.CABLE_TYPE);
+
+ return out;
+}
+
+static void retrieve_ca
[PATCH 07/12] drm/amd/display: clear remote dc_sink when stop mst
From: Wayne Lin
[Why]
Currently, we don't have code path to release remote dc_sink when unplug
MST hub from the system. After few times hotplug, we hit the limition of
maximum number of remote dc_sink and can't light up new connected monitor
anymore.
[How]
Releasing all remote dc_sink at dm_helpers_dp_mst_stop_top_mgr() was
removed by previous patch. Restore it.
Reviewed-by: Jerry Zuo
Acked-by: Solomon Chiu
Signed-off-by: Wayne Lin
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 20 ++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 9536e819d5b3..6b2f6466abe9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -451,6 +451,7 @@ bool dm_helpers_dp_mst_stop_top_mgr(
struct dc_link *link)
{
struct amdgpu_dm_connector *aconnector = link->priv;
+ uint8_t i;
if (!aconnector) {
DRM_ERROR("Failed to find connector for link!");
@@ -460,9 +461,26 @@ bool dm_helpers_dp_mst_stop_top_mgr(
DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
aconnector, aconnector->base.base.id);
- if (aconnector->mst_mgr.mst_state == true)
+ if (aconnector->mst_mgr.mst_state == true) {
drm_dp_mst_topology_mgr_set_mst(>mst_mgr, false);
+ for (i = 0; i < MAX_SINKS_PER_LINK; i++) {
+ if (link->remote_sinks[i] == NULL)
+ continue;
+
+ if (link->remote_sinks[i]->sink_signal ==
+ SIGNAL_TYPE_DISPLAY_PORT_MST) {
+ dc_link_remove_remote_sink(link,
link->remote_sinks[i]);
+
+ if (aconnector->dc_sink) {
+ dc_sink_release(aconnector->dc_sink);
+ aconnector->dc_sink = NULL;
+
aconnector->dc_link->cur_link_settings.lane_count = 0;
+ }
+ }
+ }
+ }
+
return false;
}
--
2.25.1
[PATCH 06/12] drm/amd/display: Ignore Transitional Invalid Link Rate Error Message
From: Fangzhi Zuo
[Why]
When hotplug or unplug happens, each stream disabled one by one, and then
enable any alived streams. Link phy and payload table is cleared when 1st
stream is disabled. That causes the error message pops up when disable 2nd
stream. There is no active stream after link_rate is cleared.
After all streams are disabled, link will be trained again and link rate is
assigned to any alived streams.
Therefore there is no harm for the error message that represents invalid
link rate value in the atomic reset transitional time period.
[How]
Downgrade the log level from ERROR to DEBUG.
Reviewed-by: Wayne Lin
Acked-by: Solomon Chiu
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c553d0ea63d3..1d6b6ed3f24c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3921,7 +3921,7 @@ static enum dc_status deallocate_mst_payload(struct
pipe_ctx *pipe_ctx)
>mst_stream_alloc_table);
break;
case DP_UNKNOWN_ENCODING:
- DC_LOG_ERROR("Failure: unknown encoding format\n");
+ DC_LOG_DEBUG("Unknown encoding format\n");
return DC_ERROR_UNEXPECTED;
}
--
2.25.1
[PATCH 05/12] drm/amd/display: Fix wrong resolution with DP/VGA adapter
From: Ilya
[Why]
Hotplugging the VGA side of some DP/VGA adapters caused the display to
light up with the wrong (non-native) resolution.
This is caused by the adapter misbehaving by reporting the wrong number
of downstream ports when the VGA side is unplugged (reports 1 instead of
0), but only if the SINK_COUNT DPCD register is read more than once.
[How]
To work around the adapter behavior, remove the sink if link is
detected, but EDID cannot be read.
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
Signed-off-by: Ilya
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c| 16
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c| 3 +++
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 48858e31b092..c553d0ea63d3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1197,6 +1197,22 @@ static bool detect_link_and_local_sink(struct dc_link
*link,
return false;
}
+
+ if (link->type == dc_connection_sst_branch &&
+ link->dpcd_caps.dongle_type ==
+ DISPLAY_DONGLE_DP_VGA_CONVERTER
&&
+ reason == DETECT_REASON_HPDRX) {
+ /* Abort detection for DP-VGA adapters when EDID
+* can't be read and detection reason is
VGA-side
+* hotplug
+*/
+ if (prev_sink)
+ dc_sink_release(prev_sink);
+ link_disconnect_sink(link);
+
+ return true;
+ }
+
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 24dc662ec3e4..f1bbd918de35 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -298,6 +298,9 @@ static uint32_t defer_delay_converter_wa(
if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER &&
link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
+ (link->dpcd_caps.branch_fw_revision[0] < 0x01 ||
+ (link->dpcd_caps.branch_fw_revision[0] == 0x01
&&
+ link->dpcd_caps.branch_fw_revision[1] < 0x40))
&&
!memcmp(link->dpcd_caps.branch_dev_name,
DP_VGA_DONGLE_BRANCH_DEV_NAME,
sizeof(link->dpcd_caps.branch_dev_name)))
--
2.25.1
[PATCH 04/12] drm/amd/display: Refactor PSR DPCD caps detection
From: Po Ting Chen
[Why]
To move the PSR DPCD caps detection into detect_edp_sink_caps()
Reviewed-by: Anthony Koo
Acked-by: Solomon Chiu
Signed-off-by: Po Ting Chen
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 58 ++-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 28 +
drivers/gpu/drm/amd/display/dc/dc.h | 4 +-
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 30 ++
.../amd/display/include/ddc_service_types.h | 1 +
6 files changed, 70 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index d7611c81fca8..d49aa8d1c2c4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -857,9 +857,9 @@ static int psr_capability_show(struct seq_file *m, void
*data)
if (!(link->connector_signal & SIGNAL_TYPE_EDP))
return -ENODEV;
- seq_printf(m, "Sink support: %s",
yesno(link->dpcd_caps.psr_caps.psr_version != 0));
- if (link->dpcd_caps.psr_caps.psr_version)
- seq_printf(m, " [0x%02x]",
link->dpcd_caps.psr_caps.psr_version);
+ seq_printf(m, "Sink support: %s",
yesno(link->dpcd_caps.psr_info.psr_version != 0));
+ if (link->dpcd_caps.psr_info.psr_version)
+ seq_printf(m, " [0x%02x]",
link->dpcd_caps.psr_info.psr_version);
seq_puts(m, "\n");
seq_printf(m, "Driver support: %s",
yesno(link->psr_settings.psr_feature_enabled));
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index a009fc654ac9..0c923a90615c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -28,49 +28,6 @@
#include "dm_helpers.h"
#include "amdgpu_dm.h"
-static bool link_get_psr_caps(struct dc_link *link)
-{
- uint8_t psr_dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
- uint8_t edp_rev_dpcd_data;
-
-
-
- if (!dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
- psr_dpcd_data, sizeof(psr_dpcd_data)))
- return false;
-
- if (!dm_helpers_dp_read_dpcd(NULL, link, DP_EDP_DPCD_REV,
- _rev_dpcd_data,
sizeof(edp_rev_dpcd_data)))
- return false;
-
- link->dpcd_caps.psr_caps.psr_version = psr_dpcd_data[0];
- link->dpcd_caps.psr_caps.edp_revision = edp_rev_dpcd_data;
-
-#ifdef CONFIG_DRM_AMD_DC_DCN
- if (link->dpcd_caps.psr_caps.psr_version > 0x1) {
- uint8_t alpm_dpcd_data;
- uint8_t su_granularity_dpcd_data;
-
- if (!dm_helpers_dp_read_dpcd(NULL, link, DP_RECEIVER_ALPM_CAP,
- _dpcd_data,
sizeof(alpm_dpcd_data)))
- return false;
-
- if (!dm_helpers_dp_read_dpcd(NULL, link,
DP_PSR2_SU_Y_GRANULARITY,
- _granularity_dpcd_data,
sizeof(su_granularity_dpcd_data)))
- return false;
-
- link->dpcd_caps.psr_caps.y_coordinate_required =
psr_dpcd_data[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
- link->dpcd_caps.psr_caps.su_granularity_required =
psr_dpcd_data[1] & DP_PSR2_SU_GRANULARITY_REQUIRED;
-
- link->dpcd_caps.psr_caps.alpm_cap = alpm_dpcd_data &
DP_ALPM_CAP;
- link->dpcd_caps.psr_caps.standby_support = alpm_dpcd_data & (1
<< 1);
-
- link->dpcd_caps.psr_caps.su_y_granularity =
su_granularity_dpcd_data;
- }
-#endif
- return true;
-}
-
#ifdef CONFIG_DRM_AMD_DC_DCN
static bool link_supports_psrsu(struct dc_link *link)
{
@@ -82,12 +39,12 @@ static bool link_supports_psrsu(struct dc_link *link)
if (dc->ctx->dce_version < DCN_VERSION_3_1)
return false;
- if (!link->dpcd_caps.psr_caps.alpm_cap ||
- !link->dpcd_caps.psr_caps.y_coordinate_required)
+ if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP ||
+ !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED)
return false;
- if (link->dpcd_caps.psr_caps.su_granularity_required &&
- !link->dpcd_caps.psr_caps.su_y_granularity)
+ if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED
&&
+ !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap)
return false;
return true;
@@ -107,12 +64,7 @@ void amdgpu_dm_set_psr_caps(struct dc_link *link)
if (link->type == dc_connection_none)
[PATCH 03/12] drm/amd/display: Set compbuf size to min at prep prevent overbook crb
From: "Ma, Duncan"
[Why]
Detbuffer size is dynamically set for dcn31x. At certain moment,
compbuf+(def size * num pipes) > config return buffer size causing
flickering. This is easily reproducible when MPO is
enabled with two displays.
[How]
At prepare BW, use the min comp buffer size. When it is to
optimize BW, set compbuf size back to maximum possible size.
Reviewed-by: Charlene Liu
Reviewed-by: Charlene Liu
Acked-by: Solomon Chiu
Signed-off-by: Duncan Ma
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 12 ++--
.../drm/amd/display/dc/dml/display_mode_structs.h| 1 +
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 20a9cbb7c0a8..1ef880fed776 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1818,6 +1818,7 @@ void dcn20_prepare_bandwidth(
struct dc_state *context)
{
struct hubbub *hubbub = dc->res_pool->hubbub;
+ unsigned int compbuf_size_kb = 0;
dc->clk_mgr->funcs->update_clocks(
dc->clk_mgr,
@@ -1829,9 +1830,16 @@ void dcn20_prepare_bandwidth(
>bw_ctx.bw.dcn.watermarks,
dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
false);
+
/* decrease compbuf size */
- if (hubbub->funcs->program_compbuf_size)
- hubbub->funcs->program_compbuf_size(hubbub,
context->bw_ctx.bw.dcn.compbuf_size_kb, false);
+ if (hubbub->funcs->program_compbuf_size) {
+ if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes)
+ compbuf_size_kb =
context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
+ else
+ compbuf_size_kb =
context->bw_ctx.bw.dcn.compbuf_size_kb;
+
+ hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb,
false);
+ }
}
void dcn20_optimize_bandwidth(
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 8f9f1d607f7c..59f0a61c33cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -141,6 +141,7 @@ struct _vcs_dpi_ip_params_st {
unsigned int odm_capable;
unsigned int rob_buffer_size_kbytes;
unsigned int det_buffer_size_kbytes;
+ unsigned int min_comp_buffer_size_kbytes;
unsigned int dpte_buffer_size_in_pte_reqs_luma;
unsigned int dpte_buffer_size_in_pte_reqs_chroma;
unsigned int pde_proc_buffer_size_64k_reqs;
--
2.25.1
[PATCH 02/12] drm/amd/display: lock/un-lock cursor if odm pipe split used
From: Paul Hsieh
[Why]
When system resume from sleep, the cursor lock will be reset
to default(lock status). And the cursor programming sequence
doesn't consider about odm pipe split cause cursor can't be
enabled.
[How]
If odm pipe split has been used, lock/un-lock on each pipes.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Solomon Chiu
Signed-off-by: Paul Hsieh
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 263f9891ecbc..dc5fd27b031a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -273,6 +273,8 @@ static void program_cursor_attributes(
if (!pipe_to_program) {
pipe_to_program = pipe_ctx;
dc->hwss.cursor_lock(dc, pipe_to_program, true);
+ if (pipe_to_program->next_odm_pipe)
+ dc->hwss.cursor_lock(dc,
pipe_to_program->next_odm_pipe, true);
}
dc->hwss.set_cursor_attribute(pipe_ctx);
@@ -280,8 +282,11 @@ static void program_cursor_attributes(
dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
}
- if (pipe_to_program)
+ if (pipe_to_program) {
dc->hwss.cursor_lock(dc, pipe_to_program, false);
+ if (pipe_to_program->next_odm_pipe)
+ dc->hwss.cursor_lock(dc,
pipe_to_program->next_odm_pipe, false);
+ }
}
#ifndef TRIM_FSFT
--
2.25.1
[PATCH 01/12] drm/amd/display: OVT Update on InfoFrame and Mode Management
From: Chris Park
[Why]
Integrate OVT timing from DM to DC logic to update info frame
and mode management to report the resolution to the OS.
[How]
Reflect RID and Frame Rate to AVI InfoFrame Version 5.
Define new Timing Standard for OVT timing.
Reviewed-by: Charlene Liu
Acked-by: Solomon Chiu
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c| 11 +++
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 ++
drivers/gpu/drm/amd/display/dc/dc_types.h| 2 ++
drivers/gpu/drm/amd/display/include/set_mode_types.h | 8 ++--
4 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index a2a25d444574..8ee41f00f050 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2443,6 +2443,8 @@ static void set_avi_info_frame(
union hdmi_info_packet hdmi_info;
union display_content_support support = {0};
unsigned int vic = pipe_ctx->stream->timing.vic;
+ unsigned int rid = pipe_ctx->stream->timing.rid;
+ unsigned int fr_ind = pipe_ctx->stream->timing.fr_index;
enum dc_timing_3d_format format;
memset(_info, 0, sizeof(union hdmi_info_packet));
@@ -2633,6 +2635,15 @@ static void set_avi_info_frame(
hdmi_info.bits.header.length = 14;
}
+ if (rid != 0 && fr_ind != 0) {
+ hdmi_info.bits.header.version = 5;
+ hdmi_info.bits.header.length = 15;
+
+ hdmi_info.bits.FR0_FR3 = fr_ind & 0xF;
+ hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1;
+ hdmi_info.bits.RID0_RID5 = rid;
+ }
+
/* pixel repetition
* PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
* repetition start from 1 */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index c964f598755a..46f66527dc21 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -766,6 +766,8 @@ struct dc_crtc_timing {
uint32_t vic;
uint32_t hdmi_vic;
+ uint32_t rid;
+ uint32_t fr_index;
enum dc_timing_3d_format timing_3d_format;
enum dc_color_depth display_color_depth;
enum dc_pixel_encoding pixel_encoding;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 48859d5fc172..30f5f7e73186 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -276,6 +276,8 @@ enum dc_timing_source {
TIMING_SOURCE_EDID_CEA_SVD,
TIMING_SOURCE_EDID_CVT_3BYTE,
TIMING_SOURCE_EDID_4BYTE,
+ TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB,
+ TIMING_SOURCE_EDID_CEA_RID,
TIMING_SOURCE_VBIOS,
TIMING_SOURCE_CV,
TIMING_SOURCE_TV,
diff --git a/drivers/gpu/drm/amd/display/include/set_mode_types.h
b/drivers/gpu/drm/amd/display/include/set_mode_types.h
index 845fea8a387f..75f2c79492c0 100644
--- a/drivers/gpu/drm/amd/display/include/set_mode_types.h
+++ b/drivers/gpu/drm/amd/display/include/set_mode_types.h
@@ -84,10 +84,14 @@ union hdmi_info_packet {
uint16_t bar_left;
uint16_t bar_right;
- uint8_t F140_F143:4;
+ uint8_t FR0_FR3:4;
uint8_t ACE0_ACE3:4;
- uint8_t reserved[13];
+ uint8_t RID0_RID5:6;
+ uint8_t FR4:1;
+ uint8_t F157:1;
+
+ uint8_t reserved[12];
} bits;
struct info_packet_raw_data packet_raw_data;
--
2.25.1
[PATCH 00/12] DC Patches February 21, 2022
This DC patchset brings improvements in multiple areas. In summary, we highlight: * add debug option to bypass ssinfo from bios. * Refactor fixed VS logic for non-transparent mode * add cable ID support for usb c connector * clear remote dc_sink when stop mst * Ignore Transitional Invalid Link Rate Error Message * Fix wrong resolution with DP/VGA adapter * Refactor PSR DPCD caps detection * Set compbuf size to min at prep prevent overbook crb * lock/un-lock cursor if odm pipe split used * OVT Update on InfoFrame and Mode Management Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.105.0 Aric Cyr (1): drm/amd/display: 3.2.174 Charlene Liu (1): drm/amd/display: add debug option to bypass ssinfo from bios. Chris Park (1): drm/amd/display: OVT Update on InfoFrame and Mode Management Fangzhi Zuo (1): drm/amd/display: Ignore Transitional Invalid Link Rate Error Message Ilya (1): drm/amd/display: Fix wrong resolution with DP/VGA adapter Ma, Duncan (1): drm/amd/display: Set compbuf size to min at prep prevent overbook crb Paul Hsieh (1): drm/amd/display: lock/un-lock cursor if odm pipe split used Po Ting Chen (1): drm/amd/display: Refactor PSR DPCD caps detection Shen, George (1): drm/amd/display: Refactor fixed VS logic for non-transparent mode Wayne Lin (1): drm/amd/display: clear remote dc_sink when stop mst Wenjing Liu (1): drm/amd/display: add cable ID support for usb c connector .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 +- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 20 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 58 + .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 2 + .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 2 + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 +- .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 3 + .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 230 +++--- .../gpu/drm/amd/display/dc/core/dc_resource.c | 11 + .../gpu/drm/amd/display/dc/core/dc_stream.c | 7 +- drivers/gpu/drm/amd/display/dc/dc.h | 9 +- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 32 ++- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 + drivers/gpu/drm/amd/display/dc/dc_link.h | 8 +- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 + .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 12 +- .../amd/display/dc/dml/display_mode_structs.h | 1 + .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 +- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 44 +++- .../amd/display/include/ddc_service_types.h | 1 + .../drm/amd/display/include/set_mode_types.h | 8 +- 21 files changed, 369 insertions(+), 113 deletions(-) -- 2.25.1
[PATCH 14/14] drm/amd/display: Fix error in dmesg at boot
From: "Leo (Hanghong) Ma"
[Why]
During DQE's promotion test, error appears in dmesg at boot
on dcn3.1;
[How]
Add NULL pointor check for the pointor to the amdgpu_dm_connector;
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 81bf1e5a64c8..64b9c493dce2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1917,7 +1917,7 @@ void blank_all_dp_displays(struct dc *dc, bool hw_init)
if ((signal == SIGNAL_TYPE_EDP) ||
(signal == SIGNAL_TYPE_DISPLAY_PORT)) {
- if (hw_init && signal != SIGNAL_TYPE_EDP) {
+ if (hw_init && signal != SIGNAL_TYPE_EDP &&
dc->links[i]->priv != NULL) {
/* DP 2.0 spec requires that we read LTTPR caps
first */
dp_retrieve_lttpr_cap(dc->links[i]);
/* if any of the displays are lit up turn them
off */
@@ -1943,7 +1943,7 @@ void blank_all_dp_displays(struct dc *dc, bool hw_init)
}
if
(!dc->links[i]->wa_flags.dp_keep_receiver_powered ||
- (hw_init && signal != SIGNAL_TYPE_EDP))
+ (hw_init && signal != SIGNAL_TYPE_EDP
&& dc->links[i]->priv != NULL))
dp_receiver_power_ctrl(dc->links[i],
false);
}
}
--
2.25.1
[PATCH 13/14] drm/amd/display: Fix concurrent dynamic encoder assignment.
From: Jimmy Kizito
[Why]
Trying to enable multiple displays simultaneously exposed shortcomings
with the algorithm for dynamic link encoder assignment.
The main problems were:
- Assuming stream order remained constant across states would
sometimes lead to invalid DIG encoder assignment.
- Incorrect logic for deciding whether or not a DIG could support a
stream would also sometimes lead to invalid DIG encoder assignment.
- Changes in encoder assignment were wholesale while updating of the
pipe backend is incremental. This would lead to the hardware state
not matching the software state even with valid encoder assignments.
[How]
The following changes fix the identified problems.
- Use stream pointer rather than stream index to track streams across
states.
- Fix DIG compatibility check by examining the link signal type
rather than the stream signal type.
- Modify assignment algorithm to make incremental updates so software
and hardware states remain coherent.
Additionally:
- Add assertions and an encoder assignment validation
function link_enc_cfg_validate() to detect potential problems with
encoder assignment closer to their root cause.
- Reduce the frequency with which the assignment algorithm is
executed. It should not be necessary for fast state validation.
Reviewed-by: Jun Lei
Acked-by: Solomon Chiu
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 74da226efffe..81bf1e5a64c8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1926,9 +1926,9 @@ void blank_all_dp_displays(struct dc *dc, bool hw_init)
}
if ((signal != SIGNAL_TYPE_EDP && status == DC_OK &&
dpcd_power_state == DP_POWER_STATE_D0) ||
- (!hw_init &&
dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc))) {
- if (dc->links[i]->ep_type ==
DISPLAY_ENDPOINT_PHY &&
-
dc->links[i]->link_enc->funcs->get_dig_frontend) {
+ (!hw_init && dc->links[i]->link_enc &&
+
dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc))) {
+ if
(dc->links[i]->link_enc->funcs->get_dig_frontend) {
fe =
dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
if (fe == ENGINE_ID_UNKNOWN)
continue;
--
2.25.1
[PATCH 12/14] drm/amd/display: Add helper for blanking all dp displays
From: "Leo (Hanghong) Ma"
[Why & How]
The codes to blank all dp display have been called many times,
so add a helper in dc_link to make it more concise.
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 45 +++
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
.../display/dc/dce110/dce110_hw_sequencer.c | 24 ++
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 41 ++---
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 39 ++--
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 39 ++--
6 files changed, 59 insertions(+), 130 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 02c7a18c095f..74da226efffe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1906,6 +1906,51 @@ static enum dc_status enable_link_dp_mst(
return enable_link_dp(state, pipe_ctx);
}
+void blank_all_dp_displays(struct dc *dc, bool hw_init)
+{
+ unsigned int i, j, fe;
+ uint8_t dpcd_power_state = '\0';
+ enum dc_status status = DC_ERROR_UNEXPECTED;
+
+ for (i = 0; i < dc->link_count; i++) {
+ enum signal_type signal = dc->links[i]->connector_signal;
+
+ if ((signal == SIGNAL_TYPE_EDP) ||
+ (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
+ if (hw_init && signal != SIGNAL_TYPE_EDP) {
+ /* DP 2.0 spec requires that we read LTTPR caps
first */
+ dp_retrieve_lttpr_cap(dc->links[i]);
+ /* if any of the displays are lit up turn them
off */
+ status = core_link_read_dpcd(dc->links[i],
DP_SET_POWER,
+ _power_state,
sizeof(dpcd_power_state));
+ }
+
+ if ((signal != SIGNAL_TYPE_EDP && status == DC_OK &&
dpcd_power_state == DP_POWER_STATE_D0) ||
+ (!hw_init &&
dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc))) {
+ if (dc->links[i]->ep_type ==
DISPLAY_ENDPOINT_PHY &&
+
dc->links[i]->link_enc->funcs->get_dig_frontend) {
+ fe =
dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
+ if (fe == ENGINE_ID_UNKNOWN)
+ continue;
+
+ for (j = 0; j <
dc->res_pool->stream_enc_count; j++) {
+ if (fe ==
dc->res_pool->stream_enc[j]->id) {
+
dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
+
dc->res_pool->stream_enc[j]);
+ break;
+ }
+ }
+ }
+
+ if
(!dc->links[i]->wa_flags.dp_keep_receiver_powered ||
+ (hw_init && signal != SIGNAL_TYPE_EDP))
+ dp_receiver_power_ctrl(dc->links[i],
false);
+ }
+ }
+ }
+
+}
+
static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
enum engine_id eng_id,
struct ext_hdmi_settings *settings)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index a73d64b1fd33..69b008bafbbc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -277,6 +277,7 @@ bool dc_link_setup_psr(struct dc_link *dc_link,
struct psr_context *psr_context);
void dc_link_get_psr_residency(const struct dc_link *link, uint32_t
*residency);
+void blank_all_dp_displays(struct dc *dc, bool hw_init);
/* Request DC to detect if there is a Panel connected.
* boot - If this call is during initial boot.
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index af3e68d3e747..8108f9ae2638 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1649,31 +1649,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(
static void power_down_encoders(struct dc *dc)
[PATCH 11/14] drm/amd/display: 3.2.156
From: Aric Cyr This version brings along following fixes: - New firmware version - Fix DMUB problems on stress test. - Improve link training by skip overrride for preferred link - Refinement of FPU code structure for DCN2 - Fix 3DLUT skipped programming - Fix detection of 4 lane for DPALT - Fix dcn3 failure due to dmcbu_abm not created - Limit display scaling to up to 4k for DCN 3.1 - Add helper for blanking all dp displays Acked-by: Solomon Chiu Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5ffe2a41258f..204bab6f82ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ /* forward declaration */ struct aux_payload; -#define DC_VER "3.2.155" +#define DC_VER "3.2.156" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.25.1
[PATCH 10/14] drm/amd/display: [FW Promotion] Release 0.0.87
From: Anthony Koo Acked-by: Solomon Chiu Signed-off-by: Anthony Koo --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index f5974562aa23..42956dd398f3 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -47,10 +47,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0x42c0e74b +#define DMUB_FW_VERSION_GIT_HASH 0xf0c64c97 #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 86 +#define DMUB_FW_VERSION_REVISION 87 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 -- 2.25.1
[PATCH 09/14] drm/amd/display: Fix detection of 4 lane for DPALT
From: Hansen
[Why]
DPALT detection for B0 PHY has its own set of RDPCSPIPE registers
[How]
Use RDPCSPIPE registers to detect if DPALT lane is 4 lane
Reviewed-by: Charlene Liu
Acked-by: Solomon Chiu
Signed-off-by: Hansen
---
.../display/dc/dcn31/dcn31_dio_link_encoder.c | 33 ++-
.../display/dc/dcn31/dcn31_dio_link_encoder.h | 3 ++
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
index 4f0a0803db6c..616a48d72afa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
@@ -63,6 +63,10 @@
#define AUX_REG_WRITE(reg_name, val) \
dm_write_reg(CTX, AUX_REG(reg_name), val)
+#ifndef MIN
+#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
+#endif
+
void dcn31_link_encoder_set_dio_phy_mux(
struct link_encoder *enc,
enum encoder_type_select sel,
@@ -217,7 +221,7 @@ static const struct link_encoder_funcs dcn31_link_enc_funcs
= {
.get_dig_frontend = dcn10_get_dig_frontend,
.get_dig_mode = dcn10_get_dig_mode,
.is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,
- .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
+ .get_max_link_cap = dcn31_link_encoder_get_max_link_cap,
.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
};
@@ -439,3 +443,30 @@ bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder
*enc)
return is_usb_c_alt_mode;
}
+
+void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,
+
struct dc_link_settings *link_settings)
+{
+ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+ uint32_t is_in_usb_c_dp4_mode = 0;
+
+ dcn10_link_encoder_get_max_link_cap(enc, link_settings);
+
+ /* in usb c dp2 mode, max lane count is 2 */
+ if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
+ if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
+ // [Note] no need to check hw_internal_rev once phy mux
selection is ready
+ REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4,
_in_usb_c_dp4_mode);
+ } else {
+ if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
+ || (enc10->base.transmitter ==
TRANSMITTER_UNIPHY_B)
+ || (enc10->base.transmitter ==
TRANSMITTER_UNIPHY_E)) {
+ REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4,
_in_usb_c_dp4_mode);
+ } else {
+ REG_GET(RDPCSPIPE_PHY_CNTL6,
RDPCS_PHY_DPALT_DP4, _in_usb_c_dp4_mode);
+ }
+ }
+ if (!is_in_usb_c_dp4_mode)
+ link_settings->lane_count = MIN(LANE_COUNT_TWO,
link_settings->lane_count);
+ }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
index bec50e4402ff..3454f1e7c1f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
@@ -252,4 +252,7 @@ void dcn31_link_encoder_disable_output(
bool dcn31_link_encoder_is_in_alt_mode(
struct link_encoder *enc);
+void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,
+ struct dc_link_settings *link_settings);
+
#endif /* __DC_LINK_ENCODER__DCN31_H__ */
--
2.25.1
[PATCH 08/14] drm/amd/display: Limit display scaling to up to 4k for DCN 3.1
From: Nikola Cornij
[why]
The existing limit was mistakenly bigger than 4k for DCN 3.1
Reviewed-by: Zhan Liu
Acked-by: Solomon Chiu
Signed-off-by: Nikola Cornij
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 613d34bde7dd..d5b58025f0cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -998,7 +998,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
.performance_trace = false,
- .max_downscale_src_width = 7680,/*upto 8K*/
+ .max_downscale_src_width = 3840,/*upto 4K*/
.disable_pplib_wm_range = false,
.scl_reset_length10 = true,
.sanity_checks = false,
--
2.25.1
[PATCH 07/14] drm/amd/display: Added root clock optimization flags
From: Jake Wang
[Why & How]
Added root clock optimization debug flags for future debugging.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
Signed-off-by: Jake Wang
---
drivers/gpu/drm/amd/display/dc/dc.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index c5a091d0bbfc..5ffe2a41258f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -477,6 +477,23 @@ union mem_low_power_enable_options {
uint32_t u32All;
};
+union root_clock_optimization_options {
+ struct {
+ bool dpp: 1;
+ bool dsc: 1;
+ bool hdmistream: 1;
+ bool hdmichar: 1;
+ bool dpstream: 1;
+ bool symclk32_se: 1;
+ bool symclk32_le: 1;
+ bool symclk_fe: 1;
+ bool physymclk: 1;
+ bool dpiasymclk: 1;
+ uint32_t reserved: 22;
+ } bits;
+ uint32_t u32All;
+};
+
struct dc_debug_data {
uint32_t ltFailCount;
uint32_t i2cErrorCount;
@@ -637,6 +654,7 @@ struct dc_debug_options {
bool legacy_dp2_lt;
#endif
union mem_low_power_enable_options enable_mem_low_power;
+ union root_clock_optimization_options root_clock_optimization;
bool force_vblank_alignment;
/* Enable dmub aux for legacy ddc */
--
2.25.1
[PATCH 06/14] drm/amd/display: dcn3 failed due to dmcbu_abm not created
From: Charlene Liu
[why]
dc->config.disable_dmcu set to true, but it still need create
dmcub based abm.
[how]
check to dc->caps.dmcub_support check.
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index 0f273ac0c83f..6ab81d609c97 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -256,7 +256,7 @@ struct abm *dmub_abm_create(
const struct dce_abm_shift *abm_shift,
const struct dce_abm_mask *abm_mask)
{
- if (!ctx->dc->config.disable_dmcu) {
+ if (ctx->dc->caps.dmcub_support) {
struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
if (abm_dce == NULL) {
--
2.25.1
[PATCH 05/14] drm/amd/display: Fix 3DLUT skipped programming
From: Aric Cyr
[Why]
3DLUT not updated due to missing condition
[How]
Check if 3DLUT update is needed
Reviewed-by: Anthony Koo
Acked-by: Solomon Chiu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0f0440408a16..8e0bcd4fd000 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2187,6 +2187,9 @@ static enum surface_update_type det_surface_update(const
struct dc *dc,
update_flags->bits.gamma_change = 1;
}
+ if (u->lut3d_func || u->func_shaper)
+ update_flags->bits.lut_3d = 1;
+
if (u->hdr_mult.value)
if (u->hdr_mult.value != u->surface->hdr_mult.value) {
update_flags->bits.hdr_mult = 1;
@@ -2200,6 +2203,7 @@ static enum surface_update_type det_surface_update(const
struct dc *dc,
if (update_flags->bits.input_csc_change
|| update_flags->bits.coeff_reduction_change
+ || update_flags->bits.lut_3d
|| update_flags->bits.gamma_change
|| update_flags->bits.gamut_remap_change) {
type = UPDATE_TYPE_FULL;
--
2.25.1
[PATCH 04/14] drm/amd/display: Re-arrange FPU code structure for dcn2x
From: Qingqing Zhuo
[Why]
Current FPU code for DCN2x is located under dml/dcn2x.
This is not aligned with DC's general source tree
structure.
[How]
Move FPU code for DCN2x to dml/dcn20.
Reviewed-by: Rodrigo Siqueira
Acked-by: Solomon Chiu
Signed-off-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 ++--
.../amd/display/dc/dml/{dcn2x/dcn2x.c => dcn20/dcn20_fpu.c} | 2 +-
.../amd/display/dc/dml/{dcn2x/dcn2x.h => dcn20/dcn20_fpu.h} | 6 +++---
7 files changed, 10 insertions(+), 10 deletions(-)
rename drivers/gpu/drm/amd/display/dc/dml/{dcn2x/dcn2x.c => dcn20/dcn20_fpu.c}
(99%)
rename drivers/gpu/drm/amd/display/dc/dml/{dcn2x/dcn2x.h => dcn20/dcn20_fpu.h}
(94%)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
index b1bf80da3a55..ab0c6d191038 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
@@ -52,7 +52,7 @@ static DEFINE_PER_CPU(int, fpu_recursion_depth);
* This function tells if the code is already under FPU protection or not. A
* function that works as an API for a set of FPU operations can use this
* function for checking if the caller invoked it after DC_FP_START(). For
- * example, take a look at dcn2x.c file.
+ * example, take a look at dcn20_fpu.c file.
*/
inline void dc_assert_fp_enabled(void)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 899d0086ffbe..756f5d411d9a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -35,7 +35,7 @@
#include "include/irq_service_interface.h"
#include "dcn20/dcn20_resource.h"
-#include "dml/dcn2x/dcn2x.h"
+#include "dml/dcn20/dcn20_fpu.h"
#include "dcn10/dcn10_hubp.h"
#include "dcn10/dcn10_ipp.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
index aec276e1db65..5881dc49f7c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
@@ -27,7 +27,7 @@
#include "dc.h"
#include "dcn201_init.h"
-#include "dml/dcn2x/dcn2x.h"
+#include "dml/dcn20/dcn20_fpu.h"
#include "resource.h"
#include "include/irq_service_interface.h"
#include "dcn201_resource.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index fbbdf9976183..d452a0d1777e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -35,7 +35,7 @@
#include "include/irq_service_interface.h"
#include "dcn20/dcn20_resource.h"
-#include "dml/dcn2x/dcn2x.h"
+#include "dml/dcn20/dcn20_fpu.h"
#include "clk_mgr.h"
#include "dcn10/dcn10_hubp.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile
b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index 56055df2e8d2..169a4e68f86e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -58,7 +58,7 @@ CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o :=
$(dml_ccflags)
ifdef CONFIG_DRM_AMD_DC_DCN
CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
-CFLAGS_$(AMDDALPATH)/dc/dml/dcn2x/dcn2x.o := $(dml_ccflags)
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
@@ -93,8 +93,8 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o
:= $(dml_rcflags)
DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
ifdef CONFIG_DRM_AMD_DC_DCN
+DML += dcn20/dcn20_fpu.o
DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o
dcn20/display_mode_vba_20.o
-DML += dcn2x/dcn2x.o
DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
DML += dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn2x/dcn2x.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
similarity index 99%
rename from drivers/gpu/drm/amd/display/dc/dml/dcn2x/dcn2x.c
rename to drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20
[PATCH 03/14] drm/amd/display: Skip override for preferred link settings during link training
From: George Shen
[Why]
Overriding link setting inside override_training_settings
result in fallback link settings being ignored. This can
potentially cause link training to always fail and consequently
result in an infinite loop of link training to occur in
dp_verify_link_cap during detection.
[How]
Since preferred link settings are already considered inside
decide_link_settings, skip the check in override_training_settings
to avoid infinite link training loops.
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 029cc78bc9e9..649a9da338a7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1645,12 +1645,6 @@ static void override_training_settings(
{
uint32_t lane;
- /* Override link settings */
- if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
- lt_settings->link_settings.link_rate =
link->preferred_link_setting.link_rate;
- if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
- lt_settings->link_settings.lane_count =
link->preferred_link_setting.lane_count;
-
/* Override link spread */
if (!link->dp_ss_off && overrides->downspread != NULL)
lt_settings->link_settings.link_spread = *overrides->downspread
?
--
2.25.1
[PATCH 02/14] drm/amd/display: update irq_service and other required change part 2.
From: Charlene Liu
[why]
fix NULL pointer in irq_service_dcn201
[how]
initialize proper num of irq source for linu
Reviewed-by: Sung joon Kim
Acked-by: Solomon Chiu
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dc.h| 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 9 +
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 17 ++---
4 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 8cc9626fc111..c5a091d0bbfc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -899,6 +899,7 @@ union surface_update_flags {
uint32_t bandwidth_change:1;
uint32_t clock_change:1;
uint32_t stereo_format_change:1;
+ uint32_t lut_3d:1;
uint32_t full_update:1;
} bits;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 296b2f80a1ec..307369b52b42 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -663,14 +663,15 @@ struct dce_hwseq_registers {
uint32_t MC_VM_XGMI_LFB_CNTL;
uint32_t AZALIA_AUDIO_DTO;
uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
+ /* MMHUB VM */
+ uint32_t MC_VM_FB_LOCATION_BASE;
+ uint32_t MC_VM_FB_LOCATION_TOP;
+ uint32_t MC_VM_FB_OFFSET;
+ uint32_t MMHUBBUB_MEM_PWR_CNTL;
uint32_t HPO_TOP_CLOCK_CONTROL;
uint32_t ODM_MEM_PWR_CTRL3;
uint32_t DMU_MEM_PWR_CNTL;
- uint32_t MMHUBBUB_MEM_PWR_CNTL;
uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
- uint32_t MC_VM_FB_LOCATION_BASE;
- uint32_t MC_VM_FB_LOCATION_TOP;
- uint32_t MC_VM_FB_OFFSET;
};
/* set field name */
#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
index bf1ffc3629c7..3d9be87aae45 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
@@ -111,6 +111,7 @@ enum dce110_opp_reg_type {
OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
+ OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index fb0dec4ed3a6..0f273ac0c83f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -256,16 +256,19 @@ struct abm *dmub_abm_create(
const struct dce_abm_shift *abm_shift,
const struct dce_abm_mask *abm_mask)
{
- struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
+ if (!ctx->dc->config.disable_dmcu) {
+ struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
- if (abm_dce == NULL) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
+ if (abm_dce == NULL) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
- dmub_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask);
+ dmub_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask);
- return _dce->base;
+ return _dce->base;
+ }
+ return NULL;
}
void dmub_abm_destroy(struct abm **abm)
--
2.25.1
[PATCH 01/14] drm/amd/display: Prevent using DMUB rptr that is out-of-bounds
From: Wyatt Wood
[Why]
Running into bugchecks during stress test where rptr is 0x.
Typically this is caused by a hard hang, and can come from HW outside
of DCN.
[How]
To prevent bugchecks when writing the DMUB rptr, fist check that the
rptr is valid.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
Signed-off-by: Wyatt Wood
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 10 --
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index ef324fc39315..efb667cf6c98 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -84,6 +84,7 @@ enum dmub_status {
DMUB_STATUS_QUEUE_FULL,
DMUB_STATUS_TIMEOUT,
DMUB_STATUS_INVALID,
+ DMUB_STATUS_HW_FAILURE,
};
/* enum dmub_asic - dmub asic identifier */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index a6188d067d65..77c67222cabd 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -655,13 +655,19 @@ enum dmub_status dmub_srv_wait_for_phy_init(struct
dmub_srv *dmub,
enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
uint32_t timeout_us)
{
- uint32_t i;
+ uint32_t i, rptr;
if (!dmub->hw_init)
return DMUB_STATUS_INVALID;
for (i = 0; i <= timeout_us; ++i) {
- dmub->inbox1_rb.rptr =
dmub->hw_funcs.get_inbox1_rptr(dmub);
+ rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
+
+ if (rptr > dmub->inbox1_rb.capacity)
+ return DMUB_STATUS_HW_FAILURE;
+
+ dmub->inbox1_rb.rptr = rptr;
+
if (dmub_rb_empty(>inbox1_rb))
return DMUB_STATUS_OK;
--
2.25.1
[PATCH 00/14] DC Patches October 1, 2021
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- New firmware version
- Fix DMUB problems on stress test.
- Improve link training by skip overrride for preferred link
- Refinement of FPU code structure for DCN2
- Fix 3DLUT skipped programming
- Fix detection of 4 lane for DPALT
- Fix dcn3 failure due to dmcbu_abm not created
- Limit display scaling to up to 4k for DCN 3.1
- Add helper for blanking all dp displays
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.87
Aric Cyr (2):
drm/amd/display: Fix 3DLUT skipped programming
drm/amd/display: 3.2.156
Charlene Liu (2):
drm/amd/display: update irq_service and other required change part 2.
drm/amd/display: dcn3 failed due to dmcbu_abm not created
George Shen (1):
drm/amd/display: Skip override for preferred link settings during link
training
Hansen (1):
drm/amd/display: Fix detection of 4 lane for DPALT
Jake Wang (1):
drm/amd/display: Added root clock optimization flags
Jimmy Kizito (1):
drm/amd/display: Fix concurrent dynamic encoder assignment.
Leo (Hanghong) Ma (2):
drm/amd/display: Add helper for blanking all dp displays
drm/amd/display: Fix error in dmesg at boot
Nikola Cornij (1):
drm/amd/display: Limit display scaling to up to 4k for DCN 3.1
Qingqing Zhuo (1):
drm/amd/display: Re-arrange FPU code structure for dcn2x
Wyatt Wood (1):
drm/amd/display: Prevent using DMUB rptr that is out-of-bounds
.../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c| 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 45 +++
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 6 ---
drivers/gpu/drm/amd/display/dc/dc.h | 21 -
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 9 ++--
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 17 ---
.../display/dc/dce110/dce110_hw_sequencer.c | 24 ++
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 41 ++---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
.../amd/display/dc/dcn201/dcn201_resource.c | 2 +-
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 39 ++--
.../display/dc/dcn31/dcn31_dio_link_encoder.c | 33 +-
.../display/dc/dcn31/dcn31_dio_link_encoder.h | 3 ++
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 39 ++--
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 +-
.../dml/{dcn2x/dcn2x.c => dcn20/dcn20_fpu.c} | 2 +-
.../dml/{dcn2x/dcn2x.h => dcn20/dcn20_fpu.h} | 6 +--
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +-
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 10 -
25 files changed, 156 insertions(+), 164 deletions(-)
rename drivers/gpu/drm/amd/display/dc/dml/{dcn2x/dcn2x.c => dcn20/dcn20_fpu.c}
(99%)
rename drivers/gpu/drm/amd/display/dc/dml/{dcn2x/dcn2x.h => dcn20/dcn20_fpu.h}
(94%)
--
2.25.1
[PATCH 12/14] drm/amd/display: ensure dentist display clock update finished in DCN20
From: Dale Zhao [Why] We don't check DENTIST_DISPCLK_CHG_DONE to ensure dentist display clockis updated to target value. In some scenarios with large display clock margin, it will deliver unfinished display clock and cause issues like display black screen. [How] Checking DENTIST_DISPCLK_CHG_DONE to ensure display clock has been update to target value before driver do other clock related actions. Reviewed-by: Cyr Aric Acked-by: Solomon Chiu Signed-off-by: Dale Zhao --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index eee406d11b1e..0d01aa9f15a6 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -197,7 +197,7 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); -// REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100); + REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 1000); REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/14] drm/amd/display: [FW Promotion] Release 0.0.76
From: Anthony Koo Reviewed-by: Cyr Aric Acked-by: Solomon Chiu Signed-off-by: Anthony Koo --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 8b0b4d86986c..02921ad22310 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -47,10 +47,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0x2d2f6f51e +#define DMUB_FW_VERSION_GIT_HASH 0xe599e0896 #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 75 +#define DMUB_FW_VERSION_REVISION 76 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/14] drm/amd/display: refactor riommu invalidation wa
From: Eric Yang
[Why]
A cleaner solution, only done once on boot.
[How]
Remove previous workaround and configure an extra
vmid one time on boot
Reviewed-by: Kazlauskas Nicholas
Acked-by: Solomon Chiu
Signed-off-by: Eric Yang
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 6 ---
.../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 48 +++
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 17 ---
.../gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 2 +-
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 1 -
.../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 3 --
.../amd/display/dc/inc/hw_sequencer_private.h | 1 -
7 files changed, 28 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index ef185b93b31d..5c2853654cca 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -570,12 +570,6 @@ void dcn20_plane_atomic_disable(struct dc *dc, struct
pipe_ctx *pipe_ctx)
struct hubp *hubp = pipe_ctx->plane_res.hubp;
struct dpp *dpp = pipe_ctx->plane_res.dpp;
- if (hws->wa.early_riommu_invalidation) {
- struct hubbub *hubbub = dc->res_pool->hubbub;
-
- hubbub->funcs->apply_invalidation_req_wa(hubbub,
>vmid_cache);
- }
-
dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
/* In flip immediate with pipe splitting case GSL is used for
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
index ef233cb49b31..90c73a1cb986 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
@@ -876,11 +876,35 @@ static bool hubbub31_get_dcc_compression_cap(struct
hubbub *hubbub,
static int hubbub31_init_dchub_sys_ctx(struct hubbub *hubbub,
struct dcn_hubbub_phys_addr_config *pa_config)
{
- hubbub3_init_dchub_sys_ctx(hubbub, pa_config);
+ struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+ struct dcn_vmid_page_table_config phys_config;
- dcn21_dchvm_init(hubbub);
+ REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
+ FB_BASE, pa_config->system_aperture.fb_base >> 24);
+ REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
+ FB_TOP, pa_config->system_aperture.fb_top >> 24);
+ REG_SET(DCN_VM_FB_OFFSET, 0,
+ FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
+ REG_SET(DCN_VM_AGP_BOT, 0,
+ AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
+ REG_SET(DCN_VM_AGP_TOP, 0,
+ AGP_TOP, pa_config->system_aperture.agp_top >> 24);
+ REG_SET(DCN_VM_AGP_BASE, 0,
+ AGP_BASE, pa_config->system_aperture.agp_base >> 24);
- hubbub->vmid_cache = *pa_config;
+ if (pa_config->gart_config.page_table_start_addr !=
pa_config->gart_config.page_table_end_addr) {
+ phys_config.page_table_start_addr =
pa_config->gart_config.page_table_start_addr >> 12;
+ phys_config.page_table_end_addr =
pa_config->gart_config.page_table_end_addr >> 12;
+ phys_config.page_table_base_addr =
pa_config->gart_config.page_table_base_addr;
+ phys_config.depth = 0;
+ phys_config.block_size = 0;
+ // Init VMID 0 based on PA config
+ dcn20_vmid_setup(>vmid[0], _config);
+
+ dcn20_vmid_setup(>vmid[15], _config);
+ }
+
+ dcn21_dchvm_init(hubbub);
return NUM_VMID;
}
@@ -922,23 +946,6 @@ static void hubbub31_get_dchub_ref_freq(struct hubbub
*hubbub,
}
}
-static void hubbub31_apply_invalidation_req_wa(struct hubbub *hubbub,
- struct dcn_hubbub_phys_addr_config *pa_config)
-{
- struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
- struct dcn_vmid_page_table_config phys_config;
-
- if (pa_config->gart_config.page_table_start_addr !=
pa_config->gart_config.page_table_end_addr) {
- phys_config.page_table_start_addr =
pa_config->gart_config.page_table_start_addr >> 12;
- phys_config.page_table_end_addr =
pa_config->gart_config.page_table_end_addr >> 12;
- phys_config.page_table_base_addr =
pa_config->gart_config.page_table_base_addr;
- phys_config.depth = 0;
- phys_config.block_size = 0;
- // Program an arbitrary unused VMID
- dcn20_vmid_setup(>vmid[15], _config);
- }
-}
-
static const struct hubbub_funcs hubbub31_funcs = {
.update_dchub = hubbub2_update_dchub,
.init_dchub_sys_ctx = hubbub31_init_dchub_sys_ctx,
@@ -955,7 +962,6
[PATCH 10/14] drm/amd/display: Always wait for update lock status
From: Eric Bernstein Remove code that would skip wait for lock status for Diags FPGA case Reviewed-by: Laktyushkin Dmytro Acked-by: Solomon Chiu Signed-off-by: Eric Bernstein --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c index f37e8254df21..089be7347591 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c @@ -109,11 +109,9 @@ void optc3_lock(struct timing_generator *optc) REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK, 1); - /* Should be fast, status does not update on maximus */ - if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) - REG_WAIT(OTG_MASTER_UPDATE_LOCK, - UPDATE_LOCK_STATUS, 1, - 1, 10); + REG_WAIT(OTG_MASTER_UPDATE_LOCK, + UPDATE_LOCK_STATUS, 1, + 1, 10); } void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/14] drm/amd/display: 3.2.146
From: Aric Cyr This version brings along following fixed: - Guard DST_Y_PREFETCH register overflow in DCN21 - Add missing DCN21 IP parameter - Fix PSR command version - Add ETW logging for AUX failures - Add ETW log to dmub_psr_get_state - Fixed EdidUtility build errors - Fix missing reg offset for the dmcub test debug registers - Adding update authentication interface - Remove unused functions of opm state query support - Always wait for update lock status - Refactor riommu invalidation wa - Ensure dentist display clock update finished in DCN20 Reviewed-by: Hsieh Mike Acked-by: Solomon Chiu Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 2f3810f0510c..a948f4f48935 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ /* forward declaration */ struct aux_payload; -#define DC_VER "3.2.145" +#define DC_VER "3.2.146" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 08/14] drm/amd/display: add update authentication interface
From: Wenjing Liu
[why]
Previously to toggle authentication, we need to remove and
add the same display back with modified adjustment.
This method will toggle DTM state without actual hardware changes.
This is not per design and would cause potential issues in the long run.
[how]
We are creating a dedicated interface that does the same thing as
remove and add back the display without changing DTM state.
Acked-by: Solomon Chiu
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/modules/hdcp/hdcp.c | 64 +--
.../drm/amd/display/modules/inc/mod_hdcp.h| 11 +++-
2 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
index b963226e8af4..2bcab9c9b96e 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
@@ -39,8 +39,12 @@ static void push_error_status(struct mod_hdcp *hdcp,
if (is_hdcp1(hdcp)) {
hdcp->connection.hdcp1_retry_count++;
+ if (hdcp->connection.hdcp1_retry_count == MAX_NUM_OF_ATTEMPTS)
+ hdcp->connection.link.adjust.hdcp1.disable = 1;
} else if (is_hdcp2(hdcp)) {
hdcp->connection.hdcp2_retry_count++;
+ if (hdcp->connection.hdcp2_retry_count == MAX_NUM_OF_ATTEMPTS)
+ hdcp->connection.link.adjust.hdcp2.disable = 1;
}
}
@@ -59,8 +63,7 @@ static uint8_t is_cp_desired_hdcp1(struct mod_hdcp *hdcp)
}
}
- return (hdcp->connection.hdcp1_retry_count < MAX_NUM_OF_ATTEMPTS) &&
- is_auth_needed &&
+ return is_auth_needed &&
!hdcp->connection.link.adjust.hdcp1.disable &&
!hdcp->connection.is_hdcp1_revoked;
}
@@ -80,8 +83,7 @@ static uint8_t is_cp_desired_hdcp2(struct mod_hdcp *hdcp)
}
}
- return (hdcp->connection.hdcp2_retry_count < MAX_NUM_OF_ATTEMPTS) &&
- is_auth_needed &&
+ return is_auth_needed &&
!hdcp->connection.link.adjust.hdcp2.disable &&
!hdcp->connection.is_hdcp2_revoked;
}
@@ -392,6 +394,60 @@ enum mod_hdcp_status mod_hdcp_remove_display(struct
mod_hdcp *hdcp,
return status;
}
+enum mod_hdcp_status mod_hdcp_update_authentication(struct mod_hdcp *hdcp,
+ uint8_t index,
+ struct mod_hdcp_link_adjustment *link_adjust,
+ struct mod_hdcp_display_adjustment *display_adjust,
+ struct mod_hdcp_output *output)
+{
+ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
+ struct mod_hdcp_display *display = NULL;
+
+ HDCP_TOP_INTERFACE_TRACE_WITH_INDEX(hdcp, index);
+ memset(output, 0, sizeof(struct mod_hdcp_output));
+
+ /* find display in connection */
+ display = get_active_display_at_index(hdcp, index);
+ if (!display) {
+ status = MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;
+ goto out;
+ }
+
+ /* skip if no changes */
+ if (memcmp(link_adjust, >connection.link.adjust,
+ sizeof(struct mod_hdcp_link_adjustment)) == 0 &&
+ memcmp(display_adjust, >adjust,
+ sizeof(struct
mod_hdcp_display_adjustment)) == 0) {
+ status = MOD_HDCP_STATUS_SUCCESS;
+ goto out;
+ }
+
+ /* stop current authentication */
+ status = reset_authentication(hdcp, output);
+ if (status != MOD_HDCP_STATUS_SUCCESS)
+ goto out;
+
+ /* clear retry counters */
+ reset_retry_counts(hdcp);
+
+ /* reset error trace */
+ memset(>connection.trace, 0, sizeof(hdcp->connection.trace));
+
+ /* set new adjustment */
+ hdcp->connection.link.adjust = *link_adjust;
+ display->adjust = *display_adjust;
+
+ /* request authentication when connection is not reset */
+ if (current_state(hdcp) != HDCP_UNINITIALIZED)
+ /* wait 100ms to debounce simultaneous updates for different
indices */
+ callback_in_ms(100, output);
+
+out:
+ if (status != MOD_HDCP_STATUS_SUCCESS)
+ push_error_status(hdcp, status);
+ return status;
+}
+
enum mod_hdcp_status mod_hdcp_query_display(struct mod_hdcp *hdcp,
uint8_t index, struct mod_hdcp_display_query *query)
{
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
index c590493fd293..c1b485f5fb71 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
@@ -282,15 +282,22 @@ enum mod_hdcp_status mod_hdcp_setup(struct mod
[PATCH 09/14] drm/amd/display: remove unused functions
From: Wenjing Liu
[why]
It has been decided that opm state query support will be dropped.
Therefore link encryption enabled and save current encryption states
won't be used anymore and there are no foreseeable usages in the future.
We will remove these two interfaces for clean up.
Acked-by: Solomon Chiu
Signed-off-by: Wenjing Liu
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 4 +-
.../gpu/drm/amd/display/modules/hdcp/hdcp.c | 6 ---
.../gpu/drm/amd/display/modules/hdcp/hdcp.h | 2 -
.../display/modules/hdcp/hdcp1_execution.c| 6 ---
.../display/modules/hdcp/hdcp2_execution.c| 3 --
.../drm/amd/display/modules/hdcp/hdcp_psp.c | 53 ---
.../drm/amd/display/modules/inc/mod_hdcp.h| 1 -
7 files changed, 22 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index e63c6885c757..8e39e9245d06 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -655,10 +655,8 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct
amdgpu_device *adev, struct
INIT_DELAYED_WORK(_work[i].property_validate_dwork,
event_property_validate);
hdcp_work[i].hdcp.config.psp.handle = >psp;
- if (dc->ctx->dce_version == DCN_VERSION_3_1) {
+ if (dc->ctx->dce_version == DCN_VERSION_3_1)
hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1;
-
hdcp_work[i].hdcp.config.psp.caps.opm_state_query_supported = false;
- }
hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc,
i);
hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c;
hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c;
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
index 2bcab9c9b96e..06d60f031a06 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
@@ -315,9 +315,6 @@ enum mod_hdcp_status mod_hdcp_add_display(struct mod_hdcp
*hdcp,
goto out;
}
- /* save current encryption states to restore after next authentication
*/
- mod_hdcp_save_current_encryption_states(hdcp);
-
/* reset existing authentication status */
status = reset_authentication(hdcp, output);
if (status != MOD_HDCP_STATUS_SUCCESS)
@@ -364,9 +361,6 @@ enum mod_hdcp_status mod_hdcp_remove_display(struct
mod_hdcp *hdcp,
goto out;
}
- /* save current encryption states to restore after next authentication
*/
- mod_hdcp_save_current_encryption_states(hdcp);
-
/* stop current authentication */
status = reset_authentication(hdcp, output);
if (status != MOD_HDCP_STATUS_SUCCESS)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
index 3ce91db560d1..7123f0915706 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
@@ -331,8 +331,6 @@ enum mod_hdcp_status mod_hdcp_add_display_to_topology(
struct mod_hdcp *hdcp, struct mod_hdcp_display *display);
enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
struct mod_hdcp *hdcp, uint8_t index);
-bool mod_hdcp_is_link_encryption_enabled(struct mod_hdcp *hdcp);
-void mod_hdcp_save_current_encryption_states(struct mod_hdcp *hdcp);
enum mod_hdcp_status mod_hdcp_hdcp1_create_session(struct mod_hdcp *hdcp);
enum mod_hdcp_status mod_hdcp_hdcp1_destroy_session(struct mod_hdcp *hdcp);
enum mod_hdcp_status mod_hdcp_hdcp1_validate_rx(struct mod_hdcp *hdcp);
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
index de872e7958b0..6ec918af3bff 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
@@ -266,9 +266,6 @@ static enum mod_hdcp_status authenticated(struct mod_hdcp
*hdcp,
mod_hdcp_execute_and_set(mod_hdcp_hdcp1_link_maintenance,
>link_maintenance, ,
hdcp, "link_maintenance");
-
- if (status != MOD_HDCP_STATUS_SUCCESS)
- mod_hdcp_save_current_encryption_states(hdcp);
out:
return status;
}
@@ -447,9 +444,6 @@ static enum mod_hdcp_status authenticated_dp(struct
mod_hdcp *hdcp,
mod_hdcp_execute_and_set(check_no_reauthentication_request_dp,
>reauth_request_check, ,
hdcp, "reauth_request_check");
-
- if (status != MOD_HDCP_STATUS_SUCCESS)
- mod_hdcp_save_current_encryption_states(hd
[PATCH 07/14] drm/amd/display: fix missing reg offset
From: Eric Yang
[Why]
Initializing was missing reg offsets for the dmcub test debug registers
causing assert
[How]
Add initialization
Reviewed-by: Kazlauskas Nicholas
Acked-by: Solomon Chiu
Signed-off-by: Eric Yang
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
index c3ead13f4e2b..61446170056e 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
@@ -38,7 +38,10 @@
const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs = {
#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
- { DMUB_DCN31_REGS() },
+ {
+ DMUB_DCN31_REGS()
+ DMCUB_INTERNAL_REGS()
+ },
#undef DMUB_SR
#define DMUB_SF(reg, field) FD_MASK(reg, field),
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/14] drm/amd/display: Add ETW logging for AUX failures
From: Wyatt Wood
[Why]
Would like to identify the cause of AUX transactions failing
via ETW logs.
[How]
Add ETW logging for AUX failures.
Reviewed-by: Pavic Josip
Acked-by: Solomon Chiu
Signed-off-by: Wyatt Wood
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 2fb88e54a4bf..058a9356a39a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -71,6 +71,8 @@ enum {
#define DEFAULT_AUX_ENGINE_MULT 0
#define DEFAULT_AUX_ENGINE_LENGTH 69
+#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
+
static void release_engine(
struct dce_aux *engine)
{
@@ -743,5 +745,11 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
fail:
if (!payload_reply)
payload->reply = NULL;
+
+ DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+ WPP_BIT_FLAG_DC_ERROR,
+ "AUX transaction failed. Result: %d",
+ operation_result);
+
return false;
}
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 06/14] drm/amd/display: Fixed EdidUtility build errors
From: Mark Morra
[HOW]
Added #ifdefs and refactored various parts of dc to
allow dc_link to be built by AMD EDID UTILITY
[WHY]
dc_dsc was refactored moving some of the code that AMD EDID UTILITY needed
to dc_link, so now dc_link needs to be included by AMD EDID UTILITY
Reviewed-by: Leung Martin
Acked-by: Solomon Chiu
Signed-off-by: Mark Morra
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 108 +++--
drivers/gpu/drm/amd/display/dc/dc.h | 118 +++---
drivers/gpu/drm/amd/display/dc/dc_types.h | 81 ++--
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 393 ++
4 files changed, 380 insertions(+), 320 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index f68a0d9543f4..5be9d6c70ea6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3517,61 +3517,6 @@ void dc_link_enable_hpd_filter(struct dc_link *link,
bool enable)
}
}
-uint32_t dc_bandwidth_in_kbps_from_timing(
- const struct dc_crtc_timing *timing)
-{
- uint32_t bits_per_channel = 0;
- uint32_t kbps;
-
-#if defined(CONFIG_DRM_AMD_DC_DCN)
- if (timing->flags.DSC)
- return dc_dsc_stream_bandwidth_in_kbps(timing,
- timing->dsc_cfg.bits_per_pixel,
- timing->dsc_cfg.num_slices_h,
- timing->dsc_cfg.is_dp);
-#endif
-
- switch (timing->display_color_depth) {
- case COLOR_DEPTH_666:
- bits_per_channel = 6;
- break;
- case COLOR_DEPTH_888:
- bits_per_channel = 8;
- break;
- case COLOR_DEPTH_101010:
- bits_per_channel = 10;
- break;
- case COLOR_DEPTH_121212:
- bits_per_channel = 12;
- break;
- case COLOR_DEPTH_141414:
- bits_per_channel = 14;
- break;
- case COLOR_DEPTH_161616:
- bits_per_channel = 16;
- break;
- default:
- ASSERT(bits_per_channel != 0);
- bits_per_channel = 8;
- break;
- }
-
- kbps = timing->pix_clk_100hz / 10;
- kbps *= bits_per_channel;
-
- if (timing->flags.Y_ONLY != 1) {
- /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
- kbps *= 3;
- if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
- kbps /= 2;
- else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
- kbps = kbps * 2 / 3;
- }
-
- return kbps;
-
-}
-
void dc_link_set_drive_settings(struct dc *dc,
struct link_training_settings *lt_settings,
const struct dc_link *link)
@@ -3777,3 +3722,56 @@ bool dc_link_should_enable_fec(const struct dc_link
*link)
return ret;
}
+
+uint32_t dc_bandwidth_in_kbps_from_timing(
+ const struct dc_crtc_timing *timing)
+{
+ uint32_t bits_per_channel = 0;
+ uint32_t kbps;
+
+ if (timing->flags.DSC)
+ return dc_dsc_stream_bandwidth_in_kbps(timing,
+ timing->dsc_cfg.bits_per_pixel,
+ timing->dsc_cfg.num_slices_h,
+ timing->dsc_cfg.is_dp);
+
+ switch (timing->display_color_depth) {
+ case COLOR_DEPTH_666:
+ bits_per_channel = 6;
+ break;
+ case COLOR_DEPTH_888:
+ bits_per_channel = 8;
+ break;
+ case COLOR_DEPTH_101010:
+ bits_per_channel = 10;
+ break;
+ case COLOR_DEPTH_121212:
+ bits_per_channel = 12;
+ break;
+ case COLOR_DEPTH_141414:
+ bits_per_channel = 14;
+ break;
+ case COLOR_DEPTH_161616:
+ bits_per_channel = 16;
+ break;
+ default:
+ ASSERT(bits_per_channel != 0);
+ bits_per_channel = 8;
+ break;
+ }
+
+ kbps = timing->pix_clk_100hz / 10;
+ kbps *= bits_per_channel;
+
+ if (timing->flags.Y_ONLY != 1) {
+ /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
+ kbps *= 3;
+ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
+ kbps /= 2;
+ else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ kbps = kbps * 2 / 3;
+ }
+
+ return kbps;
+
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 3f2a0f1807d2..2f3810f0510c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -458,7 +458,65 @@ union
[PATCH 05/14] drm/amd/display: Add ETW log to dmub_psr_get_state
From: Wyatt Wood
[Why]
GPINT commands have the lowest priority in DMCUB, so it's possible
that the command isn't processed in time.
[How]
Add a log to help identify this case.
Reviewed-by: Koo Anthony
Acked-by: Solomon Chiu
Signed-off-by: Wyatt Wood
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 3428334c6c57..1ca8b1d94bc2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -29,6 +29,8 @@
#include "dmub/dmub_srv.h"
#include "core_types.h"
+#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
+
#define MAX_PIPES 6
/*
@@ -96,10 +98,19 @@ static void dmub_psr_get_state(struct dmub_psr *dmub, enum
dc_psr_state *state,
// Return invalid state when GPINT times out
*state = PSR_STATE_INVALID;
- // Assert if max retry hit
- if (retry_count >= 1000)
- ASSERT(0);
} while (++retry_count <= 1000 && *state == PSR_STATE_INVALID);
+
+ // Assert if max retry hit
+ if (retry_count >= 1000 && *state == PSR_STATE_INVALID) {
+ ASSERT(0);
+ DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+ WPP_BIT_FLAG_Firmware_PsrState,
+ "Unable to get PSR state from FW.");
+ } else
+ DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE,
+ WPP_BIT_FLAG_Firmware_PsrState,
+ "Got PSR state from FW. PSR state: %d, Retry
count: %d",
+ *state, retry_count);
}
/*
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 03/14] drm/amd/display: Fix PSR command version
From: Mikita Lipski [why] For dual eDP when setting the new settings we need to set command version to DMUB_CMD_PSR_CONTROL_VERSION_1, otherwise DMUB will not read panel_inst parameter. [how] Instead of PSR_VERSION_1 pass DMUB_CMD_PSR_CONTROL_VERSION_1 Reviewed-by: Wood Wyatt Acked-by: Solomon Chiu Signed-off-by: Mikita Lipski --- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 10d42ae0cffe..3428334c6c57 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -207,7 +207,7 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_ cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL; cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data); cmd.psr_set_level.psr_set_level_data.psr_level = psr_level; - cmd.psr_set_level.psr_set_level_data.cmd_version = PSR_VERSION_1; + cmd.psr_set_level.psr_set_level_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst; dc_dmub_srv_cmd_queue(dc->dmub_srv, ); dc_dmub_srv_cmd_execute(dc->dmub_srv); @@ -293,7 +293,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled); copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; - copy_settings_data->cmd_version = PSR_VERSION_1; + copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; copy_settings_data->panel_inst = panel_inst; dc_dmub_srv_cmd_queue(dc->dmub_srv, ); -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 01/14] drm/amd/display: Guard DST_Y_PREFETCH register overflow in DCN21
From: Victor Lu
[why]
DST_Y_PREFETCH can overflow when DestinationLinesForPrefetch values are
too large due to the former being limited to 8 bits.
[how]
Set the maximum value of DestinationLinesForPrefetch to be 255 * refclk
period.
Reviewed-by: Laktyushkin Dmytro
Acked-by: Solomon Chiu
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index 506797c721ed..4136eb8256cb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -841,6 +841,9 @@ static bool CalculatePrefetchSchedule(
else
*DestinationLinesForPrefetch = dst_y_prefetch_equ;
+ // Limit to prevent overflow in DST_Y_PREFETCH register
+ *DestinationLinesForPrefetch = dml_min(*DestinationLinesForPrefetch,
63.75);
+
dml_print("DML: VStartup: %d\n", VStartup);
dml_print("DML: TCalc: %f\n", TCalc);
dml_print("DML: TWait: %f\n", TWait);
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 02/14] drm/amd/display: Add missing DCN21 IP parameter
From: Victor Lu
[why]
IP parameter min_meta_chunk_size_bytes is read for bandwidth
calculations but it was never defined.
[how]
Define min_meta_chunk_size_bytes and initialize value to 256.
Reviewed-by: Laktyushkin Dmytro
Acked-by: Solomon Chiu
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index a5dd97a2c5a3..f27fc2acac57 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -109,6 +109,7 @@ struct _vcs_dpi_ip_params_st dcn2_1_ip = {
.max_page_table_levels = 4,
.pte_chunk_size_kbytes = 2,
.meta_chunk_size_kbytes = 2,
+ .min_meta_chunk_size_bytes = 256,
.writeback_chunk_size_kbytes = 2,
.line_buffer_size_bits = 789504,
.is_line_buffer_bpp_fixed = 0,
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/14] DC Patches July 26, 2021
This DC patchset brings improvements in multiple areas. In summary, we highlight: * Guard DST_Y_PREFETCH register overflow in DCN21 * Add missing DCN21 IP parameter * Fix PSR command version * Add ETW logging for AUX failures * Add ETW log to dmub_psr_get_state * Fixed EdidUtility build errors * Fix missing reg offset for the dmcub test debug registers * Adding update authentication interface * Remove unused functions of opm state query support * Always wait for update lock status * Refactor riommu invalidation wa * Ensure dentist display clock update finished in DCN20 Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.76 Aric Cyr (1): drm/amd/display: 3.2.146 Dale Zhao (1): drm/amd/display: ensure dentist display clock update finished in DCN20 Eric Bernstein (1): drm/amd/display: Always wait for update lock status Eric Yang (2): drm/amd/display: fix missing reg offset drm/amd/display: refactor riommu invalidation wa Mark Morra (1): drm/amd/display: Fixed EdidUtility build errors Mikita Lipski (1): drm/amd/display: Fix PSR command version Victor Lu (2): drm/amd/display: Guard DST_Y_PREFETCH register overflow in DCN21 drm/amd/display: Add missing DCN21 IP parameter Wenjing Liu (2): drm/amd/display: add update authentication interface drm/amd/display: remove unused functions Wyatt Wood (2): drm/amd/display: Add ETW logging for AUX failures drm/amd/display: Add ETW log to dmub_psr_get_state .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 4 +- .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 108 +++-- drivers/gpu/drm/amd/display/dc/dc.h | 120 +++--- drivers/gpu/drm/amd/display/dc/dc_types.h | 81 ++-- drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 8 + drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 21 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 6 - .../drm/amd/display/dc/dcn21/dcn21_resource.c | 1 + .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 8 +- .../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 48 ++- .../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 17 - .../gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 2 +- .../drm/amd/display/dc/dcn31/dcn31_resource.c | 1 - .../dc/dml/dcn21/display_mode_vba_21.c| 3 + drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 393 ++ .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 3 - .../amd/display/dc/inc/hw_sequencer_private.h | 1 - .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 5 +- .../gpu/drm/amd/display/modules/hdcp/hdcp.c | 70 +++- .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 2 - .../display/modules/hdcp/hdcp1_execution.c| 6 - .../display/modules/hdcp/hdcp2_execution.c| 3 - .../drm/amd/display/modules/hdcp/hdcp_psp.c | 53 +-- .../drm/amd/display/modules/inc/mod_hdcp.h| 12 +- 26 files changed, 538 insertions(+), 444 deletions(-) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/14] DC Patches July 26, 2021
This DC patchset brings improvements in multiple areas. In summary, we highlight: * Guard DST_Y_PREFETCH register overflow in DCN21 * Add missing DCN21 IP parameter * Fix PSR command version * Add ETW logging for AUX failures * Add ETW log to dmub_psr_get_state * Fixed EdidUtility build errors * Fix missing reg offset for the dmcub test debug registers * Adding update authentication interface * Remove unused functions of opm state query support * Always wait for update lock status * Refactor riommu invalidation wa * Ensure dentist display clock update finished in DCN20 Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.76 Aric Cyr (1): drm/amd/display: 3.2.146 Dale Zhao (1): drm/amd/display: ensure dentist display clock update finished in DCN20 Eric Bernstein (1): drm/amd/display: Always wait for update lock status Eric Yang (2): drm/amd/display: fix missing reg offset drm/amd/display: refactor riommu invalidation wa Mark Morra (1): drm/amd/display: Fixed EdidUtility build errors Mikita Lipski (1): drm/amd/display: Fix PSR command version Victor Lu (2): drm/amd/display: Guard DST_Y_PREFETCH register overflow in DCN21 drm/amd/display: Add missing DCN21 IP parameter Wenjing Liu (2): drm/amd/display: add update authentication interface drm/amd/display: remove unused functions Wyatt Wood (2): drm/amd/display: Add ETW logging for AUX failures drm/amd/display: Add ETW log to dmub_psr_get_state .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 4 +- .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 108 +++-- drivers/gpu/drm/amd/display/dc/dc.h | 120 +++--- drivers/gpu/drm/amd/display/dc/dc_types.h | 81 ++-- drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 8 + drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 21 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 6 - .../drm/amd/display/dc/dcn21/dcn21_resource.c | 1 + .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 8 +- .../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 48 ++- .../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 17 - .../gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 2 +- .../drm/amd/display/dc/dcn31/dcn31_resource.c | 1 - .../dc/dml/dcn21/display_mode_vba_21.c| 3 + drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 393 ++ .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 3 - .../amd/display/dc/inc/hw_sequencer_private.h | 1 - .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 5 +- .../gpu/drm/amd/display/modules/hdcp/hdcp.c | 70 +++- .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 2 - .../display/modules/hdcp/hdcp1_execution.c| 6 - .../display/modules/hdcp/hdcp2_execution.c| 3 - .../drm/amd/display/modules/hdcp/hdcp_psp.c | 53 +-- .../drm/amd/display/modules/inc/mod_hdcp.h| 12 +- 26 files changed, 538 insertions(+), 444 deletions(-) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/14] drm/amd/display: 3.2.128
From: Aric Cyr This version brings along following fixes: - Populate socclk entries for dcn2.1 - hide VGH asic specific structs - Add kernel doc to crc_rd_wrk field - revert max lb lines change - Log DMCUB trace buffer events - Fix debugfs link_settings entry - revert max lb use by default for n10 - Deallocate IRQ handlers on amdgpu_dm_irq_fini - Fixed Clock Recovery Sequence - Fix UBSAN: shift-out-of-bounds warning - [FW Promotion] Release 0.0.57 - Change input parameter for set_drr - Use pwrseq instance to determine eDP instance Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Solomon Chiu --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d163007e057c..55f3c76823d8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ /* forward declaration */ struct aux_payload; -#define DC_VER "3.2.127" +#define DC_VER "3.2.128" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/14] drm/amd/display: Use pwrseq instance to determine eDP instance
From: Jake Wang
[Why & How]
Link index doesn't always correspond to the appropriate eDP instance.
We can assume lower link index is a lower eDP instance and set panel
control instance accordingly.
Signed-off-by: Jake Wang
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 10e34e411e06..e1e8a8bdf476 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1383,6 +1383,8 @@ static bool dc_link_construct(struct dc_link *link,
struct dc_bios *bios = init_params->dc->ctx->dc_bios;
const struct dc_vbios_funcs *bp_funcs = bios->funcs;
struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
+ struct dc_link *edp_links[MAX_NUM_EDP];
+ int edp_num;
DC_LOGGER_INIT(dc_ctx->logger);
@@ -1506,7 +1508,11 @@ static bool dc_link_construct(struct dc_link *link,
(link->link_id.id == CONNECTOR_ID_EDP ||
link->link_id.id == CONNECTOR_ID_LVDS)) {
panel_cntl_init_data.ctx = dc_ctx;
- panel_cntl_init_data.inst = link->link_index;
+ get_edp_links(panel_cntl_init_data.ctx->dc, edp_links,
_num);
+ if ((edp_num > 1) && (link->link_index >
edp_links[0]->link_index))
+ panel_cntl_init_data.inst = 1;
+ else
+ panel_cntl_init_data.inst = 0;
link->panel_cntl =
link->dc->res_pool->funcs->panel_cntl_create(
_cntl_init_data);
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 12/14] drm/amd/display: Change input parameter for set_drr
From: Alvin Lee
[Why]
Change set_drr to pass in the entire dc_crtc_timing_adjust
structure instead of passing in the parameters individually.
This is to more easily pass in required parameters in the
adjust structure when it gets updated.
Signed-off-by: Alvin Lee
Reviewed-by: Jun Lei
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 ++---
.../display/dc/dce110/dce110_hw_sequencer.c | 9 ++---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 +++
.../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 3 +-
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 +-
.../amd/display/modules/freesync/freesync.c | 37 +--
.../amd/display/modules/inc/mod_freesync.h| 7 +++-
7 files changed, 49 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8e6c815b55d2..d55c1dd6464c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -304,7 +304,10 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
int i = 0;
bool ret = false;
- stream->adjust = *adjust;
+ stream->adjust.v_total_max = adjust->v_total_max;
+ stream->adjust.v_total_mid = adjust->v_total_mid;
+ stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
+ stream->adjust.v_total_min = adjust->v_total_min;
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe = >current_state->res_ctx.pipe_ctx[i];
@@ -312,10 +315,7 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
if (pipe->stream == stream && pipe->stream_res.tg) {
dc->hwss.set_drr(,
1,
- adjust->v_total_min,
- adjust->v_total_max,
- adjust->v_total_mid,
- adjust->v_total_mid_frame_num);
+ *adjust);
ret = true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 804092f81f85..873c6f2d2cd9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1846,8 +1846,7 @@ void dce110_set_safe_displaymarks(
**/
static void set_drr(struct pipe_ctx **pipe_ctx,
- int num_pipes, unsigned int vmin, unsigned int vmax,
- unsigned int vmid, unsigned int vmid_frame_number)
+ int num_pipes, struct dc_crtc_timing_adjust adjust)
{
int i = 0;
struct drr_params params = {0};
@@ -1856,8 +1855,8 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
// Note DRR trigger events are generated regardless of whether num
frames met.
unsigned int num_frames = 2;
- params.vertical_total_max = vmax;
- params.vertical_total_min = vmin;
+ params.vertical_total_max = adjust.v_total_max;
+ params.vertical_total_min = adjust.v_total_min;
/* TODO: If multiple pipes are to be supported, you need
* some GSL stuff. Static screen triggers may be programmed differently
@@ -1867,7 +1866,7 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
pipe_ctx[i]->stream_res.tg->funcs->set_drr(
pipe_ctx[i]->stream_res.tg, );
- if (vmax != 0 && vmin != 0)
+ if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
pipe_ctx[i]->stream_res.tg,
event_triggers, num_frames);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 9eb33eae0e81..e0aa88a7766b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3271,8 +3271,7 @@ void dcn10_optimize_bandwidth(
}
void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
- int num_pipes, unsigned int vmin, unsigned int vmax,
- unsigned int vmid, unsigned int vmid_frame_number)
+ int num_pipes, struct dc_crtc_timing_adjust adjust)
{
int i = 0;
struct drr_params params = {0};
@@ -3281,11 +3280,10 @@ void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
// Note DRR trigger events are generated regardless of whether num
frames met.
unsigned int num_frames = 2;
- params.vertical_total_max = vmax;
- params.vertica
[PATCH 11/14] drm/amd/display: [FW Promotion] Release 0.0.57
From: Anthony Koo Signed-off-by: Anthony Koo Reviewed-by: Anthony Koo Acked-by: Solomon Chiu --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index f07b348f7c29..09c62485a1f1 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -47,10 +47,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0xc29b1734b +#define DMUB_FW_VERSION_GIT_HASH 0x899019e5c #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 56 +#define DMUB_FW_VERSION_REVISION 57 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 10/14] drm/amd/display: Fix UBSAN: shift-out-of-bounds warning
From: Anson Jacob
[Why]
On NAVI14 CONFIG_UBSAN reported shift-out-of-bounds at
display_rq_dlg_calc_20v2.c:304:38
rq_param->misc.rq_c.blk256_height is 0 when chroma(*_c) is invalid.
dml_log2 returns -1023 for log2(0), although log2(0) is undefined.
Which ended up as:
rq_param->dlg.rq_c.swath_height = 1 << -1023
[How]
Fix applied on all dml versions.
1. Ensure dml_log2 is only called if the argument is greater than 0.
2. Subtract req128_l/req128_c from log2_swath_height_l/log2_swath_height_c
only when it is greater than 0.
Signed-off-by: Anson Jacob
Reviewed-by: Dmytro Laktyushkin
Reviewed-by: Jun Lei
Acked-by: Solomon Chiu
---
.../dc/dml/dcn20/display_rq_dlg_calc_20.c | 28 +++
.../dc/dml/dcn20/display_rq_dlg_calc_20v2.c | 28 +++
.../dc/dml/dcn21/display_rq_dlg_calc_21.c | 28 +++
.../dc/dml/dcn30/display_rq_dlg_calc_30.c | 28 +++
.../display/dc/dml/dml1_display_rq_dlg_calc.c | 28 +++
5 files changed, 115 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
index 72423dc425dc..799bae229e67 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
@@ -293,13 +293,31 @@ static void handle_det_buf_split(struct display_mode_lib
*mode_lib,
if (surf_linear) {
log2_swath_height_l = 0;
log2_swath_height_c = 0;
- } else if (!surf_vert) {
- log2_swath_height_l =
dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
- log2_swath_height_c =
dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
} else {
- log2_swath_height_l =
dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
- log2_swath_height_c =
dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
+ unsigned int swath_height_l;
+ unsigned int swath_height_c;
+
+ if (!surf_vert) {
+ swath_height_l = rq_param->misc.rq_l.blk256_height;
+ swath_height_c = rq_param->misc.rq_c.blk256_height;
+ } else {
+ swath_height_l = rq_param->misc.rq_l.blk256_width;
+ swath_height_c = rq_param->misc.rq_c.blk256_width;
+ }
+
+ if (swath_height_l > 0)
+ log2_swath_height_l = dml_log2(swath_height_l);
+
+ if (req128_l && log2_swath_height_l > 0)
+ log2_swath_height_l -= 1;
+
+ if (swath_height_c > 0)
+ log2_swath_height_c = dml_log2(swath_height_c);
+
+ if (req128_c && log2_swath_height_c > 0)
+ log2_swath_height_c -= 1;
}
+
rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
index 9c78446c3a9d..6a6d5970d1d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
@@ -293,13 +293,31 @@ static void handle_det_buf_split(struct display_mode_lib
*mode_lib,
if (surf_linear) {
log2_swath_height_l = 0;
log2_swath_height_c = 0;
- } else if (!surf_vert) {
- log2_swath_height_l =
dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
- log2_swath_height_c =
dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
} else {
- log2_swath_height_l =
dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
- log2_swath_height_c =
dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
+ unsigned int swath_height_l;
+ unsigned int swath_height_c;
+
+ if (!surf_vert) {
+ swath_height_l = rq_param->misc.rq_l.blk256_height;
+ swath_height_c = rq_param->misc.rq_c.blk256_height;
+ } else {
+ swath_height_l = rq_param->misc.rq_l.blk256_width;
+ swath_height_c = rq_param->misc.rq_c.blk256_width;
+ }
+
+ if (swath_height_l > 0)
+ log2_swath_height_l = dml_log2(swath_height_l);
+
+ if (req128_l && log2_swath_height_l > 0)
+ log2_swath_height_l -= 1;
+
+ if (swath_height_c > 0)
+ log2_swath_height_c = dml_log2(s
[PATCH 09/14] drm/amd/display: Fixed Clock Recovery Sequence
From: David Galiffi [Why] When performing clock recovery, if a pre-emphasis adjustment is requested, but voltage swing remains constant, the the retry counter will not be reset. This can lead to prematurely failing link training. [How] Reset the clock recovery retry counter if an adjustment is requested for either voltage swing or pre-emphasis. Signed-off-by: Calvin Hou Signed-off-by: David Galiffi Reviewed-by: Jun Lei Acked-by: Solomon Chiu --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 47e6c33f73cb..484d96f78ade 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1098,11 +1098,13 @@ static enum link_training_result perform_clock_recovery_sequence( if (is_max_vs_reached(lt_settings)) break; - /* 7. same voltage*/ - /* Note: VS same for all lanes, - * so comparing first lane is sufficient*/ - if (lt_settings->lane_settings[0].VOLTAGE_SWING == + /* 7. same lane settings*/ + /* Note: settings are the same for all lanes, +* so comparing first lane is sufficient*/ + if ((lt_settings->lane_settings[0].VOLTAGE_SWING == req_settings.lane_settings[0].VOLTAGE_SWING) + && (lt_settings->lane_settings[0].PRE_EMPHASIS == + req_settings.lane_settings[0].PRE_EMPHASIS)) retries_cr++; else retries_cr = 0; -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 08/14] drm/amd/display: Deallocate IRQ handlers on amdgpu_dm_irq_fini
From: Victor Lu
[why]
The amdgpu_dm IRQ handlers are not freed during the IRQ teardown.
[how]
Add function to deallocate IRQ handlers on amdgpu_dm_irq_fini step.
Signed-off-by: Victor Lu
Reviewed-by: Roman Li
Acked-by: Solomon Chiu
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 51 +++
1 file changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index ffd18cd90947..da2703a04e23 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -184,6 +184,55 @@ static struct list_head *remove_irq_handler(struct
amdgpu_device *adev,
return hnd_list;
}
+/**
+ * unregister_all_irq_handlers() - Cleans up handlers from the DM IRQ table
+ * @adev: The base driver device containing the DM device
+ *
+ * Go through low and high context IRQ tables and deallocate handlers.
+ */
+static void unregister_all_irq_handlers(struct amdgpu_device *adev)
+{
+ struct list_head *hnd_list_low;
+ struct list_head *hnd_list_high;
+ struct list_head *entry, *tmp;
+ struct amdgpu_dm_irq_handler_data *handler;
+ unsigned long irq_table_flags;
+ int i;
+
+ DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
+
+ for (i = 0; i < DAL_IRQ_SOURCES_NUMBER; i++) {
+ hnd_list_low = >dm.irq_handler_list_low_tab[i];
+ hnd_list_high = >dm.irq_handler_list_high_tab[i];
+
+ list_for_each_safe(entry, tmp, hnd_list_low) {
+
+ handler = list_entry(entry, struct
amdgpu_dm_irq_handler_data,
+list);
+
+ if (handler == NULL || handler->handler == NULL)
+ continue;
+
+ list_del(>list);
+ kfree(handler);
+ }
+
+ list_for_each_safe(entry, tmp, hnd_list_high) {
+
+ handler = list_entry(entry, struct
amdgpu_dm_irq_handler_data,
+list);
+
+ if (handler == NULL || handler->handler == NULL)
+ continue;
+
+ list_del(>list);
+ kfree(handler);
+ }
+ }
+
+ DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
+}
+
static bool
validate_irq_registration_params(struct dc_interrupt_params *int_params,
void (*ih)(void *))
@@ -414,6 +463,8 @@ void amdgpu_dm_irq_fini(struct amdgpu_device *adev)
}
}
}
+ /* Deallocate handlers from the table. */
+ unregister_all_irq_handlers(adev);
}
int amdgpu_dm_irq_suspend(struct amdgpu_device *adev)
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 06/14] drm/amd/display: Fix debugfs link_settings entry
From: Fangzhi Zuo 1. Catch invalid link_rate and link_count settings 2. Call dc interface to overwrite preferred link settings, and wait until next stream update to apply the new settings. Signed-off-by: Fangzhi Zuo Reviewed-by: Nicholas Kazlauskas Acked-by: Solomon Chiu --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 927de7678a4f..f6f10a8c3e43 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -149,7 +149,7 @@ static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, * * --- to get dp configuration * - * cat link_settings + * cat /sys/kernel/debug/dri/0/DP-x/link_settings * * It will list current, verified, reported, preferred dp configuration. * current -- for current video mode @@ -162,7 +162,7 @@ static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, * echo> link_settings * * for example, to force to 2 lane, 2.7GHz, - * echo 4 0xa > link_settings + * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings * * spread_spectrum could not be changed dynamically. * @@ -170,7 +170,7 @@ static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, * done. please check link settings after force operation to see if HW get * programming. * - * cat link_settings + * cat /sys/kernel/debug/dri/0/DP-x/link_settings * * check current and preferred settings. * @@ -254,7 +254,7 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, int max_param_num = 2; uint8_t param_nums = 0; long param[2]; - bool valid_input = false; + bool valid_input = true; if (size == 0) return -EINVAL; @@ -281,9 +281,9 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, case LANE_COUNT_ONE: case LANE_COUNT_TWO: case LANE_COUNT_FOUR: - valid_input = true; break; default: + valid_input = false; break; } @@ -293,9 +293,9 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, case LINK_RATE_RBR2: case LINK_RATE_HIGH2: case LINK_RATE_HIGH3: - valid_input = true; break; default: + valid_input = false; break; } @@ -309,10 +309,11 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, * spread spectrum will not be changed */ prefer_link_settings.link_spread = link->cur_link_settings.link_spread; + prefer_link_settings.use_link_rate_set = false; prefer_link_settings.lane_count = param[0]; prefer_link_settings.link_rate = param[1]; - dc_link_set_preferred_link_settings(dc, _link_settings, link); + dc_link_set_preferred_training_settings(dc, _link_settings, NULL, link, true); kfree(wr_buf); return size; -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/14] drm/amd/display: revert max lb use by default for n10
From: Dmytro Laktyushkin
This is causing a pstate change underflow regression for
unknown reason
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 --
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 --
2 files changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 0b1000d782a8..f962b905e79e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -619,7 +619,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.recovery_enabled = false, /*enable this by default after
testing.*/
.max_downscale_src_width = 3840,
.underflow_assert_delay_us = 0x,
- .use_max_lb = true
};
static const struct dc_debug_options debug_defaults_diags = {
@@ -631,7 +630,6 @@ static const struct dc_debug_options debug_defaults_diags =
{
.disable_pplib_clock_request = true,
.disable_pplib_wm_range = true,
.underflow_assert_delay_us = 0x,
- .use_max_lb = true
};
static void dcn10_dpp_destroy(struct dpp **dpp)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index b8acad7acd94..28a3b4185424 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1075,7 +1075,6 @@ static const struct dc_debug_options debug_defaults_drv =
{
.scl_reset_length10 = true,
.sanity_checks = false,
.underflow_assert_delay_us = 0x,
- .use_max_lb = true
};
static const struct dc_debug_options debug_defaults_diags = {
@@ -1092,7 +1091,6 @@ static const struct dc_debug_options debug_defaults_diags
= {
.scl_reset_length10 = true,
.underflow_assert_delay_us = 0x,
.enable_tri_buf = true,
- .use_max_lb = true
};
void dcn20_dpp_destroy(struct dpp **dpp)
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/14] drm/amd/display: revert max lb lines change
From: Dmytro Laktyushkin
Some hardware revisions do have a max number of lines limitation
not honouring which can cause pstate switch underflow.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +-
6 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index d079f4e491e5..0b1000d782a8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -82,7 +82,7 @@ const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
.meta_chunk_size_kbytes = 2,
.writeback_chunk_size_kbytes = 2,
.line_buffer_size_bits = 589824,
- .max_line_buffer_lines = 32,
+ .max_line_buffer_lines = 12,
.IsLineBufferBppFixed = 0,
.LineBufferFixedBpp = -1,
.writeback_luma_buffer_size_kbytes = 12,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2307b3517821..b8acad7acd94 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -112,7 +112,7 @@ struct _vcs_dpi_ip_params_st dcn2_0_ip = {
.is_line_buffer_bpp_fixed = 0,
.line_buffer_fixed_bpp = 0,
.dcc_supported = true,
- .max_line_buffer_lines = 32,
+ .max_line_buffer_lines = 12,
.writeback_luma_buffer_size_kbytes = 12,
.writeback_chroma_buffer_size_kbytes = 8,
.writeback_chroma_line_buffer_width_pixels = 4,
@@ -180,7 +180,7 @@ static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
.is_line_buffer_bpp_fixed = 0,
.line_buffer_fixed_bpp = 0,
.dcc_supported = true,
- .max_line_buffer_lines = 32,
+ .max_line_buffer_lines = 12,
.writeback_luma_buffer_size_kbytes = 12,
.writeback_chroma_buffer_size_kbytes = 8,
.writeback_chroma_line_buffer_width_pixels = 4,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 7123151ed60f..8e3f1d0b4cc3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -114,7 +114,7 @@ struct _vcs_dpi_ip_params_st dcn2_1_ip = {
.is_line_buffer_bpp_fixed = 0,
.line_buffer_fixed_bpp = 0,
.dcc_supported = true,
- .max_line_buffer_lines = 32,
+ .max_line_buffer_lines = 12,
.writeback_luma_buffer_size_kbytes = 12,
.writeback_chroma_buffer_size_kbytes = 8,
.writeback_chroma_line_buffer_width_pixels = 4,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 263c2986682d..4a5fa23d8e7b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -120,7 +120,7 @@ struct _vcs_dpi_ip_params_st dcn3_0_ip = {
.dcc_supported = true,
.writeback_interface_buffer_size_kbytes = 90,
.writeback_line_buffer_buffer_size = 0,
- .max_line_buffer_lines = 32,
+ .max_line_buffer_lines = 12,
.writeback_luma_buffer_size_kbytes = 12, //
writeback_line_buffer_buffer_size = 656640
.writeback_chroma_buffer_size_kbytes = 8,
.writeback_chroma_line_buffer_width_pixels = 4,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 0fbdfff87835..10c1884e3d30 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -116,7 +116,7 @@ struct _vcs_dpi_ip_params_st dcn3_01_ip = {
.dcc_supported = true,
.writeback_interface_buffer_size_kbytes = 90,
.writeback_line_buffer_buffer_size = 656640,
- .max_line_buffer_lines = 32,
+ .max_line_buffer_lines = 12,
.writeback_luma_buffer_size_kbytes = 12, //
writeback_line_buffer_buffer_size = 656640
.writeback_chroma_buffer_size_kbytes = 8,
.writeback_chroma_line_buffer_width_pixels = 4,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index 0723e29fd42e..a928c1d9a557 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -101,7 +101,7 @@ struct _vcs_dpi_ip_params_st dcn3_02_ip
[PATCH 03/14] drm/amd/display: Add kernel doc to crc_rd_wrk field
From: Wayne Lin
[Why]
Receive warning message below:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:380: warning: Function
parameter or member 'crc_rd_wrk' not described in 'amdgpu_display_manager'
[How]
Add documentation for crc_rd_wrk.
Reported-by: Stephen Rothwell
Signed-off-by: Wayne Lin
Reviewed-by: Rodrigo Siqueira
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 2c9eed78f6df..f7f0680c1fa1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -385,6 +385,11 @@ struct amdgpu_display_manager {
#endif
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
+ /**
+* @crc_rd_wrk
+*
+* Work to be executed in a separate thread to communicate with PSP.
+*/
struct crc_rd_work *crc_rd_wrk;
#endif
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 05/14] drm/amd/display: Log DMCUB trace buffer events
From: "Leo (Hanghong) Ma"
[Why]
We want to log DMCUB trace buffer events as Linux kernel traces.
[How]
Register an IRQ handler for DMCUB outbox0 interrupt in amdgpu_dm,
and log the messages in the DMCUB tracebuffer to a new DMCUB
TRACE_EVENT as soon as we receive the outbox0 IRQ from DMCUB FW.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Harry Wentland
Acked-by: Solomon Chiu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 48 +++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 9
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 12 -
.../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 20
.../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 21
.../display/dc/irq/dcn21/irq_service_dcn21.c | 32 -
.../display/dc/irq/dcn30/irq_service_dcn30.c | 32 -
7 files changed, 170 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8b464debc1ef..36100eeefb3b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -908,6 +908,32 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
return 0;
}
+#define DMUB_TRACE_MAX_READ 64
+static void dm_dmub_trace_high_irq(void *interrupt_params)
+{
+ struct common_irq_params *irq_params = interrupt_params;
+ struct amdgpu_device *adev = irq_params->adev;
+ struct amdgpu_display_manager *dm = >dm;
+ struct dmcub_trace_buf_entry entry = { 0 };
+ uint32_t count = 0;
+
+ do {
+ if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, )) {
+ trace_amdgpu_dmub_trace_high_irq(entry.trace_code,
entry.tick_count,
+ entry.param0,
entry.param1);
+
+ DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u,
param0:%u, param1:%u\n",
+entry.trace_code, entry.tick_count,
entry.param0, entry.param1);
+ } else
+ break;
+
+ count++;
+
+ } while (count <= DMUB_TRACE_MAX_READ);
+
+ ASSERT(count <= DMUB_TRACE_MAX_READ);
+}
+
#if defined(CONFIG_DRM_AMD_DC_DCN)
static void mmhub_read_system_context(struct amdgpu_device *adev, struct
dc_phy_addr_space_config *pa_config)
{
@@ -3078,6 +3104,28 @@ static int dcn10_register_irq_handlers(struct
amdgpu_device *adev)
}
+ if (dc->ctx->dmub_srv) {
+ i = DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT;
+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i,
>dmub_trace_irq);
+
+ if (r) {
+ DRM_ERROR("Failed to add dmub trace irq id!\n");
+ return r;
+ }
+
+ int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
+ int_params.irq_source =
+ dc_interrupt_to_irq_source(dc, i, 0);
+
+ c_irq_params = >dm.dmub_trace_params[0];
+
+ c_irq_params->adev = adev;
+ c_irq_params->irq_src = int_params.irq_source;
+
+ amdgpu_dm_irq_register_interrupt(adev, _params,
+ dm_dmub_trace_high_irq, c_irq_params);
+ }
+
/* HPD */
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
DCN_1_0__SRCID__DC_HPD1_INT,
>hpd_irq);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index f7f0680c1fa1..9d12f304b2ee 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -339,6 +339,15 @@ struct amdgpu_display_manager {
struct common_irq_params
vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
+ /**
+* @dmub_trace_params:
+*
+* DMUB trace event IRQ parameters, passed to registered handlers when
+* triggered.
+*/
+ struct common_irq_params
+ dmub_trace_params[1];
+
spinlock_t irq_handler_list_table_lock;
struct backlight_device *backlight_dev;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 09bdffb3a09e..103e29905b57 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -700,6 +700,14 @@ void dm_helpers_free_gpu_mem(
bool dm_helpers_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool
enable)
{
- // TODO
- return true;
+ enum dc_irq_source irq_source;
+ bool ret;
+
+ irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX0;
+
+ ret = dc_interrupt_set(ctx->dc, irq_source, enable);
+
+ DRM_DEBUG_DRIVER("Dmub
[PATCH 02/14] drm/amd/display: hide VGH asic specific structs
From: Dmytro Laktyushkin
The pmfw structs are specific to the asic and should not be
present in base clk_mgr struct
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Yang
Acked-by: Solomon Chiu
---
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 116 +-
.../display/dc/clk_mgr/dcn301/vg_clk_mgr.c| 101 +++
.../display/dc/clk_mgr/dcn301/vg_clk_mgr.h| 28 ++---
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 1 -
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 9 --
5 files changed, 147 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index f7c728d4f50a..203150dd37f6 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -125,87 +125,135 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context
*ctx, struct pp_smu_funcs *p
{
struct hw_asic_id asic_id = ctx->asic_id;
- struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr),
GFP_KERNEL);
-
- if (clk_mgr == NULL) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
switch (asic_id.chip_family) {
#if defined(CONFIG_DRM_AMD_DC_SI)
- case FAMILY_SI:
+ case FAMILY_SI: {
+ struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr),
GFP_KERNEL);
+
+ if (clk_mgr == NULL) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
dce60_clk_mgr_construct(ctx, clk_mgr);
- break;
+ dce_clk_mgr_construct(ctx, clk_mgr);
+ }
#endif
case FAMILY_CI:
- case FAMILY_KV:
+ case FAMILY_KV: {
+ struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr),
GFP_KERNEL);
+
+ if (clk_mgr == NULL) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
dce_clk_mgr_construct(ctx, clk_mgr);
- break;
- case FAMILY_CZ:
+ return _mgr->base;
+ }
+ case FAMILY_CZ: {
+ struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr),
GFP_KERNEL);
+
+ if (clk_mgr == NULL) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
dce110_clk_mgr_construct(ctx, clk_mgr);
- break;
- case FAMILY_VI:
+ return _mgr->base;
+ }
+ case FAMILY_VI: {
+ struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr),
GFP_KERNEL);
+
+ if (clk_mgr == NULL) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
dce_clk_mgr_construct(ctx, clk_mgr);
- break;
+ return _mgr->base;
}
if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
dce112_clk_mgr_construct(ctx, clk_mgr);
- break;
+ return _mgr->base;
}
if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) {
dce112_clk_mgr_construct(ctx, clk_mgr);
- break;
+ return _mgr->base;
+ }
+ return _mgr->base;
+ }
+ case FAMILY_AI: {
+ struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr),
GFP_KERNEL);
+
+ if (clk_mgr == NULL) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
}
- break;
- case FAMILY_AI:
if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
dce121_clk_mgr_construct(ctx, clk_mgr);
else
dce120_clk_mgr_construct(ctx, clk_mgr);
- break;
-
+ return _mgr->base;
+ }
#if defined(CONFIG_DRM_AMD_DC_DCN)
- case FAMILY_RV:
+ case FAMILY_RV: {
+ struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr),
GFP_KERNEL);
+
+ if (clk_mgr == NULL) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
- break;
+ return _mgr->base;
}
if (ASICREV_IS_GREEN_SARD
[PATCH 01/14] drm/amd/display: Populate socclk entries for dcn2.1
From: Roman Li
[Why]
Dcn2.1 socclk entries in bandwidth params are not initialized.
They are not used now, but will be needed for dml validation.
[How]
Populate socclk bw params from dpm clock table
Signed-off-by: Roman Li
Reviewed-by: Dmytro Laktyushkin
Acked-by: Solomon Chiu
---
.../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 01b1853b7750..887a54246bde 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -797,7 +797,18 @@ static struct wm_table lpddr4_wm_table_rn = {
},
}
};
+static unsigned int find_socclk_for_voltage(struct dpm_clocks *clock_table,
unsigned int voltage)
+{
+ int i;
+
+ for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
+ if (clock_table->SocClocks[i].Vol == voltage)
+ return clock_table->SocClocks[i].Freq;
+ }
+ ASSERT(0);
+ return 0;
+}
static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table,
unsigned int voltage)
{
int i;
@@ -841,6 +852,8 @@ static void rn_clk_mgr_helper_populate_bw_params(struct
clk_bw_params *bw_params
bw_params->clk_table.entries[i].memclk_mhz =
clock_table->MemClocks[j].Freq;
bw_params->clk_table.entries[i].voltage =
clock_table->FClocks[j].Vol;
bw_params->clk_table.entries[i].dcfclk_mhz =
find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
+ bw_params->clk_table.entries[i].socclk_mhz =
find_socclk_for_voltage(clock_table,
+
bw_params->clk_table.entries[i].voltage);
}
bw_params->vram_type = bios_info->memory_type;
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/14] DC Patches March 22, 2021
This DC patchset brings improvements in multiple areas. In summary, we highlight: * Populate socclk entries for dcn2.1 * hide VGH asic specific structs * Add kernel doc to crc_rd_wrk field * revert max lb lines change * Log DMCUB trace buffer events * Fix debugfs link_settings entry * revert max lb use by default for n10 * Deallocate IRQ handlers on amdgpu_dm_irq_fini * Fixed Clock Recovery Sequence * Fix UBSAN: shift-out-of-bounds warning * [FW Promotion] Release 0.0.57 * Change input parameter for set_drr * Use pwrseq instance to determine eDP instance Alvin Lee (1): drm/amd/display: Change input parameter for set_drr Anson Jacob (1): drm/amd/display: Fix UBSAN: shift-out-of-bounds warning Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.57 Aric Cyr (1): drm/amd/display: 3.2.128 David Galiffi (1): drm/amd/display: Fixed Clock Recovery Sequence Dmytro Laktyushkin (3): drm/amd/display: hide VGH asic specific structs drm/amd/display: revert max lb lines change drm/amd/display: revert max lb use by default for n10 Fangzhi Zuo (1): drm/amd/display: Fix debugfs link_settings entry Jake Wang (1): drm/amd/display: Use pwrseq instance to determine eDP instance Leo (Hanghong) Ma (1): drm/amd/display: Log DMCUB trace buffer events Roman Li (1): drm/amd/display: Populate socclk entries for dcn2.1 Victor Lu (1): drm/amd/display: Deallocate IRQ handlers on amdgpu_dm_irq_fini Wayne Lin (1): drm/amd/display: Add kernel doc to crc_rd_wrk field .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 48 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 14 +++ .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 15 +-- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 12 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 71 +++ .../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 21 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 116 +- .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 13 ++ .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c| 101 +++ .../display/dc/clk_mgr/dcn301/vg_clk_mgr.h| 28 ++--- drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 10 +- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- .../display/dc/dce110/dce110_hw_sequencer.c | 9 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 +-- .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 3 +- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 6 +- .../drm/amd/display/dc/dcn21/dcn21_resource.c | 3 +- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +- .../amd/display/dc/dcn301/dcn301_resource.c | 2 +- .../amd/display/dc/dcn302/dcn302_resource.c | 2 +- .../dc/dml/dcn20/display_rq_dlg_calc_20.c | 28 - .../dc/dml/dcn20/display_rq_dlg_calc_20v2.c | 28 - .../dc/dml/dcn21/display_rq_dlg_calc_21.c | 28 - .../dc/dml/dcn30/display_rq_dlg_calc_30.c | 28 - .../display/dc/dml/dml1_display_rq_dlg_calc.c | 28 - .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 9 -- .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 +- .../display/dc/irq/dcn21/irq_service_dcn21.c | 32 - .../display/dc/irq/dcn30/irq_service_dcn30.c | 32 - .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +- .../amd/display/modules/freesync/freesync.c | 37 -- .../amd/display/modules/inc/mod_freesync.h| 7 +- 35 files changed, 581 insertions(+), 197 deletions(-) -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 23/23] drm/amd/display: Fix potential memory leak
From: Qingqing Zhuo
[Why]
vblank_workqueue is never released.
[How]
Free it upon dm finish.
Signed-off-by: Qingqing Zhuo
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 3db69f5bd6e9..41f19ec743d4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1228,6 +1228,15 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
if (adev->dm.dc)
dc_deinit_callbacks(adev->dm.dc);
#endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+ if (adev->dm.vblank_workqueue) {
+ adev->dm.vblank_workqueue->dm = NULL;
+ kfree(adev->dm.vblank_workqueue);
+ adev->dm.vblank_workqueue = NULL;
+ }
+#endif
+
if (adev->dm.dc->ctx->dmub_srv) {
dc_dmub_srv_destroy(>dm.dc->ctx->dmub_srv);
adev->dm.dc->ctx->dmub_srv = NULL;
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 22/23] drm/amd/display: add a func to disable accelerated mode
From: Yao Wang1
[Why]
When driver disabled, we driver force the YCbCr420 to RGB,
which means some register will be changed, such as
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV changed from 1 to 0
When driver re-enabled, OS will Set Mode YCbCr420 again,
which means the register RDPCS_PHY_DP_MPLLB_TX_CLK_DIV
should to be 1 again, but dmub fw can’t update the
register to 1 due to the mpll is not off
[How]
Adds an interface to disable accelerated mode bit,
which allows DM to decide to call during driver
disable/unload scenarios.
Signed-off-by: Yao Wang1
Reviewed-by: Anthony Koo
Acked-by: Solomon Chiu
---
.../amd/display/dc/bios/bios_parser_helper.c | 5 +++--
.../amd/display/dc/bios/bios_parser_helper.h | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 18 ++
drivers/gpu/drm/amd/display/dc/dc.h| 6 ++
.../display/dc/dce110/dce110_hw_sequencer.c| 2 +-
5 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
index fce46ab54c54..53d7513b5083 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
@@ -64,9 +64,10 @@ bool bios_is_accelerated_mode(
void bios_set_scratch_acc_mode_change(
- struct dc_bios *bios)
+ struct dc_bios *bios,
+ uint32_t state)
{
- REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, 1);
+ REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, state);
}
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
index 75a29e68fb27..e1b4a40a353d 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
@@ -32,7 +32,7 @@ uint8_t *bios_get_image(struct dc_bios *bp, uint32_t offset,
uint32_t size);
bool bios_is_accelerated_mode(struct dc_bios *bios);
-void bios_set_scratch_acc_mode_change(struct dc_bios *bios);
+void bios_set_scratch_acc_mode_change(struct dc_bios *bios, uint32_t state);
void bios_set_scratch_critical_state(struct dc_bios *bios, bool state);
uint32_t bios_get_vga_enabled_displays(struct dc_bios *bios);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index dffd150180ec..8e6c815b55d2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -41,6 +41,7 @@
#include "dc_bios_types.h"
#include "bios_parser_interface.h"
+#include "bios/bios_parser_helper.h"
#include "include/irq_service_interface.h"
#include "transform.h"
#include "dmcu.h"
@@ -3372,3 +3373,20 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc,
return true;
}
+
+/**
+ *
+ * Function: dc_disable_accelerated_mode
+ *
+ * @brief
+ * disable accelerated mode
+ *
+ * @param
+ * [in] dc: dc structure
+ *
+ *
+ */
+void dc_disable_accelerated_mode(struct dc *dc)
+{
+ bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 352651c805ff..d163007e057c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1313,4 +1313,10 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc,
* DSC Interfaces
**/
#include "dc_dsc.h"
+
+/***
+ * Disable acc mode Interfaces
+
**/
+void dc_disable_accelerated_mode(struct dc *dc);
+
#endif /* DC_INTERFACE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 08047802d040..804092f81f85 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1750,7 +1750,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct
dc_state *context)
if (edp_link_with_sink && !keep_edp_vdd_on)
dc->hwss.edp_power_control(edp_link_with_sink, false);
}
- bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
+ bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
}
static uint32_t compute_pstate_blackout_duration(
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 21/23] drm/amd/display: fix dcn3+ bw validation soc param update sequence
From: Dmytro Laktyushkin
SOC needs to be updated to the WM set A values before validation
happens.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Solomon Chiu
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 17 -
.../drm/amd/display/dc/dcn30/dcn30_resource.h | 1 +
.../drm/amd/display/dc/dcn301/dcn301_resource.c | 1 +
.../drm/amd/display/dc/dcn302/dcn302_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 ++
5 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index deab48806fa2..263c2986682d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1876,6 +1876,7 @@ static noinline bool dcn30_internal_validate_bw(
if (!pipes)
return false;
+ dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes,
fast_validate);
DC_FP_START();
@@ -2225,11 +2226,7 @@ static noinline void dcn30_calculate_wm_and_dlg_fp(
*
* Set A calculated last so that following calculations are
based on Set A
*/
- if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
- context->bw_ctx.dml.soc.dram_clock_change_latency_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
- context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
- context->bw_ctx.dml.soc.sr_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
- }
+ dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
context->bw_ctx.bw.dcn.watermarks.a.urgent_ns =
get_wm_urgent(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
get_wm_stutter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
@@ -2272,6 +2269,15 @@ static noinline void dcn30_calculate_wm_and_dlg_fp(
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
}
+void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
+{
+ if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
+ context->bw_ctx.dml.soc.dram_clock_change_latency_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
+ context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
+ context->bw_ctx.dml.soc.sr_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
+ }
+}
+
void dcn30_calculate_wm_and_dlg(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
@@ -2496,6 +2502,7 @@ static const struct resource_funcs dcn30_res_pool_funcs =
{
.panel_cntl_create = dcn30_panel_cntl_create,
.validate_bandwidth = dcn30_validate_bandwidth,
.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
+ .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
index 8ce7f6d39a20..b754b89beadf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
@@ -60,6 +60,7 @@ void dcn30_calculate_wm_and_dlg(
display_e2e_pipe_params_st *pipes,
int pipe_cnt,
int vlevel);
+void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
void dcn30_populate_dml_writeback_from_context(
struct dc *dc, struct resource_context *res_ctx,
display_e2e_pipe_params_st *pipes);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 5f29a4f85ef2..e41747c39e29 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1721,6 +1721,7 @@ static struct resour
[PATCH 20/23] drm/amd/display: fix dml prefetch validation
From: Dmytro Laktyushkin
Incorrect variable used, missing initialization during validation.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 1 +
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 0f3f510fd83b..9729cf292e84 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -3437,6 +3437,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
mode_lib->vba.DCCEnabledInAnyPlane = true;
}
}
+ mode_lib->vba.UrgentLatency = mode_lib->vba.UrgentLatencyPixelDataOnly;
for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
locals->FabricAndDRAMBandwidthPerState[i] = dml_min(
mode_lib->vba.DRAMSpeedPerState[i] *
mode_lib->vba.NumberOfChannels
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 210c96cd5b03..51098c2c9854 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -3544,6 +3544,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode
mode_lib->vba.DCCEnabledInAnyPlane = true;
}
}
+ mode_lib->vba.UrgentLatency = mode_lib->vba.UrgentLatencyPixelDataOnly;
for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
locals->FabricAndDRAMBandwidthPerState[i] = dml_min(
mode_lib->vba.DRAMSpeedPerState[i] *
mode_lib->vba.NumberOfChannels
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 19/23] drm/amd/display: 3.2.127
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Solomon Chiu --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d26472ef1572..352651c805ff 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ /* forward declaration */ struct aux_payload; -#define DC_VER "3.2.126.1" +#define DC_VER "3.2.127" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 18/23] drm/amd/display: DCHUB underflow counter increasing in some scenarios
From: Aric Cyr
[Why]
When unplugging a display, the underflow counter can be seen to
increase because PSTATE switch is allowed even when some planes are not
blanked.
[How]
Check that all planes are not active instead of all streams before
allowing PSTATE change.
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index c7e5a64e06af..81ea5d3a1947 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -252,6 +252,7 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
bool force_reset = false;
bool update_uclk = false;
bool p_state_change_support;
+ int total_plane_count;
if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)
return;
@@ -292,7 +293,8 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
clk_mgr_base->clks.prev_p_state_change_support =
clk_mgr_base->clks.p_state_change_support;
- p_state_change_support = new_clocks->p_state_change_support ||
(display_count == 0);
+ total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
+ p_state_change_support = new_clocks->p_state_change_support ||
(total_plane_count == 0);
if (should_update_pstate_support(safe_to_lower, p_state_change_support,
clk_mgr_base->clks.p_state_change_support)) {
clk_mgr_base->clks.p_state_change_support =
p_state_change_support;
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 17/23] drm/amd/display: [FW Promotion] Release 0.0.56
From: Anthony Koo
More updates to the comments to better describe the function of
different cmds and parameters in the dmub interface.
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 668 ++
1 file changed, 526 insertions(+), 142 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index b6f4db3af5e8..f07b348f7c29 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x920aff8b2
+#define DMUB_FW_VERSION_GIT_HASH 0xc29b1734b
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 55
+#define DMUB_FW_VERSION_REVISION 56
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
@@ -120,14 +120,23 @@
/* Trace buffer offset for entry */
#define TRACE_BUFFER_ENTRY_OFFSET 16
+/**
+ * Physical framebuffer address location, 64-bit.
+ */
#ifndef PHYSICAL_ADDRESS_LOC
#define PHYSICAL_ADDRESS_LOC union large_integer
#endif
+/**
+ * OS/FW agnostic memcpy
+ */
#ifndef dmub_memcpy
#define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
#endif
+/**
+ * OS/FW agnostic memset
+ */
#ifndef dmub_memset
#define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
#endif
@@ -136,16 +145,22 @@
extern "C" {
#endif
+/**
+ * OS/FW agnostic udelay
+ */
#ifndef dmub_udelay
#define dmub_udelay(microseconds) udelay(microseconds)
#endif
+/**
+ * union dmub_addr - DMUB physical/virtual 64-bit address.
+ */
union dmub_addr {
struct {
- uint32_t low_part;
- uint32_t high_part;
- } u;
- uint64_t quad_part;
+ uint32_t low_part; /**< Lower 32 bits */
+ uint32_t high_part; /**< Upper 32 bits */
+ } u; /*<< Low/high bit access */
+ uint64_t quad_part; /*<< 64 bit address */
};
/**
@@ -187,11 +202,12 @@ struct dmub_feature_caps {
* Max PSR version supported by FW.
*/
uint8_t psr;
-
- /**
-* Reserved.
-*/
+#ifndef TRIM_FAMS
+ uint8_t fw_assisted_mclk_switch;
+ uint8_t reserved[6];
+#else
uint8_t reserved[7];
+#endif
};
#if defined(__cplusplus)
@@ -225,18 +241,20 @@ struct dmub_feature_caps {
* @dal_fw: 1 if the firmware is DAL
*/
struct dmub_fw_meta_info {
- uint32_t magic_value;
- uint32_t fw_region_size;
- uint32_t trace_buffer_size;
- uint32_t fw_version;
- uint8_t dal_fw;
- uint8_t reserved[3];
+ uint32_t magic_value; /**< magic value identifying DMUB firmware meta
info */
+ uint32_t fw_region_size; /**< size of the firmware state region */
+ uint32_t trace_buffer_size; /**< size of the tracebuffer region */
+ uint32_t fw_version; /**< the firmware version information */
+ uint8_t dal_fw; /**< 1 if the firmware is DAL */
+ uint8_t reserved[3]; /**< padding bits */
};
-/* Ensure that the structure remains 64 bytes. */
+/**
+ * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
+ */
union dmub_fw_meta {
- struct dmub_fw_meta_info info;
- uint8_t reserved[64];
+ struct dmub_fw_meta_info info; /**< metadata info */
+ uint8_t reserved[64]; /**< padding bits */
};
#pragma pack(pop)
@@ -244,13 +262,19 @@ union dmub_fw_meta {
//==
//< DMUB Trace
Buffer>
//==
+/**
+ * dmub_trace_code_t - firmware trace code, 32-bits
+ */
typedef uint32_t dmub_trace_code_t;
+/**
+ * struct dmcub_trace_buf_entry - Firmware trace entry
+ */
struct dmcub_trace_buf_entry {
- dmub_trace_code_t trace_code;
- uint32_t tick_count;
- uint32_t param0;
- uint32_t param1;
+ dmub_trace_code_t trace_code; /**< trace code for the event */
+ uint32_t tick_count; /**< the tick count at time of trace */
+ uint32_t param0; /**< trace defined parameter 0 */
+ uint32_t param1; /**< trace defined parameter 1 */
};
//==
@@ -265,42 +289,49 @@ struct dmcub_trace_buf_entry {
* SCRATCH15: FW Boot Options register
*/
-/* Register bit definition for SCRATCH0 */
+/**
+ * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
+ */
union dmub_fw_boot_status {
struct {
- uint32_t dal_fw : 1;
- uint32_t mailbox_rdy : 1;
- uint32_t optimized_init_d
[PATCH 16/23] drm/amd/display: Add debugfs to control DMUB trace buffer events
From: "Leo (Hanghong) Ma"
[Why]
We want to have a debugfs interface to enable or disable DMCUB
trace buffer events.
[How]
Add debugfs interface to enable or disable trace buffer events.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Harry Wentland
Acked-by: Solomon Chiu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 37 +++
2 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index be931efc772d..2c9eed78f6df 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -395,6 +395,7 @@ struct amdgpu_display_manager {
*/
struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
bool force_timing_sync;
+ bool dmcub_trace_event_en;
/**
* @da_list:
*
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index b8644f49e0f2..927de7678a4f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -34,6 +34,7 @@
#include "resource.h"
#include "dsc.h"
#include "dc_link_dp.h"
+#include "dc/dc_dmub_srv.h"
struct dmub_debugfs_trace_header {
uint32_t entry_count;
@@ -2490,6 +2491,39 @@ static int psr_get(void *data, u64 *val)
return 0;
}
+/*
+ * Set dmcub trace event IRQ enable or disable.
+ * Usage to enable dmcub trace event IRQ: echo 1 >
/sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
+ * Usage to disable dmcub trace event IRQ: echo 0 >
/sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
+ */
+static int dmcub_trace_event_state_set(void *data, u64 val)
+{
+ struct amdgpu_device *adev = data;
+
+ if (val == 1 || val == 0) {
+ dc_dmub_trace_event_control(adev->dm.dc, val);
+ adev->dm.dmcub_trace_event_en = (bool)val;
+ } else
+ return 0;
+
+ return 0;
+}
+
+/*
+ * The interface doesn't need get function, so it will return the
+ * value of zero
+ * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
+ */
+static int dmcub_trace_event_state_get(void *data, u64 *val)
+{
+ struct amdgpu_device *adev = data;
+
+ *val = adev->dm.dmcub_trace_event_en;
+ return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops,
dmcub_trace_event_state_get,
+dmcub_trace_event_state_set, "%llu\n");
DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
@@ -2970,4 +3004,7 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
adev, _timing_sync_ops);
+
+ debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
+ adev, _trace_event_state_fops);
}
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 15/23] drm/amd/display: Separate caps for maximum RGB and YUV plane counts
From: Atufa Khan
Not all ASICs have same plane capabilities so need to split them
out for proper support handling.
Signed-off-by: Atufa Khan
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 ++
8 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2088508dac1a..d26472ef1572 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -155,6 +155,8 @@ struct dc_caps {
uint32_t max_links;
uint32_t max_audios;
uint32_t max_slave_planes;
+ uint32_t max_slave_yuv_planes;
+ uint32_t max_slave_rgb_planes;
uint32_t max_planes;
uint32_t max_downscale_ratio;
uint32_t i2c_speed_in_khz;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index d7fcc5cccdce..ef56eab4e5da 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1272,6 +1272,8 @@ static bool underlay_create(struct dc_context *ctx,
struct resource_pool *pool)
/* update the public caps to indicate an underlay is available */
ctx->dc->caps.max_slave_planes = 1;
+ ctx->dc->caps.max_slave_yuv_planes = 1;
+ ctx->dc->caps.max_slave_rgb_planes = 0;
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 33811953585b..d079f4e491e5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1422,6 +1422,8 @@ static bool dcn10_resource_construct(
dc->caps.max_cursor_size = 256;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.max_slave_planes = 1;
+ dc->caps.max_slave_yuv_planes = 1;
+ dc->caps.max_slave_rgb_planes = 0;
dc->caps.is_apu = true;
dc->caps.post_blend_color_processing = false;
dc->caps.extended_aux_timeout_support = false;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 9ae12a87d685..2307b3517821 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3703,6 +3703,8 @@ static bool dcn20_resource_construct(
dc->caps.dmdata_alloc_size = 2048;
dc->caps.max_slave_planes = 1;
+ dc->caps.max_slave_yuv_planes = 1;
+ dc->caps.max_slave_rgb_planes = 1;
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;
dc->caps.extended_aux_timeout_support = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index bd8e4c0f92db..e62f931fc269 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1982,6 +1982,8 @@ static bool dcn21_resource_construct(
dc->caps.dmdata_alloc_size = 2048;
dc->caps.max_slave_planes = 1;
+ dc->caps.max_slave_yuv_planes = 1;
+ dc->caps.max_slave_rgb_planes = 1;
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;
dc->caps.extended_aux_timeout_support = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index a3ac7e275f3d..deab48806fa2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2568,6 +2568,8 @@ static bool dcn30_resource_construct(
dc->caps.cursor_cache_size = dc->caps.max_cursor_size *
dc->caps.max_cursor_size * 8;
dc->caps.max_slave_planes = 1;
+ dc->caps.max_slave_yuv_planes = 1;
+ dc->caps.max_slave_rgb_planes = 1;
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;
dc->caps.extended_aux_timeout_support = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 6358b2b266cf..5f29a4f85ef2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dc
[PATCH 14/23] drm/amd/display: Fix no previous prototype warning
From: Wayne Lin
[Why]
Received compiling warning:
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5574:5:
warning: no previous prototype for 'amdgpu_dm_crtc_late_register'
[-Wmissing-prototypes]
5574 | int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In
function 'dm_update_mst_vcpi_slots_for_dsc':
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:6405:46:
warning: variable 'old_con_state' set but not used
[-Wunused-but-set-variable]
6405 | struct drm_connector_state *new_con_state, *old_con_state;
| ^
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In
function 'amdgpu_dm_commit_cursors':
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8006:44:
warning: variable 'new_plane_state' set but not used
[-Wunused-but-set-variable]
8006 | struct drm_plane_state *old_plane_state, *new_plane_state;
|^~~
vim +/amdgpu_dm_crtc_late_register +5574
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c
5572
5573 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
> 5574 int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
5575 {
5576 crtc_debugfs_init(crtc);
5577
5578 return 0;
5579 }
5580 #endif
5581
[How]
Fix it with declaration as "static"
Reported-by: kernel test robot
Signed-off-by: Wayne Lin
Reviewed-by: Rodrigo Siqueira
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index df060c354eb8..3db69f5bd6e9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5562,7 +5562,7 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
}
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
-int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
+static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
{
crtc_debugfs_init(crtc);
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/23] drm/amd/display: Fix secure display lock problems
From: Wayne Lin
[Why]
Find out few locks problems while doing secure display. They are
following few parts:
1. crc_rd_work_lock in amdgpu_dm_crtc_handle_crc_window_irq() should
also use spin_lock_irqsave instead of spin_lock_irq.
2. In crc_win_update_set(), crc_rd_work_lock should be grabbed after
obtaining lock event_lock. Otherwise, will cause deadlock by conflicting
the lock order in amdgpu_dm_crtc_handle_crc_window_irq()
3. flush_work() in crc_win_update_set() is no need and will cause
deadlock since amdgpu_dm_crtc_notify_ta_to_read() also tries to grab
lock crc_rd_work_lock.
[How]
Fix above problems.
Signed-off-by: Wayne Lin
Reviewed-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 10 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 ++
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index 3adbaf50a558..c6d6baab106e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -433,7 +433,7 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc
*crtc)
struct amdgpu_device *adev = NULL;
struct crc_rd_work *crc_rd_wrk = NULL;
struct crc_params *crc_window = NULL, tmp_window;
- unsigned long flags;
+ unsigned long flags1, flags2;
struct crtc_position position;
uint32_t v_blank;
uint32_t v_back_porch;
@@ -447,7 +447,7 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc
*crtc)
adev = drm_to_adev(crtc->dev);
drm_dev = crtc->dev;
- spin_lock_irqsave(_dev->event_lock, flags);
+ spin_lock_irqsave(_dev->event_lock, flags1);
stream_state = acrtc->dm_irq_params.stream;
cur_crc_src = acrtc->dm_irq_params.crc_src;
timing_out = _state->timing;
@@ -508,10 +508,10 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc
*crtc)
if
(acrtc->dm_irq_params.crc_window.skip_frame_cnt == 0) {
if (adev->dm.crc_rd_wrk) {
crc_rd_wrk =
adev->dm.crc_rd_wrk;
-
spin_lock_irq(_rd_wrk->crc_rd_work_lock);
+
spin_lock_irqsave(_rd_wrk->crc_rd_work_lock, flags2);
crc_rd_wrk->phy_inst =
stream_state->link->link_enc_hw_inst;
-
spin_unlock_irq(_rd_wrk->crc_rd_work_lock);
+
spin_unlock_irqrestore(_rd_wrk->crc_rd_work_lock, flags2);
schedule_work(_rd_wrk->notify_ta_work);
}
} else {
@@ -522,7 +522,7 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc
*crtc)
}
cleanup:
- spin_unlock_irqrestore(_dev->event_lock, flags);
+ spin_unlock_irqrestore(_dev->event_lock, flags1);
}
void amdgpu_dm_crtc_secure_display_resume(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 6d839d3fb6a3..b8644f49e0f2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -2695,14 +2695,12 @@ static int crc_win_update_set(void *data, u64 val)
struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk;
if (val) {
- spin_lock_irq(_rd_wrk->crc_rd_work_lock);
spin_lock_irq(_to_drm(adev)->event_lock);
+ spin_lock_irq(_rd_wrk->crc_rd_work_lock);
if (crc_rd_wrk && crc_rd_wrk->crtc) {
old_crtc = crc_rd_wrk->crtc;
old_acrtc = to_amdgpu_crtc(old_crtc);
- flush_work(>dm.crc_rd_wrk->notify_ta_work);
}
-
new_acrtc = to_amdgpu_crtc(new_crtc);
if (old_crtc && old_crtc != new_crtc) {
@@ -2720,8 +2718,8 @@ static int crc_win_update_set(void *data, u64 val)
new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
crc_rd_wrk->crtc = new_crtc;
}
- spin_unlock_irq(_to_drm(adev)->event_lock);
spin_unlock_irq(_rd_wrk->crc_rd_work_lock);
+ spin_unlock_irq(_to_drm(adev)->event_lock);
}
return 0;
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 12/23] drm/amd/display: Fix typo for helpers function name
From: "Leo (Hanghong) Ma"
[why]
Word "helper" was misspelled as "helpes" in
dm_helpes_dmub_outbox0_interrupt_control function.
[how]
Fix the spelling.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Yongqiang Sun
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 +-
drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index b0e49d01c206..09bdffb3a09e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -698,7 +698,7 @@ void dm_helpers_free_gpu_mem(
}
}
-bool dm_helpes_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool
enable)
+bool dm_helpers_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool
enable)
{
// TODO
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 68453c29c617..6b72af2b3f4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -180,5 +180,5 @@ bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc,
struct dmcub_trace_bu
void dc_dmub_trace_event_control(struct dc *dc, bool enable)
{
- dm_helpes_dmub_outbox0_interrupt_control(dc->ctx, enable);
+ dm_helpers_dmub_outbox0_interrupt_control(dc->ctx, enable);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index 65704f46c79b..f41db27c44de 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -156,6 +156,6 @@ void dm_set_dcn_clocks(
struct dc_context *ctx,
struct dc_clocks *clks);
-bool dm_helpes_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool
enable);
+bool dm_helpers_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool
enable);
#endif /* __DM_HELPERS__ */
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/23] drm/amd/display: Remove MPC gamut remap logic for DCN30
From: Dillon Varone
[Why?]
Should only reroute gamut remap to mpc unless 3D LUT is not used and all
planes are using the same src->dest.
[How?]
Remove DCN30 specific logic for rerouting gamut remap to mpc.
Signed-off-by: Dillon Varone
Reviewed-by: Krunoslav Kovac
Acked-by: Aric Cyr
Acked-by: Solomon Chiu
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 34 ++-
1 file changed, 2 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 0d3c7e42204f..6a10daec15cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1507,38 +1507,8 @@ static void dcn20_update_dchubp_dpp(
if (pipe_ctx->update_flags.bits.enable ||
pipe_ctx->update_flags.bits.opp_changed
|| pipe_ctx->stream->update_flags.bits.gamut_remap
|| pipe_ctx->stream->update_flags.bits.out_csc) {
- struct mpc *mpc =
pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
-
- if (mpc->funcs->set_gamut_remap) {
- int i;
- int mpcc_id = hubp->inst;
- struct mpc_grph_gamut_adjustment adjust;
- bool enable_remap_dpp = false;
-
- memset(, 0, sizeof(adjust));
- adjust.gamut_adjust_type =
GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
-
- /* save the enablement of gamut remap for dpp */
- enable_remap_dpp =
pipe_ctx->stream->gamut_remap_matrix.enable_remap;
-
- /* force bypass gamut remap for dpp/cm */
- pipe_ctx->stream->gamut_remap_matrix.enable_remap =
false;
- dc->hwss.program_gamut_remap(pipe_ctx);
-
- /* restore gamut remap flag and use this remap into mpc
*/
- pipe_ctx->stream->gamut_remap_matrix.enable_remap =
enable_remap_dpp;
-
- /* build remap matrix for top plane if enabled */
- if (enable_remap_dpp && pipe_ctx->top_pipe == NULL) {
- adjust.gamut_adjust_type =
GRAPHICS_GAMUT_ADJUST_TYPE_SW;
- for (i = 0; i <
CSC_TEMPERATURE_MATRIX_SIZE; i++)
- adjust.temperature_matrix[i] =
-
pipe_ctx->stream->gamut_remap_matrix.matrix[i];
- }
- mpc->funcs->set_gamut_remap(mpc, mpcc_id, );
- } else
- /* dpp/cm gamut remap*/
- dc->hwss.program_gamut_remap(pipe_ctx);
+ /* dpp/cm gamut remap*/
+ dc->hwss.program_gamut_remap(pipe_ctx);
/*call the dcn2 method which uses mpc csc*/
dc->hwss.program_output_csc(dc,
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 10/23] drm/amd/display: Correct algorithm for reversed gamma
From: Calvin Hou
[Why]
DCN30 needs to correctly program reversed gamma curve, which DCN20
already has.
Also needs to fix a bug that 252-255 values are clipped.
[How]
Apply two fixes into DCN30.
Signed-off-by: Calvin Hou
Reviewed-by: Jun Lei
Reviewed-by: Krunoslav Kovac
Acked-by: Solomon Chiu
Acked-by: Vladimir Stempen
---
.../amd/display/dc/dcn30/dcn30_cm_common.c| 26 +--
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
index 41a1d0e9b7e2..e0df9b0065f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
@@ -113,6 +113,7 @@ bool cm3_helper_translate_curve_to_hw_format(
struct pwl_result_data *rgb_resulted;
struct pwl_result_data *rgb;
struct pwl_result_data *rgb_plus_1;
+ struct pwl_result_data *rgb_minus_1;
struct fixed31_32 end_value;
int32_t region_start, region_end;
@@ -140,7 +141,7 @@ bool cm3_helper_translate_curve_to_hw_format(
region_start = -MAX_LOW_POINT;
region_end = NUMBER_REGIONS - MAX_LOW_POINT;
} else {
- /* 10 segments
+ /* 11 segments
* segment is from 2^-10 to 2^0
* There are less than 256 points, for optimization
*/
@@ -154,9 +155,10 @@ bool cm3_helper_translate_curve_to_hw_format(
seg_distr[7] = 4;
seg_distr[8] = 4;
seg_distr[9] = 4;
+ seg_distr[10] = 1;
region_start = -10;
- region_end = 0;
+ region_end = 1;
}
for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
@@ -189,6 +191,10 @@ bool cm3_helper_translate_curve_to_hw_format(
rgb_resulted[hw_points - 1].green =
output_tf->tf_pts.green[start_index];
rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
+ rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red;
+ rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green;
+ rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue;
+
// All 3 color channels have same x
corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
dc_fixpt_from_int(region_start));
@@ -259,15 +265,18 @@ bool cm3_helper_translate_curve_to_hw_format(
rgb = rgb_resulted;
rgb_plus_1 = rgb_resulted + 1;
+ rgb_minus_1 = rgb;
i = 1;
while (i != hw_points + 1) {
- if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
- rgb_plus_1->red = rgb->red;
- if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
- rgb_plus_1->green = rgb->green;
- if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
- rgb_plus_1->blue = rgb->blue;
+ if (i >= hw_points - 1) {
+ if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
+ rgb_plus_1->red = dc_fixpt_add(rgb->red,
rgb_minus_1->delta_red);
+ if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
+ rgb_plus_1->green = dc_fixpt_add(rgb->green,
rgb_minus_1->delta_green);
+ if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
+ rgb_plus_1->blue = dc_fixpt_add(rgb->blue,
rgb_minus_1->delta_blue);
+ }
rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
@@ -283,6 +292,7 @@ bool cm3_helper_translate_curve_to_hw_format(
}
++rgb_plus_1;
+ rgb_minus_1 = rgb;
++rgb;
++i;
}
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 09/23] drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations
From: Dillon Varone
[Why?]
Some code still expected bpp to be used in whole bits, not 16ths. dsc.c uses
redundant function now found in dc to calculate stream bandwidth from timing.
[How?]
Fix code to work with 16ths instead of whole bits for dsc bpp.
Refactor get_dsc_bandwidth to accept inputs in 16ths of a bit.
Use dc function to calculate bandwidth from timing, and make dsc bw calculation
a part of dsc.c.
Signed-off-by: Dillon Varone
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 +-
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 9 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 105 ++
3 files changed, 43 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 9337e87a73e7..30263009851e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3497,19 +3497,16 @@ void dc_link_enable_hpd_filter(struct dc_link *link,
bool enable)
}
}
+uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t
bpp_x16);
+
uint32_t dc_bandwidth_in_kbps_from_timing(
const struct dc_crtc_timing *timing)
{
uint32_t bits_per_channel = 0;
uint32_t kbps;
- struct fixed31_32 link_bw_kbps;
if (timing->flags.DSC) {
- link_bw_kbps = dc_fixpt_from_int(timing->pix_clk_100hz);
- link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160);
- link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps,
timing->dsc_cfg.bits_per_pixel);
- kbps = dc_fixpt_ceil(link_bw_kbps);
- return kbps;
+ return dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz,
timing->dsc_cfg.bits_per_pixel);
}
switch (timing->display_color_depth) {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index ec55b77727d5..0c5d98524536 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -51,6 +51,7 @@ struct dc_dsc_policy {
int min_slice_height; // Must not be less than 8
uint32_t max_target_bpp;
uint32_t min_target_bpp;
+ uint32_t preferred_bpp_x16;
bool enable_dsc_when_not_needed;
};
@@ -62,8 +63,8 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,
bool dc_dsc_compute_bandwidth_range(
const struct display_stream_compressor *dsc,
uint32_t dsc_min_slice_height_override,
- uint32_t min_bpp,
- uint32_t max_bpp,
+ uint32_t min_bpp_x16,
+ uint32_t max_bpp_x16,
const struct dsc_dec_dpcd_caps *dsc_sink_caps,
const struct dc_crtc_timing *timing,
struct dc_dsc_bw_range *range);
@@ -77,8 +78,10 @@ bool dc_dsc_compute_config(
const struct dc_crtc_timing *timing,
struct dc_dsc_config *dsc_cfg);
+uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t
bpp_x16);
+
void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
- uint32_t max_target_bpp_limit_override,
+ uint32_t max_target_bpp_limit_override_x16,
struct dc_dsc_policy *policy);
void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index c62d0eddc9c6..be57088d185d 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -37,59 +37,6 @@ static uint32_t dsc_policy_max_target_bpp_limit = 16;
/* default DSC policy enables DSC only when needed */
static bool dsc_policy_enable_dsc_when_not_needed;
-static uint32_t dc_dsc_bandwidth_in_kbps_from_timing(
- const struct dc_crtc_timing *timing)
-{
- uint32_t bits_per_channel = 0;
- uint32_t kbps;
-
- if (timing->flags.DSC) {
- kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
- kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
- return kbps;
- }
-
- switch (timing->display_color_depth) {
- case COLOR_DEPTH_666:
- bits_per_channel = 6;
- break;
- case COLOR_DEPTH_888:
- bits_per_channel = 8;
- break;
- case COLOR_DEPTH_101010:
- bits_per_channel = 10;
- break;
- case COLOR_DEPTH_121212:
- bits_per_channel = 12;
- break;
- case COLOR_DEPTH_141414:
- bits_per_channel = 14;
- break;
- case COLOR_DEPTH_161616:
- bits_per_channel = 16;
- break;
- default:
- break;
- }
-
- ASSERT(bits_per_channel != 0);
-
- kbp
[PATCH 08/23] drm/amd/display: Increase precision for bpp in DSC calculations
From: Jun Lei
[Why?]
Many DSC variables and related functions use whole bits for bpp.
[How?]
Change variables and related functions to use 16ths of a bit for bpp.
Signed-off-by: Dillon Varone
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 48d3ed97ead9..bcec019efa6f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -770,6 +770,7 @@ struct dc_crtc_timing {
#endif
struct dc_crtc_timing_flags flags;
+ uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of
bpp (e.g. 128 -> 8bpp) */
struct dc_dsc_config dsc_cfg;
};
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/23] drm/amd/display: Bypass sink detect when there are no eDPs connected
From: Jake Wang
[How & Why]
Check DC config to determine if there are any eDPs connected. If there
are no eDPs connected, bypass sink detect when querying eDP presence.
Signed-off-by: Jake Wang
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 3dc49964ea7f..dffd150180ec 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1096,20 +1096,19 @@ static void detect_edp_presence(struct dc *dc)
{
struct dc_link *edp_links[MAX_NUM_EDP];
struct dc_link *edp_link = NULL;
+ enum dc_connection_type type;
int i;
int edp_num;
- bool edp_sink_present = true;
get_edp_links(dc, edp_links, _num);
if (!edp_num)
return;
- if (dc->config.edp_not_connected) {
- edp_sink_present = false;
- } else {
- enum dc_connection_type type;
- for (i = 0; i < edp_num; i++) {
- edp_link = edp_links[i];
+ for (i = 0; i < edp_num; i++) {
+ edp_link = edp_links[i];
+ if (dc->config.edp_not_connected) {
+ edp_link->edp_sink_present = false;
+ } else {
dc_link_detect_sink(edp_link, );
edp_link->edp_sink_present = (type !=
dc_connection_none);
}
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 06/23] drm/amd/display: Fix for outbox1 ring buffer typecasting issue
From: Meenakshikumar Somasundaram [WHY] Compiler warning "pointer to integer of different size" reported on outbox1 ring buffer address typecasting. Reported-by: kernel test robot [HOW] Fixed the issue by typecasting with character pointer. Signed-off-by: Meenakshikumar Somasundaram Reviewed-by: Jun Lei Acked-by: Solomon Chiu --- drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index 1ee2000ad099..8ba0a9e2da54 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -508,7 +508,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, // Initialize outbox1 ring buffer rb_params.ctx = dmub; - rb_params.base_address = (void *) ((uint64_t) (mail_fb->cpu_addr) + DMUB_RB_SIZE); + rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); rb_params.capacity = DMUB_RB_SIZE; dmub_rb_init(>outbox1_rb, _params); -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 05/23] drm/amd/display: Fix UBSAN warning for not a valid value for type '_Bool'
From: Anson Jacob
[Why]
dc_cursor_position do not initialise position.translate_by_source when
crtc or plane->state->fb is NULL. UBSAN caught this error in
dce110_set_cursor_position, as the value was garbage.
[How]
Initialise dc_cursor_position structure elements to 0 in handle_cursor_update
before calling get_cursor_position.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1471
Reported-by: Lyude Paul
Signed-off-by: Anson Jacob
Reviewed-by: Aurabindo Jayamohanan Pillai
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7347a3dd66fc..df060c354eb8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7612,10 +7612,6 @@ static int get_cursor_position(struct drm_plane *plane,
struct drm_crtc *crtc,
int x, y;
int xorigin = 0, yorigin = 0;
- position->enable = false;
- position->x = 0;
- position->y = 0;
-
if (!crtc || !plane->state->fb)
return 0;
@@ -7662,7 +7658,7 @@ static void handle_cursor_update(struct drm_plane *plane,
struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state)
: NULL;
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
uint64_t address = afb ? afb->address : 0;
- struct dc_cursor_position position;
+ struct dc_cursor_position position = {0};
struct dc_cursor_attributes attributes;
int ret;
--
2.29.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
