[PATCH] drm/amdgpu/jpeg5: Add support for DPG mode

[Sonny Jiang]

From: Sonny Jiang 

Add DPG support for JPEG 5.0

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h |  31 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 159 ---
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.h |   6 +
 drivers/gpu/drm/amd/amdgpu/soc24.c   |   1 +
 4 files changed, 180 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
index aea31d61d991..f9cdd873ac9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
@@ -60,6 +60,37 @@
RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA);   
\
})
 
+#define WREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, value, indirect)  
\
+   do {
\
+   WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),
\
+regUVD_DPG_LMA_DATA, value);   
\
+   WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),
\
+regUVD_DPG_LMA_MASK, 0x);  
\
+   WREG32_SOC15(   
\
+   JPEG, GET_INST(JPEG, inst_idx), 
\
+   regUVD_DPG_LMA_CTL, 
\
+   (UVD_DPG_LMA_CTL__READ_WRITE_MASK | 
\
+offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT |
\
+indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));
\
+   } while (0)
+
+#define RREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, mask_en)  
\
+   do {
\
+   WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),
\
+   regUVD_DPG_LMA_MASK, 0x);   
\
+   WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),
\
+   regUVD_DPG_LMA_CTL, 
\
+   (UVD_DPG_LMA_CTL__MASK_EN_MASK |
\
+   offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));
\
+   RREG32_SOC15(JPEG, inst_idx, regUVD_DPG_LMA_DATA);  
\
+   } while (0)
+
+#define ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, offset, value, indirect)  
\
+   do {
\
+   *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = offset;   
\
+   *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = value;
\
+   } while (0)
+
 struct amdgpu_jpeg_reg{
unsigned jpeg_pitch[AMDGPU_MAX_JPEG_RINGS];
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c 
b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index e766b9463759..d694a276498a 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -31,6 +31,7 @@
 #include "vcn/vcn_5_0_0_offset.h"
 #include "vcn/vcn_5_0_0_sh_mask.h"
 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
+#include "jpeg_v5_0_0.h"
 
 static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -137,6 +138,10 @@ static int jpeg_v5_0_0_hw_init(void *handle)
adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
 
+   /* Skip ring test because pause DPG is not implemented. */
+   if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG)
+   return 0;
+
r = amdgpu_ring_test_helper(ring);
if (r)
return r;
@@ -235,7 +240,7 @@ static void jpeg_v5_0_0_enable_clock_gating(struct 
amdgpu_device *adev)
WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
 }
 
-static int jpeg_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev)
+static int jpeg_v5_0_0_disable_power_gating(struct amdgpu_device *adev)
 {
uint32_t data = 0;
 
@@ -248,14 +253,10 @@ static int jpeg_v5_0_0_disable_static_power_gating(struct 
amdgpu_device *adev)
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
 
-   /* keep the JPEG in static PG mode */
-   WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
-   ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);
-
return 0;
 }
 
-static int jpeg_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev)
+static int jpeg_v5_0_0_enable_power_gating(struct amdgpu_device *adev)
 {
/* enable anti hang mechanism */

[PATCH] drm/amdgpu/jpeg5: reprogram doorbell setting after power up for each playback

[Sonny Jiang]

From: Sonny Jiang 

Doorbell needs to be configured after power up during each playback

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c 
b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index 68ef29bc70e2..e766b9463759 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -137,10 +137,6 @@ static int jpeg_v5_0_0_hw_init(void *handle)
adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
 
-   WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
-   ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT 
|
-   VCN_JPEG_DB_CTRL__EN_MASK);
-
r = amdgpu_ring_test_helper(ring);
if (r)
return r;
@@ -314,6 +310,10 @@ static int jpeg_v5_0_0_start(struct amdgpu_device *adev)
JPEG_SYS_INT_EN__DJRBC0_MASK,
~JPEG_SYS_INT_EN__DJRBC0_MASK);
 
+   WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
+   ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
+   VCN_JPEG_DB_CTRL__EN_MASK);
+
WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0);
WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x0001L | 0x0002L));
WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
-- 
2.45.1

[PATCH v3] drm/amdgpu: IB test encode test package change for VCN5

[Sonny Jiang]

From: Sonny Jiang 

VCN5 session info package interface changed

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 677eb141554e..b89605b400c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -885,7 +885,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring 
*ring, uint32_t hand
ib->ptr[ib->length_dw++] = handle;
ib->ptr[ib->length_dw++] = upper_32_bits(addr);
ib->ptr[ib->length_dw++] = addr;
-   ib->ptr[ib->length_dw++] = 0x000b;
+   ib->ptr[ib->length_dw++] = 0x;
 
ib->ptr[ib->length_dw++] = 0x0014;
ib->ptr[ib->length_dw++] = 0x0002; /* task info */
@@ -952,7 +952,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct 
amdgpu_ring *ring, uint32_t han
ib->ptr[ib->length_dw++] = handle;
ib->ptr[ib->length_dw++] = upper_32_bits(addr);
ib->ptr[ib->length_dw++] = addr;
-   ib->ptr[ib->length_dw++] = 0x000b;
+   ib->ptr[ib->length_dw++] = 0x;
 
ib->ptr[ib->length_dw++] = 0x0014;
ib->ptr[ib->length_dw++] = 0x0002;
-- 
2.43.2

[PATCH] drm/amdgpu: update fw_share for VCN5

[Sonny Jiang]

kmd_fw_shared changed in VCN5

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c |  5 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 10 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 14 +++---
 3 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 2bebdaaff533..9ea341b76165 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -185,7 +185,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
bo_size += 
AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 
-   if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) {
+   if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(5, 0, 0)) {
+   fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct 
amdgpu_vcn5_fw_shared));
+   log_offset = offsetof(struct amdgpu_vcn5_fw_shared, fw_log);
+   } else if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) 
{
fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct 
amdgpu_vcn4_fw_shared));
log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log);
} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index a418393d89ec..9f06def236fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -454,6 +454,16 @@ struct amdgpu_vcn_rb_metadata {
uint8_t pad[26];
 };
 
+struct amdgpu_vcn5_fw_shared {
+   uint32_t present_flag_0;
+   uint8_t pad[12];
+   struct amdgpu_fw_shared_unified_queue_struct sq;
+   uint8_t pad1[8];
+   struct amdgpu_fw_shared_fw_logging fw_log;
+   struct amdgpu_fw_shared_rb_setup rb_setup;
+   uint8_t pad2[4];
+};
+
 #define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80
 #define VCN_BLOCK_DECODE_DISABLE_MASK 0x40
 #define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index b9455b6efa17..851975b5ce29 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -95,7 +95,7 @@ static int vcn_v5_0_0_sw_init(void *handle)
return r;
 
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-   volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+   volatile struct amdgpu_vcn5_fw_shared *fw_shared;
 
if (adev->vcn.harvest_config & (1 << i))
continue;
@@ -154,7 +154,7 @@ static int vcn_v5_0_0_sw_fini(void *handle)
 
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-   volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+   volatile struct amdgpu_vcn5_fw_shared *fw_shared;
 
if (adev->vcn.harvest_config & (1 << i))
continue;
@@ -335,7 +335,7 @@ static void vcn_v5_0_0_mc_resume(struct amdgpu_device 
*adev, int inst)
upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
-   AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
+   AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)));
 }
 
 /**
@@ -439,7 +439,7 @@ static void vcn_v5_0_0_mc_resume_dpg_mode(struct 
amdgpu_device *adev, int inst_i
VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(
VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
-   AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, 
indirect);
+   AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, 
indirect);
 
/* VCN global tiling registers */
WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(
@@ -616,7 +616,7 @@ static void vcn_v5_0_0_enable_clock_gating(struct 
amdgpu_device *adev, int inst)
  */
 static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, 
bool indirect)
 {
-   volatile struct amdgpu_vcn4_fw_shared *fw_shared = 
adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
+   volatile struct amdgpu_vcn5_fw_shared *fw_shared = 
adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
struct amdgpu_ring *ring;
uint32_t tmp;
 
@@ -713,7 +713,7 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device 
*adev, int inst_idx, b
  */
 static int vcn_v5_0_0_start(struct amdgpu_device *adev)
 {
-   volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+   volatile struct amdgpu_vcn5_fw_shared *fw_shared;
   

[PATCH v2] drm/amdgpu: IB test encode test package change for VCN5

[Sonny Jiang]

From: Sonny Jiang 

VCN5 session info package interface changed

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index bb85772b1374..2bebdaaff533 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -851,6 +851,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring 
*ring, uint32_t hand
 struct amdgpu_ib *ib_msg,
 struct dma_fence **fence)
 {
+   struct amdgpu_device *adev = ring->adev;
unsigned int ib_size_dw = 16;
struct amdgpu_job *job;
struct amdgpu_ib *ib;
@@ -882,7 +883,10 @@ static int amdgpu_vcn_enc_get_create_msg(struct 
amdgpu_ring *ring, uint32_t hand
ib->ptr[ib->length_dw++] = handle;
ib->ptr[ib->length_dw++] = upper_32_bits(addr);
ib->ptr[ib->length_dw++] = addr;
-   ib->ptr[ib->length_dw++] = 0x000b;
+   if (amdgpu_ip_version(adev, UVD_HWIP, 0) < IP_VERSION(5, 0, 0))
+   ib->ptr[ib->length_dw++] = 0x000b;
+   else
+   ib->ptr[ib->length_dw++] = 0x;
 
ib->ptr[ib->length_dw++] = 0x0014;
ib->ptr[ib->length_dw++] = 0x0002; /* task info */
@@ -918,6 +922,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct 
amdgpu_ring *ring, uint32_t han
  struct amdgpu_ib *ib_msg,
  struct dma_fence **fence)
 {
+   struct amdgpu_device *adev = ring->adev;
unsigned int ib_size_dw = 16;
struct amdgpu_job *job;
struct amdgpu_ib *ib;
@@ -949,7 +954,10 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct 
amdgpu_ring *ring, uint32_t han
ib->ptr[ib->length_dw++] = handle;
ib->ptr[ib->length_dw++] = upper_32_bits(addr);
ib->ptr[ib->length_dw++] = addr;
-   ib->ptr[ib->length_dw++] = 0x000b;
+   if (amdgpu_ip_version(adev, UVD_HWIP, 0) < IP_VERSION(5, 0, 0))
+   ib->ptr[ib->length_dw++] = 0x000b;
+   else
+   ib->ptr[ib->length_dw++] = 0x;
 
ib->ptr[ib->length_dw++] = 0x0014;
ib->ptr[ib->length_dw++] = 0x0002;
-- 
2.43.2

[PATCH 2/2] drm/amdgpu: IB test encode test package change for VCN5

[Sonny Jiang]

From: Sonny Jiang 

VCN5 session info package interface changed

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 7d176046498f..e08aacacc43e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -882,7 +882,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring 
*ring, uint32_t hand
ib->ptr[ib->length_dw++] = handle;
ib->ptr[ib->length_dw++] = upper_32_bits(addr);
ib->ptr[ib->length_dw++] = addr;
-   ib->ptr[ib->length_dw++] = 0x000b;
+   ib->ptr[ib->length_dw++] = 0x;
 
ib->ptr[ib->length_dw++] = 0x0014;
ib->ptr[ib->length_dw++] = 0x0002; /* task info */
@@ -949,7 +949,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct 
amdgpu_ring *ring, uint32_t han
ib->ptr[ib->length_dw++] = handle;
ib->ptr[ib->length_dw++] = upper_32_bits(addr);
ib->ptr[ib->length_dw++] = addr;
-   ib->ptr[ib->length_dw++] = 0x000b;
+   ib->ptr[ib->length_dw++] = 0x;
 
ib->ptr[ib->length_dw++] = 0x0014;
ib->ptr[ib->length_dw++] = 0x0002;
-- 
2.43.2

[PATCH 1/2] drm/amdgpu: IB size alignment on VCN5

[Sonny Jiang]

From: Sonny Jiang 

VCN5 IB size alignment adjusted.

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5d1b084eb631..94ae14e0989c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -509,7 +509,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
++num_rings;
}
ib_start_alignment = 256;
-   ib_size_alignment = 4;
+   ib_size_alignment = 64;
break;
case AMDGPU_HW_IP_VCN_JPEG:
type = (amdgpu_device_ip_get_ip_block(adev, 
AMD_IP_BLOCK_TYPE_JPEG)) ?
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index bb85772b1374..7d176046498f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -731,7 +731,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring 
*ring,
int i, r;
 
if (sq)
-   ib_size_dw += 8;
+   ib_size_dw += 16;
 
r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
@@ -861,7 +861,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring 
*ring, uint32_t hand
int i, r;
 
if (sq)
-   ib_size_dw += 8;
+   ib_size_dw += 16;
 
r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
@@ -928,7 +928,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct 
amdgpu_ring *ring, uint32_t han
int i, r;
 
if (sq)
-   ib_size_dw += 8;
+   ib_size_dw += 16;
 
r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
-- 
2.43.2

[PATCH] drm/amdgpu: vcn_4_0 set instance 0 init sched score to 1

[Sonny Jiang]

From: Sonny Jiang 

Only vcn0 can process AV1 codecx. In order to use both vcn0 and
vcn1 in h264/265 transcode to AV1 cases, set vcn0 sched score to 1
at initialization time.

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 8d371faaa2b3..b48bb5212488 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -129,7 +129,11 @@ static int vcn_v4_0_sw_init(void *handle)
if (adev->vcn.harvest_config & (1 << i))
continue;
 
-   atomic_set(&adev->vcn.inst[i].sched_score, 0);
+   /* Init instance 0 sched_score to 1, so it's scheduled after 
other instances */
+   if (i == 0)
+   atomic_set(&adev->vcn.inst[i].sched_score, 1);
+   else
+   atomic_set(&adev->vcn.inst[i].sched_score, 0);
 
/* VCN UNIFIED TRAP */
r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
-- 
2.34.1

[PATCH] drm/amdgpu: Enable VCN PG on GC11_0_1

[Sonny Jiang]

Enable VCN PG on GC11_0_1

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 16b757664a35..795706b3b092 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -629,6 +629,7 @@ static int soc21_common_early_init(void *handle)
AMD_CG_SUPPORT_JPEG_MGCG;
adev->pg_flags =
AMD_PG_SUPPORT_GFX_PG |
+   AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG;
adev->external_rev_id = adev->rev_id + 0x1;
-- 
2.36.1

[PATCH 1/2] drm/amdgpu: Enable VCN DPG for GC11_0_1

[Sonny Jiang]

Enable VCN DPG on GC11_0_1

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 5f0d6983714a..16b757664a35 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -629,6 +629,7 @@ static int soc21_common_early_init(void *handle)
AMD_CG_SUPPORT_JPEG_MGCG;
adev->pg_flags =
AMD_PG_SUPPORT_GFX_PG |
+   AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG;
adev->external_rev_id = adev->rev_id + 0x1;
break;
-- 
2.36.1

[PATCH 2/2] drm/amdgpu: Enable sram on vcn_4_0_2

[Sonny Jiang]

Enable sram on vcn_4_0_2

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index f36e4f08db6d..0b52af415b28 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -191,7 +191,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
fw_name = FIRMWARE_VCN4_0_2;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
-   adev->vcn.indirect_sram = false;
+   adev->vcn.indirect_sram = true;
break;
case IP_VERSION(4, 0, 4):
fw_name = FIRMWARE_VCN4_0_4;
-- 
2.36.1

[PATCH 5/5] drm/amdgpu: enable VCN cg and JPEG cg/pg i

[Sonny Jiang]

Not enable VCN pg because encode issue

Signed-off-by: Sonny Jiang 
Reviewed-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 68e78983f956..52816de5e17b 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -585,8 +585,11 @@ static int soc21_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x10;
break;
case IP_VERSION(11, 0, 1):
-   adev->cg_flags = 0;
-   adev->pg_flags = 0;
+   adev->cg_flags =
+   AMD_CG_SUPPORT_VCN_MGCG |
+   AMD_CG_SUPPORT_JPEG_MGCG;
+   adev->pg_flags =
+   AMD_PG_SUPPORT_JPEG;
adev->external_rev_id = adev->rev_id + 0x1;
break;
default:
-- 
2.36.1

[PATCH 1/5] drm/amdgpu: fix a vcn4 boot poll bug in emulation mode

[Sonny Jiang]

The return value should be set in vcn4 boot poll.

Signed-off-by: Sonny Jiang 
Reviewed-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index a91ffbf902d4..3a16588024d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1041,6 +1041,7 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
}
 
if (amdgpu_emu_mode==1) {
+   r = -1;
if (status & 2) {
r = 0;
break;
-- 
2.36.1

[PATCH 4/5] drm/amdgpu: vcn_4_0_2 video codec query

[Sonny Jiang]

Enable support for vcn_4_0_2 video codec

Signed-off-by: Sonny Jiang 
Reviewed-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 00e9b7089feb..68e78983f956 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -80,6 +80,7 @@ static int soc21_query_video_codecs(struct amdgpu_device 
*adev, bool encode,
switch (adev->ip_versions[UVD_HWIP][0]) {
 
case IP_VERSION(4, 0, 0):
+   case IP_VERSION(4, 0, 2):
if (encode)
*codecs = &vcn_4_0_0_video_codecs_encode;
else
-- 
2.36.1

[PATCH 3/5] drm/amdgpu: add VCN_4_0_2 firmware support i

[Sonny Jiang]

Add VCN_4_0_2 firmware support

Signed-off-by: Sonny Jiang 
Reviewed-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 1bfdfb9207ac..f36e4f08db6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -54,6 +54,7 @@
 #define FIRMWARE_YELLOW_CARP   "amdgpu/yellow_carp_vcn.bin"
 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin"
 #define FIRMWARE_VCN4_0_0  "amdgpu/vcn_4_0_0.bin"
+#define FIRMWARE_VCN4_0_2  "amdgpu/vcn_4_0_2.bin"
 #define FIRMWARE_VCN4_0_4  "amdgpu/vcn_4_0_4.bin"
 
 MODULE_FIRMWARE(FIRMWARE_RAVEN);
@@ -74,6 +75,7 @@ MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0);
+MODULE_FIRMWARE(FIRMWARE_VCN4_0_2);
 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4);
 
 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
@@ -185,6 +187,12 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
+   case IP_VERSION(4, 0, 2):
+   fw_name = FIRMWARE_VCN4_0_2;
+   if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
+   (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
+   adev->vcn.indirect_sram = false;
+   break;
case IP_VERSION(4, 0, 4):
fw_name = FIRMWARE_VCN4_0_4;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
-- 
2.36.1

[PATCH 2/5] drm/amdgpu: add VCN function in NBIO v7.7

[Sonny Jiang]

Add function to support VCN_4_0_2 doorbell

Signed-off-by: Sonny Jiang 
Reviewed-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
index e786b825cea9..01e8288d09a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
@@ -83,6 +83,26 @@ static void nbio_v7_7_sdma_doorbell_range(struct 
amdgpu_device *adev, int instan
WREG32_PCIE_PORT(reg, doorbell_range);
 }
 
+static void nbio_v7_7_vcn_doorbell_range(struct amdgpu_device *adev, bool 
use_doorbell,
+   int doorbell_index, int instance)
+{
+   u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
+   u32 doorbell_range = RREG32_PCIE_PORT(reg);
+
+   if (use_doorbell) {
+   doorbell_range = REG_SET_FIELD(doorbell_range,
+  GDC0_BIF_VCN0_DOORBELL_RANGE, 
OFFSET,
+  doorbell_index);
+   doorbell_range = REG_SET_FIELD(doorbell_range,
+  GDC0_BIF_VCN0_DOORBELL_RANGE, 
SIZE, 8);
+   } else {
+   doorbell_range = REG_SET_FIELD(doorbell_range,
+  GDC0_BIF_VCN0_DOORBELL_RANGE, 
SIZE, 0);
+   }
+
+   WREG32_PCIE_PORT(reg, doorbell_range);
+}
+
 static void nbio_v7_7_enable_doorbell_aperture(struct amdgpu_device *adev,
   bool enable)
 {
@@ -238,6 +258,7 @@ const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
.mc_access_enable = nbio_v7_7_mc_access_enable,
.get_memsize = nbio_v7_7_get_memsize,
.sdma_doorbell_range = nbio_v7_7_sdma_doorbell_range,
+   .vcn_doorbell_range = nbio_v7_7_vcn_doorbell_range,
.enable_doorbell_aperture = nbio_v7_7_enable_doorbell_aperture,
.enable_doorbell_selfring_aperture = 
nbio_v7_7_enable_doorbell_selfring_aperture,
.ih_doorbell_range = nbio_v7_7_ih_doorbell_range,
-- 
2.36.1

[PATCH v2] drm/amdgpu: limiting AV1 to first instance on VCN4 decode

[Sonny Jiang]

AV1 is only supported on first instance.

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 131 ++
 1 file changed, 131 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 84ac2401895a..a91ffbf902d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -25,6 +25,7 @@
 #include "amdgpu.h"
 #include "amdgpu_vcn.h"
 #include "amdgpu_pm.h"
+#include "amdgpu_cs.h"
 #include "soc15.h"
 #include "soc15d.h"
 #include "soc15_hw_ip.h"
@@ -44,6 +45,9 @@
 #define VCN_VID_SOC_ADDRESS_2_0
0x1fb00
 #define VCN1_VID_SOC_ADDRESS_3_0   
0x48300
 
+#define RDECODE_MSG_CREATE 
0x
+#define RDECODE_MESSAGE_CREATE 
0x0001
+
 static int amdgpu_ih_clientid_vcns[] = {
SOC15_IH_CLIENTID_VCN,
SOC15_IH_CLIENTID_VCN1
@@ -1323,6 +1327,132 @@ static void vcn_v4_0_unified_ring_set_wptr(struct 
amdgpu_ring *ring)
}
 }
 
+static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p)
+{
+   struct drm_gpu_scheduler **scheds;
+
+   /* The create msg must be in the first IB submitted */
+   if (atomic_read(&p->entity->fence_seq))
+   return -EINVAL;
+
+   scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
+   [AMDGPU_RING_PRIO_0].sched;
+   drm_sched_entity_modify_sched(p->entity, scheds, 1);
+   return 0;
+}
+
+static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr)
+{
+   struct ttm_operation_ctx ctx = { false, false };
+   struct amdgpu_bo_va_mapping *map;
+   uint32_t *msg, num_buffers;
+   struct amdgpu_bo *bo;
+   uint64_t start, end;
+   unsigned int i;
+   void *ptr;
+   int r;
+
+   addr &= AMDGPU_GMC_HOLE_MASK;
+   r = amdgpu_cs_find_mapping(p, addr, &bo, &map);
+   if (r) {
+   DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr);
+   return r;
+   }
+
+   start = map->start * AMDGPU_GPU_PAGE_SIZE;
+   end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE;
+   if (addr & 0x7) {
+   DRM_ERROR("VCN messages must be 8 byte aligned!\n");
+   return -EINVAL;
+   }
+
+   bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+   amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
+   r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+   if (r) {
+   DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);
+   return r;
+   }
+
+   r = amdgpu_bo_kmap(bo, &ptr);
+   if (r) {
+   DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);
+   return r;
+   }
+
+   msg = ptr + addr - start;
+
+   /* Check length */
+   if (msg[1] > end - addr) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   if (msg[3] != RDECODE_MSG_CREATE)
+   goto out;
+
+   num_buffers = msg[2];
+   for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) {
+   uint32_t offset, size, *create;
+
+   if (msg[0] != RDECODE_MESSAGE_CREATE)
+   continue;
+
+   offset = msg[1];
+   size = msg[2];
+
+   if (offset + size > end) {
+   r = -EINVAL;
+   goto out;
+   }
+
+   create = ptr + addr + offset - start;
+
+   /* H246, HEVC and VP9 can run on any instance */
+   if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
+   continue;
+
+   r = vcn_v4_0_limit_sched(p);
+   if (r)
+   goto out;
+   }
+
+out:
+   amdgpu_bo_kunmap(bo);
+   return r;
+}
+
+#define RADEON_VCN_ENGINE_TYPE_DECODE 
(0x0003)
+
+static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
+   struct amdgpu_job *job,
+   struct amdgpu_ib *ib)
+{
+   struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
+   struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
+   uint32_t val;
+   int r = 0;
+
+   /* The first instance can decode anything */
+   if (!ring->me)
+   return r;
+
+   /* unified queue ib header has 8 double words. */
+   if (ib->length_dw < 8)
+   return r;
+
+   val = amdgpu_ib_get_value(ib, 6); //RADEON_VCN_ENGINE_TYPE
+
+   if (val == RADEON_VCN_ENGINE_TYPE_DECO

[PATCH v2] drm/amdgpu/vcn3.0: add wptr/rptr reset/update for share memory

[Sonny Jiang]

Because of dpg, the rptr/wptr need to be saved on fw shared memory,
and restore them back in RBC_RB_RPTR/WPTR in kernel at power up.

Signed-off-by: Sonny Jiang 
Reviewed-by: Leo Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 13 +++--
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c   | 24 +++-
 2 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 13aa417f6be7..1843bf8de0cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -155,6 +155,7 @@
}   
\
} while (0)
 
+#define AMDGPU_VCN_FW_SHARED_FLAG_0_RB (1 << 6)
 #define AMDGPU_VCN_MULTI_QUEUE_FLAG(1 << 8)
 #define AMDGPU_VCN_SW_RING_FLAG(1 << 9)
 
@@ -243,6 +244,12 @@ struct amdgpu_vcn {
int inst_idx, struct dpg_pause_state *new_state);
 };
 
+struct amdgpu_fw_shared_rb_ptrs_struct {
+   /* to WA DPG R/W ptr issues.*/
+   uint32_t  rptr;
+   uint32_t  wptr;
+};
+
 struct amdgpu_fw_shared_multi_queue {
uint8_t decode_queue_mode;
uint8_t encode_generalpurpose_queue_mode;
@@ -258,10 +265,12 @@ struct amdgpu_fw_shared_sw_ring {
 
 struct amdgpu_fw_shared {
uint32_t present_flag_0;
-   uint8_t pad[53];
+   uint8_t pad[44];
+   struct amdgpu_fw_shared_rb_ptrs_struct rb;
+   uint8_t pad1[1];
struct amdgpu_fw_shared_multi_queue multi_queue;
struct amdgpu_fw_shared_sw_ring sw_ring;
-} __attribute__((__packed__));
+};
 
 struct amdgpu_vcn_decode_buffer {
uint32_t valid_buf_flag;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index def583916294..b61d1ba1aa9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -238,7 +238,8 @@ static int vcn_v3_0_sw_init(void *handle)
 
fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
fw_shared->present_flag_0 |= 
cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) |
-
cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
+
cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |
+
cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
fw_shared->sw_ring.is_enabled = 
cpu_to_le32(DEC_SW_RING_ENABLED);
}
 
@@ -1074,7 +1075,13 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device 
*adev, int inst_idx, boo
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
lower_32_bits(ring->wptr));
 
+   /* Reset FW shared memory RBC WPTR/RPTR */
+   fw_shared->rb.rptr = 0;
+   fw_shared->rb.wptr = lower_32_bits(ring->wptr);
+
+   /*resetting done, fw can check RB ring */
fw_shared->multi_queue.decode_queue_mode &= 
cpu_to_le32(~FW_QUEUE_RING_RESET);
+
/* Unstall DPG */
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
@@ -1239,9 +1246,11 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
/* Initialize the ring buffer's read and write pointers */
WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
 
+   WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0);
ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
lower_32_bits(ring->wptr));
+   fw_shared->rb.wptr = lower_32_bits(ring->wptr);
fw_shared->multi_queue.decode_queue_mode &= 
cpu_to_le32(~FW_QUEUE_RING_RESET);
 
fw_shared->multi_queue.encode_generalpurpose_queue_mode |= 
cpu_to_le32(FW_QUEUE_RING_RESET);
@@ -1662,6 +1671,10 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device 
*adev,
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, 
lower_32_bits(ring->wptr));

fw_shared->multi_queue.encode_lowlatency_queue_mode &= 
cpu_to_le32(~FW_QUEUE_RING_RESET);
 
+   /* restore wptr/rptr with pointers saved in FW 
shared memory*/
+   WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 
fw_shared->rb.rptr);
+   WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 
fw_shared->rb.wptr);
+
/* Unstall DPG */
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, 
mmUVD_POWER_STATUS),
0, 
~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
@@ -1721,6 +1734,15 @@ static uint64_t vcn_v3_0_dec_ring_get_wptr(struct 
amdgpu_ring *ring)
 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
 {

[PATCH] drm/amdgpu/vcn3.0: add wptr/rptr reset/update for share memory

[Sonny Jiang]

Because of dpg, the rptr/wptr need to be saved on fw shared memory,
and restore them back in RBC_RB_RPTR/WPTR in kernel at power up.

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 12 +++-
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c   | 24 +++-
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 13aa417f6be7..a19c0c35e2d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -155,6 +155,7 @@
}   
\
} while (0)
 
+#define AMDGPU_VCN_FW_SHARED_FLAG_0_RB (1 << 6)
 #define AMDGPU_VCN_MULTI_QUEUE_FLAG(1 << 8)
 #define AMDGPU_VCN_SW_RING_FLAG(1 << 9)
 
@@ -243,6 +244,12 @@ struct amdgpu_vcn {
int inst_idx, struct dpg_pause_state *new_state);
 };
 
+struct amdgpu_fw_shared_rb_ptrs_struct {
+   /* to WA DPG R/W ptr issues.*/
+   uint32_t  rptr;
+   uint32_t  wptr;
+};
+
 struct amdgpu_fw_shared_multi_queue {
uint8_t decode_queue_mode;
uint8_t encode_generalpurpose_queue_mode;
@@ -258,9 +265,12 @@ struct amdgpu_fw_shared_sw_ring {
 
 struct amdgpu_fw_shared {
uint32_t present_flag_0;
-   uint8_t pad[53];
+   uint8_t pad[44];
+   struct amdgpu_fw_shared_rb_ptrs_struct rb;
+   uint8_t power;
struct amdgpu_fw_shared_multi_queue multi_queue;
struct amdgpu_fw_shared_sw_ring sw_ring;
+   uint8_t padding[13];
 } __attribute__((__packed__));
 
 struct amdgpu_vcn_decode_buffer {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index def583916294..b61d1ba1aa9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -238,7 +238,8 @@ static int vcn_v3_0_sw_init(void *handle)
 
fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
fw_shared->present_flag_0 |= 
cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) |
-
cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
+
cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |
+
cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
fw_shared->sw_ring.is_enabled = 
cpu_to_le32(DEC_SW_RING_ENABLED);
}
 
@@ -1074,7 +1075,13 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device 
*adev, int inst_idx, boo
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
lower_32_bits(ring->wptr));
 
+   /* Reset FW shared memory RBC WPTR/RPTR */
+   fw_shared->rb.rptr = 0;
+   fw_shared->rb.wptr = lower_32_bits(ring->wptr);
+
+   /*resetting done, fw can check RB ring */
fw_shared->multi_queue.decode_queue_mode &= 
cpu_to_le32(~FW_QUEUE_RING_RESET);
+
/* Unstall DPG */
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
@@ -1239,9 +1246,11 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
/* Initialize the ring buffer's read and write pointers */
WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
 
+   WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0);
ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
lower_32_bits(ring->wptr));
+   fw_shared->rb.wptr = lower_32_bits(ring->wptr);
fw_shared->multi_queue.decode_queue_mode &= 
cpu_to_le32(~FW_QUEUE_RING_RESET);
 
fw_shared->multi_queue.encode_generalpurpose_queue_mode |= 
cpu_to_le32(FW_QUEUE_RING_RESET);
@@ -1662,6 +1671,10 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device 
*adev,
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, 
lower_32_bits(ring->wptr));

fw_shared->multi_queue.encode_lowlatency_queue_mode &= 
cpu_to_le32(~FW_QUEUE_RING_RESET);
 
+   /* restore wptr/rptr with pointers saved in FW 
shared memory*/
+   WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 
fw_shared->rb.rptr);
+   WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 
fw_shared->rb.wptr);
+
/* Unstall DPG */
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, 
mmUVD_POWER_STATUS),
0, 
~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
@@ -1721,6 +1734,15 @@ static uint64_t vcn_v3_0_dec_ring_get_wptr(struct 
amdgpu_ring *ring)
 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
 {
struct amdgpu_device *a

[PATCH] tests/amdgpu/vcn: clean abundant codes

[Sonny Jiang]

Remove useless codes.

Signed-off-by: Sonny Jiang 
---
 tests/amdgpu/vcn_tests.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c
index 0f5b4241..1ca66297 100644
--- a/tests/amdgpu/vcn_tests.c
+++ b/tests/amdgpu/vcn_tests.c
@@ -102,8 +102,6 @@ CU_BOOL suite_vcn_tests_enable(void)
return CU_FALSE;
 
family_id = device_handle->info.family_id;
-   chip_rev = device_handle->info.chip_rev;
-   chip_id = device_handle->info.chip_external_rev;
asic_id = device_handle->info.asic_id;
chip_rev = device_handle->info.chip_rev;
chip_id = device_handle->info.chip_external_rev;
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v3] drm/amdgpu: VCN 3.0 multiple queue ring reset

[Sonny Jiang]

Add firmware write/read point reset sync through shared memory, port from 
vcn2.5.

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 4f718ee803d0..aa1c92de7a80 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -237,7 +237,8 @@ static int vcn_v3_0_sw_init(void *handle)
}
 
fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
-   fw_shared->present_flag_0 |= 
cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG);
+   fw_shared->present_flag_0 |= 
cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) |
+
cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
fw_shared->sw_ring.is_enabled = 
cpu_to_le32(DEC_SW_RING_ENABLED);
}
 
@@ -935,6 +936,7 @@ static void vcn_v3_0_enable_clock_gating(struct 
amdgpu_device *adev, int inst)
 
 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, 
bool indirect)
 {
+   volatile struct amdgpu_fw_shared *fw_shared = 
adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
struct amdgpu_ring *ring;
uint32_t rb_bufsz, tmp;
 
@@ -1048,6 +1050,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device 
*adev, int inst_idx, boo
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
+   fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
 
/* set the write pointer delay */
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
@@ -1071,6 +1074,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device 
*adev, int inst_idx, boo
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
lower_32_bits(ring->wptr));
 
+   fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
/* Unstall DPG */
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
@@ -1080,6 +1084,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device 
*adev, int inst_idx, boo
 
 static int vcn_v3_0_start(struct amdgpu_device *adev)
 {
+   volatile struct amdgpu_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t rb_bufsz, tmp;
int i, j, k, r;
@@ -1222,6 +1227,9 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
 
+   fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
+   fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
+
/* programm the RB_BASE for ring buffer */
WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
lower_32_bits(ring->gpu_addr));
@@ -1234,19 +1242,25 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
lower_32_bits(ring->wptr));
+   fw_shared->multi_queue.decode_queue_mode &= 
~FW_QUEUE_RING_RESET;
+
+   fw_shared->multi_queue.encode_generalpurpose_queue_mode |= 
FW_QUEUE_RING_RESET;
ring = &adev->vcn.inst[i].ring_enc[0];
WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, 
upper_32_bits(ring->gpu_addr));
WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
+   fw_shared->multi_queue.encode_generalpurpose_queue_mode &= 
~FW_QUEUE_RING_RESET;
 
+   fw_shared->multi_queue.encode_lowlatency_queue_mode |= 
FW_QUEUE_RING_RESET;
ring = &adev->vcn.inst[i].ring_enc[1];
WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, 
upper_32_bits(ring->gpu_addr));
WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
+   fw_shared->multi_queue.encode_lowlatency_queue_mode &= 
~FW_QUEUE_RING_RESET;
}
 
return 0;
@@ -1595,6 +1609,7 @@ static int vcn_v3_0_stop(struct amdgpu_device *adev)
 static int vcn_v3_0_pause_dpg_mode(struct a

[PATCH v2] drm/amdgpu: VCN 3.0 multiple queue ring reset

[Sonny Jiang]

Add firmware write/read point reset sync through shared memory, port from 
vcn2.5.

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 4f718ee803d0..3eaabcfca94a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1080,6 +1080,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device 
*adev, int inst_idx, boo
 
 static int vcn_v3_0_start(struct amdgpu_device *adev)
 {
+   volatile struct amdgpu_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t rb_bufsz, tmp;
int i, j, k, r;
@@ -1222,6 +1223,9 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
 
+   fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
+   fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
+
/* programm the RB_BASE for ring buffer */
WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
lower_32_bits(ring->gpu_addr));
@@ -1234,19 +1238,25 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
lower_32_bits(ring->wptr));
+   fw_shared->multi_queue.decode_queue_mode &= 
~FW_QUEUE_RING_RESET;
+
+   fw_shared->multi_queue.encode_generalpurpose_queue_mode |= 
FW_QUEUE_RING_RESET;
ring = &adev->vcn.inst[i].ring_enc[0];
WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, 
upper_32_bits(ring->gpu_addr));
WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
+   fw_shared->multi_queue.encode_generalpurpose_queue_mode &= 
~FW_QUEUE_RING_RESET;
 
+   fw_shared->multi_queue.encode_lowlatency_queue_mode |= 
FW_QUEUE_RING_RESET;
ring = &adev->vcn.inst[i].ring_enc[1];
WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, 
upper_32_bits(ring->gpu_addr));
WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
+   fw_shared->multi_queue.encode_lowlatency_queue_mode &= 
~FW_QUEUE_RING_RESET;
}
 
return 0;
@@ -1595,6 +1605,7 @@ static int vcn_v3_0_stop(struct amdgpu_device *adev)
 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
   int inst_idx, struct dpg_pause_state *new_state)
 {
+   volatile struct amdgpu_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t reg_data = 0;
int ret_code;
@@ -1626,6 +1637,8 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device 
*adev,

~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
 
/* Restore */
+   fw_shared = 
adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
+   
fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
ring->wptr = 0;
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, 
ring->gpu_addr);
@@ -1633,7 +1646,9 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device 
*adev,
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, 
ring->ring_size / 4);
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, 
lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, 
lower_32_bits(ring->wptr));
+   
fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
 
+   
fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
ring = &adev->vcn.inst[inst_idx].ring_enc[1];
ring->wptr = 0;
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, 
ring->gpu_addr);
@@ -1641,6 +1656,7 @@ static int vcn_v3_0_pau

[PATCH] drm/amdgpu: VCN 3.0 multiple queue ring reset

[Sonny Jiang]

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 4f718ee803d0..3eaabcfca94a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1080,6 +1080,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device 
*adev, int inst_idx, boo
 
 static int vcn_v3_0_start(struct amdgpu_device *adev)
 {
+   volatile struct amdgpu_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t rb_bufsz, tmp;
int i, j, k, r;
@@ -1222,6 +1223,9 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
 
+   fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
+   fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
+
/* programm the RB_BASE for ring buffer */
WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
lower_32_bits(ring->gpu_addr));
@@ -1234,19 +1238,25 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
lower_32_bits(ring->wptr));
+   fw_shared->multi_queue.decode_queue_mode &= 
~FW_QUEUE_RING_RESET;
+
+   fw_shared->multi_queue.encode_generalpurpose_queue_mode |= 
FW_QUEUE_RING_RESET;
ring = &adev->vcn.inst[i].ring_enc[0];
WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, 
upper_32_bits(ring->gpu_addr));
WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
+   fw_shared->multi_queue.encode_generalpurpose_queue_mode &= 
~FW_QUEUE_RING_RESET;
 
+   fw_shared->multi_queue.encode_lowlatency_queue_mode |= 
FW_QUEUE_RING_RESET;
ring = &adev->vcn.inst[i].ring_enc[1];
WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, 
upper_32_bits(ring->gpu_addr));
WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
+   fw_shared->multi_queue.encode_lowlatency_queue_mode &= 
~FW_QUEUE_RING_RESET;
}
 
return 0;
@@ -1595,6 +1605,7 @@ static int vcn_v3_0_stop(struct amdgpu_device *adev)
 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
   int inst_idx, struct dpg_pause_state *new_state)
 {
+   volatile struct amdgpu_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t reg_data = 0;
int ret_code;
@@ -1626,6 +1637,8 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device 
*adev,

~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
 
/* Restore */
+   fw_shared = 
adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
+   
fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
ring->wptr = 0;
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, 
ring->gpu_addr);
@@ -1633,7 +1646,9 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device 
*adev,
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, 
ring->ring_size / 4);
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, 
lower_32_bits(ring->wptr));
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, 
lower_32_bits(ring->wptr));
+   
fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
 
+   
fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
ring = &adev->vcn.inst[inst_idx].ring_enc[1];
ring->wptr = 0;
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, 
ring->gpu_addr);
@@ -1641,6 +1656,7 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device 
*adev,
WREG32_SOC15(VCN, inst_idx, mmU

[PATCH v2] drm/amdgpu: fix SI UVD firmware validate resume fail

[Sonny Jiang]

The SI UVD firmware validate key is stored at the end of firmware,
which is changed during resume while playing video. So get the key
at sw_init and store it for fw validate using.

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h |  1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c   | 20 +++-
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index 5eb63288d157..edbb8194ee81 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -67,6 +67,7 @@ struct amdgpu_uvd {
unsignedharvest_config;
/* store image width to adjust nb memory state */
unsigneddecode_image_width;
+   uint32_tkeyselect;
 };
 
 int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
index 7cf4b11a65c5..3a5dce634cda 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
@@ -277,15 +277,8 @@ static void uvd_v3_1_mc_resume(struct amdgpu_device *adev)
  */
 static int uvd_v3_1_fw_validate(struct amdgpu_device *adev)
 {
-   void *ptr;
-   uint32_t ucode_len, i;
-   uint32_t keysel;
-
-   ptr = adev->uvd.inst[0].cpu_addr;
-   ptr += 192 + 16;
-   memcpy(&ucode_len, ptr, 4);
-   ptr += ucode_len;
-   memcpy(&keysel, ptr, 4);
+   int i;
+   uint32_t keysel = adev->uvd.keyselect;
 
WREG32(mmUVD_FW_START, keysel);
 
@@ -550,6 +543,8 @@ static int uvd_v3_1_sw_init(void *handle)
struct amdgpu_ring *ring;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;
+   void *ptr;
+   uint32_t ucode_len;
 
/* UVD TRAP */
r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, 
&adev->uvd.inst->irq);
@@ -560,6 +555,13 @@ static int uvd_v3_1_sw_init(void *handle)
if (r)
return r;
 
+   /* Retrieval firmware validate key */
+   ptr = adev->uvd.inst[0].cpu_addr;
+   ptr += 192 + 16;
+   memcpy(&ucode_len, ptr, 4);
+   ptr += ucode_len;
+   memcpy(&adev->uvd.keyselect, ptr, 4);
+
ring = &adev->uvd.inst->ring;
sprintf(ring->name, "uvd");
r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
-- 
2.25.1

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[PATCH] drm/amdgpu: fix SI UVD firmware validate resume fail

[Sonny Jiang]

The SI UVD firmware validate key is stored at the end of firmware,
which is changed during resume while playing video. So only to get
the key at device initialization and save it for later using.

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
index 7cf4b11a65c5..aab7415c1a32 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
@@ -279,13 +279,16 @@ static int uvd_v3_1_fw_validate(struct amdgpu_device 
*adev)
 {
void *ptr;
uint32_t ucode_len, i;
-   uint32_t keysel;
-
-   ptr = adev->uvd.inst[0].cpu_addr;
-   ptr += 192 + 16;
-   memcpy(&ucode_len, ptr, 4);
-   ptr += ucode_len;
-   memcpy(&keysel, ptr, 4);
+   static uint32_t keysel = 0;
+
+   /* Only get the validate key at device initialization*/
+   if (!keysel) {
+   ptr = adev->uvd.inst[0].cpu_addr;
+   ptr += 192 + 16;
+   memcpy(&ucode_len, ptr, 4);
+   ptr += ucode_len;
+   memcpy(&keysel, ptr, 4);
+   }
 
WREG32(mmUVD_FW_START, keysel);
 
-- 
2.25.1

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[PATCH 4/7] drm amdgpu: SI UVD context rreg/wreg

[Sonny Jiang]

---
 drivers/gpu/drm/amd/amdgpu/si.c | 26 --
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 153db3f763bc..f1c33395e3fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -973,6 +973,28 @@ static void si_smc_wreg(struct amdgpu_device *adev, u32 
reg, u32 v)
spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 }
 
+static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
+{
+   unsigned long flags;
+   u32 r;
+
+   spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
+   WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
+   r = RREG32(mmUVD_CTX_DATA);
+   spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
+   return r;
+}
+
+static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+{
+   unsigned long flags;
+
+   spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
+   WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
+   WREG32(mmUVD_CTX_DATA, (v));
+   spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
+}
+
 static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
{GRBM_STATUS},
{mmGRBM_STATUS2},
@@ -1443,8 +1465,8 @@ static int si_common_early_init(void *handle)
adev->pcie_wreg = &si_pcie_wreg;
adev->pciep_rreg = &si_pciep_rreg;
adev->pciep_wreg = &si_pciep_wreg;
-   adev->uvd_ctx_rreg = NULL;
-   adev->uvd_ctx_wreg = NULL;
+   adev->uvd_ctx_rreg = si_uvd_ctx_rreg;
+   adev->uvd_ctx_wreg = si_uvd_ctx_wreg;
adev->didt_rreg = NULL;
adev->didt_wreg = NULL;
 
-- 
2.25.1

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[PATCH 3/7] drm amdgpu: SI UVD v3_1

[Sonny Jiang]

---
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 792 ++
 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.h |  29 +
 2 files changed, 821 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v3_1.h

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
new file mode 100644
index ..14866f9a0e95
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
@@ -0,0 +1,792 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Sonny Jiang 
+ */
+
+#include 
+
+#include "amdgpu.h"
+#include "amdgpu_uvd.h"
+#include "sid.h"
+
+#include "uvd/uvd_3_1_d.h"
+#include "uvd/uvd_3_1_sh_mask.h"
+
+#include "oss/oss_1_0_d.h"
+#include "oss/oss_1_0_sh_mask.h"
+
+/**
+ * uvd_v3_1_ring_get_rptr - get read pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware read pointer
+ */
+static uint64_t uvd_v3_1_ring_get_rptr(struct amdgpu_ring *ring)
+{
+struct amdgpu_device *adev = ring->adev;
+
+return RREG32(mmUVD_RBC_RB_RPTR);
+}
+
+/**
+ * uvd_v3_1_ring_get_wptr - get write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware write pointer
+ */
+static uint64_t uvd_v3_1_ring_get_wptr(struct amdgpu_ring *ring)
+{
+struct amdgpu_device *adev = ring->adev;
+
+return RREG32(mmUVD_RBC_RB_WPTR);
+}
+
+/**
+ * uvd_v3_1_ring_set_wptr - set write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Commits the write pointer to the hardware
+ */
+static void uvd_v3_1_ring_set_wptr(struct amdgpu_ring *ring)
+{
+struct amdgpu_device *adev = ring->adev;
+
+WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
+}
+
+/**
+ * uvd_v3_1_ring_emit_ib - execute indirect buffer
+ *
+ * @ring: amdgpu_ring pointer
+ * @ib: indirect buffer to execute
+ *
+ * Write ring commands to execute the indirect buffer
+ */
+static void uvd_v3_1_ring_emit_ib(struct amdgpu_ring *ring,
+  struct amdgpu_job *job,
+  struct amdgpu_ib *ib,
+  uint32_t flags)
+{
+amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
+amdgpu_ring_write(ring, ib->gpu_addr);
+amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
+amdgpu_ring_write(ring, ib->length_dw);
+}
+
+/**
+ * uvd_v3_1_ring_emit_fence - emit an fence & trap command
+ *
+ * @ring: amdgpu_ring pointer
+ * @fence: fence to emit
+ *
+ * Write a fence and a trap command to the ring.
+ */
+static void uvd_v3_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 
seq,
+ unsigned flags)
+{
+WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+
+amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
+amdgpu_ring_write(ring, seq);
+amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
+amdgpu_ring_write(ring, addr & 0x);
+amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
+amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
+amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
+amdgpu_ring_write(ring, 0);
+
+amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
+amdgpu_ring_write(ring, 0);
+amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
+amdgpu_ring_write(ring, 0);
+amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
+amdgpu_ring_write(ring, 2);
+}
+
+/**
+ * uvd_v3_1_ring_test_ring - register write test
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Test if we can successfully write to the context register
+ */
+static int uvd_v3_1_ring_test_ring(struct amdgpu_ring *ring)
+{
+struct amdgpu_device *adev = ring->adev;
+uint32_t tmp = 0;
+unsign

[PATCH 1/7] drm amdgpu: SI UVD PACKET_TYPE0

[Sonny Jiang]

---
 drivers/gpu/drm/amd/amdgpu/sid.h | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h
index 7cf12adb3915..75b5d441b628 100644
--- a/drivers/gpu/drm/amd/amdgpu/sid.h
+++ b/drivers/gpu/drm/amd/amdgpu/sid.h
@@ -1646,9 +1646,10 @@
 /*
  * PM4
  */
-#define PACKET0(reg, n)((RADEON_PACKET_TYPE0 << 30) |  
\
-(((reg) >> 2) & 0x) |  \
-((n) & 0x3FFF) << 16)
+#define PACKET_TYPE00
+#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) |
\
+ ((reg) & 0x) |\
+ ((n) & 0x3FFF) << 16)
 #define CP_PACKET2 0x8000
 #definePACKET2_PAD_SHIFT   0
 #definePACKET2_PAD_MASK(0x3fff << 0)
-- 
2.25.1

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[PATCH 2/7] drm amdgpu: SI UVD registers

[Sonny Jiang]

---
 .../drm/amd/include/asic_reg/uvd/uvd_3_1_d.h  |  98 +++
 .../include/asic_reg/uvd/uvd_3_1_sh_mask.h| 804 ++
 2 files changed, 902 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h 
b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h
new file mode 100644
index ..0d78806938f2
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h
@@ -0,0 +1,98 @@
+/*
+ * UVD_3_1 Register documentation
+ *
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UVD_3_1_D_H
+#define UVD_3_1_D_H
+
+#define mmUVD_SEMA_ADDR_LOW
 0x3bc0
+#define mmUVD_SEMA_ADDR_HIGH   
 0x3bc1
+#define mmUVD_SEMA_CMD 
 0x3bc2
+#define mmUVD_GPCOM_VCPU_CMD   
 0x3bc3
+#define mmUVD_GPCOM_VCPU_DATA0 
 0x3bc4
+#define mmUVD_GPCOM_VCPU_DATA1 
 0x3bc5
+#define mmUVD_ENGINE_CNTL  
 0x3bc6
+#define mmUVD_UDEC_ADDR_CONFIG 
 0x3bd3
+#define mmUVD_UDEC_DB_ADDR_CONFIG  
 0x3bd4
+#define mmUVD_UDEC_DBW_ADDR_CONFIG 
 0x3bd5
+#define mmUVD_NO_OP
 0x3bff
+#define mmUVD_SEMA_CNTL
 0x3d00
+#define mmUVD_LMI_EXT40_ADDR   
 0x3d26
+#define mmUVD_CTX_INDEX
 0x3d28
+#define mmUVD_CTX_DATA 
 0x3d29
+#define mmUVD_CGC_GATE 
 0x3d2a
+#define mmUVD_CGC_STATUS   
 0x3d2b
+#define mmUVD_CGC_CTRL 
 0x3d2c
+#define mmUVD_CGC_UDEC_STATUS  
 0x3d2d
+#define mmUVD_LMI_CTRL2
 0x3d3d
+#define mmUVD_MASTINT_EN   
 0x3d40
+#define mmUVD_FW_START 
 0x3d47
+#define mmUVD_FW_STATUS
 0x3d57
+#define mmUVD_LMI_ADDR_EXT 
 0x3d65
+#define mmUVD_LMI_CTRL 
 0x3d66
+#define mmUVD_LMI_STATUS   
 0x3d67
+#define mmUVD_LMI_SWAP_CNTL
 0x3d6d
+#define mmUVD_MP_SWAP_CNTL 
 0x3d6f
+#define mmUVD_MPC_CNTL 
 0x3d77
+#define mmUVD_MPC_SET_MUXA0
 0x3d79
+#define mmUVD_MPC_SET_MUXA1
 0x3d7a
+#define mmUVD_MPC_SET_MUXB0
 0x3d7b
+#define mmUVD_MPC_SET_MUXB1
 0x3d7c
+#define mmUVD_MPC_SET_MUX  
 0x3d7d
+#define mmUVD_MPC_SET_ALU  
 0x3d7e
+#define mmUVD_VCPU_CACHE_OFFSET0  

[PATCH 5/7] drm amdgpu: SI UVD add uvd_v3_1 to makefile

[Sonny Jiang]

---
 drivers/gpu/drm/amd/amdgpu/Makefile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index bfcfb034aed5..403ec3db29df 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -63,7 +63,8 @@ amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
 amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o
 
-amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o 
dce_v6_0.o si_dpm.o si_smc.o
+amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o 
dce_v6_0.o si_dpm.o si_smc.o \
+   uvd_v3_1.o
 
 amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o 
vega10_reg_init.o \
-- 
2.25.1

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[PATCH 6/7] drm amdgpu: SI UVD enable for Oland

[Sonny Jiang]

---
 drivers/gpu/drm/amd/amdgpu/si.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index f1c33395e3fe..e21561fbfb82 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -41,6 +41,7 @@
 #include "si_dma.h"
 #include "dce_v6_0.h"
 #include "si.h"
+#include "uvd_v3_1.h"
 #include "dce_virtual.h"
 #include "gca/gfx_6_0_d.h"
 #include "oss/oss_1_0_d.h"
@@ -2209,8 +2210,7 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
else
amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);
-
-   /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
+   amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block);
/* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
break;
case CHIP_HAINAN:
-- 
2.25.1

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[PATCH 7/7] drm amdgpu: SI UVD enabled on Verde, Tahiti, Pitcairn

[Sonny Jiang]

---
 drivers/gpu/drm/amd/amdgpu/si.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index e21561fbfb82..cda9aa5e4b9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -2196,7 +2196,7 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
else
amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);
-   /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
+   amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block);
/* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
break;
case CHIP_OLAND:
-- 
2.25.1

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[PATCH] drm amdgpu: SI UVD add Oland, Pitcairn, Verde, Tahiti firmware

[Sonny Jiang]

---
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 26 +
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 5100ebe8858d..f8bebf18ee36 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -54,6 +54,12 @@
 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
 
 /* Firmware Names */
+#ifdef CONFIG_DRM_AMDGPU_SI
+#define FIRMWARE_TAHITI"amdgpu/tahiti_uvd.bin"
+#define FIRMWARE_VERDE "amdgpu/verde_uvd.bin"
+#define FIRMWARE_PITCAIRN  "amdgpu/pitcairn_uvd.bin"
+#define FIRMWARE_OLAND "amdgpu/oland_uvd.bin"
+#endif
 #ifdef CONFIG_DRM_AMDGPU_CIK
 #define FIRMWARE_BONAIRE   "amdgpu/bonaire_uvd.bin"
 #define FIRMWARE_KABINI"amdgpu/kabini_uvd.bin"
@@ -100,6 +106,12 @@ struct amdgpu_uvd_cs_ctx {
unsigned *buf_sizes;
 };
 
+#ifdef CONFIG_DRM_AMDGPU_SI
+MODULE_FIRMWARE(FIRMWARE_TAHITI);
+MODULE_FIRMWARE(FIRMWARE_VERDE);
+MODULE_FIRMWARE(FIRMWARE_PITCAIRN);
+MODULE_FIRMWARE(FIRMWARE_OLAND);
+#endif
 #ifdef CONFIG_DRM_AMDGPU_CIK
 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
 MODULE_FIRMWARE(FIRMWARE_KABINI);
@@ -133,6 +145,20 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
 
switch (adev->asic_type) {
+#ifdef CONFIG_DRM_AMDGPU_SI
+   case CHIP_TAHITI:
+   fw_name = FIRMWARE_TAHITI;
+   break;
+   case CHIP_VERDE:
+   fw_name = FIRMWARE_VERDE;
+   break;
+   case CHIP_PITCAIRN:
+   fw_name = FIRMWARE_PITCAIRN;
+   break;
+   case CHIP_OLAND:
+   fw_name = FIRMWARE_OLAND;
+   break;
+#endif
 #ifdef CONFIG_DRM_AMDGPU_CIK
case CHIP_BONAIRE:
fw_name = FIRMWARE_BONAIRE;
-- 
2.25.1

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[PATCH v2] drm/amdgpu: remove internal/unused kernel module parameters

[Sonny Jiang]

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  3 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12 
 2 files changed, 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d852d11..a9f09da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -106,11 +106,8 @@ extern int amdgpu_vm_fault_stop;
 extern int amdgpu_vm_debug;
 extern int amdgpu_vm_update_mode;
 extern int amdgpu_dc;
-extern int amdgpu_dc_log;
 extern int amdgpu_sched_jobs;
 extern int amdgpu_sched_hw_submission;
-extern int amdgpu_no_evict;
-extern int amdgpu_direct_gma_size;
 extern uint amdgpu_pcie_gen_cap;
 extern uint amdgpu_pcie_lane_cap;
 extern uint amdgpu_cg_mask;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 529500c..8843a06 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -104,11 +104,8 @@ int amdgpu_vram_page_split = 512;
 int amdgpu_vm_update_mode = -1;
 int amdgpu_exp_hw_support = 0;
 int amdgpu_dc = -1;
-int amdgpu_dc_log = 0;
 int amdgpu_sched_jobs = 32;
 int amdgpu_sched_hw_submission = 2;
-int amdgpu_no_evict = 0;
-int amdgpu_direct_gma_size = 0;
 uint amdgpu_pcie_gen_cap = 0;
 uint amdgpu_pcie_lane_cap = 0;
 uint amdgpu_cg_mask = 0x;
@@ -341,9 +338,6 @@ module_param_named(exp_hw_support, amdgpu_exp_hw_support, 
int, 0444);
 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto 
(default))");
 module_param_named(dc, amdgpu_dc, int, 0444);
 
-MODULE_PARM_DESC(dc_log, "Display Core Log Level (0 = minimal (default), 1 = 
chatty");
-module_param_named(dc_log, amdgpu_dc_log, int, 0444);
-
 /**
  * DOC: sched_jobs (int)
  * Override the max number of jobs supported in the sw queue. The default is 
32.
@@ -366,12 +360,6 @@ module_param_named(sched_hw_submission, 
amdgpu_sched_hw_submission, int, 0444);
 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
 
-MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = 
enable, 0 = disable (default))");
-module_param_named(no_evict, amdgpu_no_evict, int, 0444);
-
-MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
-module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
-
 /**
  * DOC: pcie_gen_cap (uint)
  * Override PCIE gen speed capabilities. See the CAIL flags in 
drivers/gpu/drm/amd/include/amd_pcie.h.
-- 
2.7.4

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[PATCH] drm/amdgpu: remove internal/unused kernel module parameters

[Sonny Jiang]

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 16 
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c |  6 --
 3 files changed, 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d852d11..e15fa64 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -106,11 +106,8 @@ extern int amdgpu_vm_fault_stop;
 extern int amdgpu_vm_debug;
 extern int amdgpu_vm_update_mode;
 extern int amdgpu_dc;
-extern int amdgpu_dc_log;
 extern int amdgpu_sched_jobs;
 extern int amdgpu_sched_hw_submission;
-extern int amdgpu_no_evict;
-extern int amdgpu_direct_gma_size;
 extern uint amdgpu_pcie_gen_cap;
 extern uint amdgpu_pcie_lane_cap;
 extern uint amdgpu_cg_mask;
@@ -127,7 +124,6 @@ extern int amdgpu_cntl_sb_buf_per_se;
 extern int amdgpu_param_buf_per_se;
 extern int amdgpu_job_hang_limit;
 extern int amdgpu_lbpw;
-extern int amdgpu_compute_multipipe;
 extern int amdgpu_gpu_recovery;
 extern int amdgpu_emu_mode;
 extern uint amdgpu_smu_memory_pool_size;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 529500c..de8a2ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -104,11 +104,8 @@ int amdgpu_vram_page_split = 512;
 int amdgpu_vm_update_mode = -1;
 int amdgpu_exp_hw_support = 0;
 int amdgpu_dc = -1;
-int amdgpu_dc_log = 0;
 int amdgpu_sched_jobs = 32;
 int amdgpu_sched_hw_submission = 2;
-int amdgpu_no_evict = 0;
-int amdgpu_direct_gma_size = 0;
 uint amdgpu_pcie_gen_cap = 0;
 uint amdgpu_pcie_lane_cap = 0;
 uint amdgpu_cg_mask = 0x;
@@ -125,7 +122,6 @@ int amdgpu_cntl_sb_buf_per_se = 0;
 int amdgpu_param_buf_per_se = 0;
 int amdgpu_job_hang_limit = 0;
 int amdgpu_lbpw = -1;
-int amdgpu_compute_multipipe = -1;
 int amdgpu_gpu_recovery = -1; /* auto */
 int amdgpu_emu_mode = 0;
 uint amdgpu_smu_memory_pool_size = 0;
@@ -341,9 +337,6 @@ module_param_named(exp_hw_support, amdgpu_exp_hw_support, 
int, 0444);
 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto 
(default))");
 module_param_named(dc, amdgpu_dc, int, 0444);
 
-MODULE_PARM_DESC(dc_log, "Display Core Log Level (0 = minimal (default), 1 = 
chatty");
-module_param_named(dc_log, amdgpu_dc_log, int, 0444);
-
 /**
  * DOC: sched_jobs (int)
  * Override the max number of jobs supported in the sw queue. The default is 
32.
@@ -366,12 +359,6 @@ module_param_named(sched_hw_submission, 
amdgpu_sched_hw_submission, int, 0444);
 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
 
-MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = 
enable, 0 = disable (default))");
-module_param_named(no_evict, amdgpu_no_evict, int, 0444);
-
-MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
-module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
-
 /**
  * DOC: pcie_gen_cap (uint)
  * Override PCIE gen speed capabilities. See the CAIL flags in 
drivers/gpu/drm/amd/include/amd_pcie.h.
@@ -478,9 +465,6 @@ module_param_named(job_hang_limit, amdgpu_job_hang_limit, 
int ,0444);
 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 
= disable, -1 = auto)");
 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
 
-MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across 
pipes (1 = enable, 0 = disable, -1 = auto)");
-module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
-
 /**
  * DOC: gpu_recovery (int)
  * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default 
is -1 (auto, disabled except SRIOV).
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 239bf2a..581959a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -111,12 +111,6 @@ void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned 
max_se, unsigned max_s
 
 static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
 {
-   if (amdgpu_compute_multipipe != -1) {
-   DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
-amdgpu_compute_multipipe);
-   return amdgpu_compute_multipipe == 1;
-   }
-
/* FIXME: spreading the queues across pipes causes perf regressions
 * on POLARIS11 compute workloads */
if (adev->asic_type == CHIP_POLARIS11)
-- 
2.7.4

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[PATCH v5] drm/amdgpu: update documentation for amdgpu_drv.c

[Sonny Jiang]

Signed-off-by: Sonny Jiang 
Acked-by: Junwei Zhang 
Acked-by: Christian König 
---
 Documentation/gpu/amdgpu.rst|   7 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 230 +++-
 2 files changed, 230 insertions(+), 7 deletions(-)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 765c2a3..a740e49 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -5,6 +5,13 @@
 The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
 Next (GCN) architecture.
 
+Module Parameters
+=
+
+The amdgpu driver supports the following module parameters:
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+
 Core Driver Infrastructure
 ==
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 963578c..aa73040 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1,10 +1,3 @@
-/**
- * \file amdgpu_drv.c
- * AMD Amdgpu driver
- *
- * \author Gareth Hughes 
- */
-
 /*
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All Rights Reserved.
@@ -136,102 +129,239 @@ int amdgpu_gpu_recovery = -1; /* auto */
 int amdgpu_emu_mode = 0;
 uint amdgpu_smu_memory_pool_size = 0;
 
+/**
+ * DOC: vramlimit (int)
+ * Restrict the total amount of VRAM in MiB for testing.  The default is 0 
(Use full VRAM).
+ */
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 
+/**
+ * DOC: vis_vramlimit (int)
+ * Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 
0 (Use full CPU visible VRAM).
+ */
 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in 
megabytes");
 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
 
+/**
+ * DOC: gartsize (uint)
+ * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is 
-1 (The size depends on asic).
+ */
 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., 
-1=auto)");
 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
 
+/**
+ * DOC: gttsize (int)
+ * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's 
VRAM size if 3GB < VRAM < 3/4 RAM,
+ * otherwise 3/4 RAM size).
+ */
 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
 
+/**
+ * DOC: moverate (int)
+ * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
+ */
 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, 
etc., -1=auto, 0=1=disabled)");
 module_param_named(moverate, amdgpu_moverate, int, 0600);
 
+/**
+ * DOC: benchmark (int)
+ * Run benchmarks. The default is 0 (Skip benchmarks).
+ */
 MODULE_PARM_DESC(benchmark, "Run benchmark");
 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
 
+/**
+ * DOC: test (int)
+ * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, 
only set 1 to run test).
+ */
 MODULE_PARM_DESC(test, "Run tests");
 module_param_named(test, amdgpu_testing, int, 0444);
 
+/**
+ * DOC: audio (int)
+ * Set Audio. The default is -1 (Enabled), set 0 to disabled it.
+ */
 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
 module_param_named(audio, amdgpu_audio, int, 0444);
 
+/**
+ * DOC: disp_priority (int)
+ * Set display Priority (1 = normal, 2 = high). Only affects non-DC display 
handling. The default is 0 (auto).
+ */
 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = 
high)");
 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
 
+/**
+ * DOC: hw_i2c (int)
+ * To enable hw i2c engine. Only affects non-DC display handling. The default 
is 0 (Disabled).
+ */
 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
 
+/**
+ * DOC: pcie_gen2 (int)
+ * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 
(auto, enabled).
+ */
 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = 
enable)");
 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
 
+/**
+ * DOC: msi (int)
+ * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = 
disable). The default is -1 (auto, enabled).
+ */
 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
 module_param_named(msi, amdgpu_msi, int, 0444);
 
+/**
+ * DOC: lockup_timeout (int)
+ * Set GPU scheduler timeout value in ms. Value 0 is invalidated, will be 
adjusted to 1.
+ * Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). The default is 
1.
+ */
 MODULE_PARM_DESC(lockup_timeout

[PATCH v4] drm/amdgpu: update documentation for amdgpu_drv.c

[Sonny Jiang]

Signed-off-by: Sonny Jiang 
Acked-by: Junwei Zhang 
Acked-by: Christian König 
---
 Documentation/gpu/amdgpu.rst|   7 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 371 +++-
 2 files changed, 371 insertions(+), 7 deletions(-)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 765c2a3..a740e49 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -5,6 +5,13 @@
 The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
 Next (GCN) architecture.
 
+Module Parameters
+=
+
+The amdgpu driver supports the following module parameters:
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+
 Core Driver Infrastructure
 ==
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 963578c..8dbdf98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1,10 +1,3 @@
-/**
- * \file amdgpu_drv.c
- * AMD Amdgpu driver
- *
- * \author Gareth Hughes 
- */
-
 /*
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All Rights Reserved.
@@ -136,102 +129,300 @@ int amdgpu_gpu_recovery = -1; /* auto */
 int amdgpu_emu_mode = 0;
 uint amdgpu_smu_memory_pool_size = 0;
 
+/**
+ * DOC: vramlimit (int)
+ * Restrict the total amount of VRAM in MiB for testing.  The default is 0 
(Use full VRAM).
+ */
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 
+/**
+ * DOC: vis_vramlimit (int)
+ * Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 
0 (Use full CPU visible VRAM).
+ */
 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in 
megabytes");
 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
 
+/**
+ * DOC: gartsize (uint)
+ * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is 
-1 (The size depends on asic).
+ */
 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., 
-1=auto)");
 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
 
+/**
+ * DOC: gttsize (int)
+ * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's 
VRAM size if 3GB < VRAM < 3/4 RAM,
+ * otherwise 3/4 RAM size).
+ */
 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
 
+/**
+ * DOC: moverate (int)
+ * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
+ */
 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, 
etc., -1=auto, 0=1=disabled)");
 module_param_named(moverate, amdgpu_moverate, int, 0600);
 
+/**
+ * DOC: benchmark (int)
+ * Run benchmarks. The default is 0 (Skip benchmarks).
+ */
 MODULE_PARM_DESC(benchmark, "Run benchmark");
 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
 
+/**
+ * DOC: test (int)
+ * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, 
only set 1 to run test).
+ */
 MODULE_PARM_DESC(test, "Run tests");
 module_param_named(test, amdgpu_testing, int, 0444);
 
+/**
+ * DOC: audio (int)
+ * Set Audio. The default is -1 (Enabled), set 0 to disabled it.
+ */
 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
 module_param_named(audio, amdgpu_audio, int, 0444);
 
+/**
+ * DOC: disp_priority (int)
+ * Set display Priority (0 = auto, 1 = normal, 2 = high). The default is 0.
+ */
 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = 
high)");
 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
 
+/**
+ * DOC: hw_i2c (int)
+ * To enable hw i2c engine. The default is 0 (Disabled).
+ */
 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
 
+/**
+ * DOC: pcie_gen2 (int)
+ * To disable PCIE Gen2 mode (0 = disable, 1 = enable). The default is -1 
(auto, enabled).
+ */
 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = 
enable)");
 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
 
+/**
+ * DOC: msi (int)
+ * To disable MSI functionality (1 = enable, 0 = disable). The default is -1 
(auto, enabled).
+ */
 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
 module_param_named(msi, amdgpu_msi, int, 0444);
 
+/**
+ * DOC: lockup_timeout (int)
+ * Set GPU scheduler timeout value in ms. Value 0 is invalidated, will be 
adjusted to 1.
+ * Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). The default is 
1.
+ */
 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 
1)");
 module_param_named(lockup_timeout, am

[PATCH v3] drm/amdgpu: update documentation for amdgpu_drv.c

[Sonny Jiang]

Signed-off-by: Sonny Jiang 
Acked-by: Junwei Zhang 
---
 Documentation/gpu/amdgpu.rst|   7 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 370 +++-
 2 files changed, 370 insertions(+), 7 deletions(-)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 765c2a3..a740e49 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -5,6 +5,13 @@
 The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
 Next (GCN) architecture.
 
+Module Parameters
+=
+
+The amdgpu driver supports the following module parameters:
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+
 Core Driver Infrastructure
 ==
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 963578c..72874cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1,10 +1,3 @@
-/**
- * \file amdgpu_drv.c
- * AMD Amdgpu driver
- *
- * \author Gareth Hughes 
- */
-
 /*
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All Rights Reserved.
@@ -136,102 +129,299 @@ int amdgpu_gpu_recovery = -1; /* auto */
 int amdgpu_emu_mode = 0;
 uint amdgpu_smu_memory_pool_size = 0;
 
+/**
+ * DOC: vramlimit (int)
+ * Restrict the total amount of VRAM in MiB for testing.  The default is 0 
(Use full VRAM).
+ */
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 
+/**
+ * DOC: vis_vramlimit (int)
+ * Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 
0 (Use full CPU visible VRAM).
+ */
 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in 
megabytes");
 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
 
+/**
+ * DOC: gartsize (uint)
+ * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is 
-1 (The size depends on asic).
+ */
 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., 
-1=auto)");
 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
 
+/**
+ * DOC: gttsize (int)
+ * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's 
VRAM size if 3GB < VRAM < 3/4 RAM,
+ * otherwise 3/4 RAM size).
+ */
 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
 
+/**
+ * DOC: moverate (int)
+ * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
+ */
 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, 
etc., -1=auto, 0=1=disabled)");
 module_param_named(moverate, amdgpu_moverate, int, 0600);
 
+/**
+ * DOC: benchmark (int)
+ * Run benchmarks. The default is 0 (Skip benchmarks).
+ */
 MODULE_PARM_DESC(benchmark, "Run benchmark");
 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
 
+/**
+ * DOC: test (int)
+ * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, 
only set 1 to run test).
+ */
 MODULE_PARM_DESC(test, "Run tests");
 module_param_named(test, amdgpu_testing, int, 0444);
 
+/**
+ * DOC: audio (int)
+ * Set Audio. The default is -1 (Enabled), set 0 to disabled it.
+ */
 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
 module_param_named(audio, amdgpu_audio, int, 0444);
 
+/**
+ * DOC: disp_priority (int)
+ * Set display Priority (0 = auto, 1 = normal, 2 = high). The default is 0.
+ */
 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = 
high)");
 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
 
+/**
+ * DOC: hw_i2c (int)
+ * To enable hw i2c engine. The default is 0 (Disabled).
+ */
 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
 
+/**
+ * DOC: pcie_gen2 (int)
+ * To disable PCIE Gen2 mode (0 = disable, 1 = enable). The default is -1 
(auto, enabled).
+ */
 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = 
enable)");
 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
 
+/**
+ * DOC: msi (int)
+ * To disable MSI functionality (1 = enable, 0 = disable). The default is -1 
(auto, enabled).
+ */
 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
 module_param_named(msi, amdgpu_msi, int, 0444);
 
+/**
+ * DOC: lockup_timeout (int)
+ * Set GPU scheduler timeout value in ms. It must be > 0.  The default is 
1.
+ */
 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 
1)");
 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
 
+/**
+ * DOC: dpm (int)
+ * Override for dynamic power management setting (1 = enable, 0 = disable). 

[PATCH v2] drm/amdgpu: update documentation for amdgpu_drv.c

[Sonny Jiang]

Signed-off-by: Sonny Jiang 
---
 Documentation/gpu/amdgpu.rst|   7 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 222 +++-
 2 files changed, 222 insertions(+), 7 deletions(-)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 765c2a3..a740e49 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -5,6 +5,13 @@
 The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
 Next (GCN) architecture.
 
+Module Parameters
+=
+
+The amdgpu driver supports the following module parameters:
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+
 Core Driver Infrastructure
 ==
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 963578c..caf81ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1,10 +1,3 @@
-/**
- * \file amdgpu_drv.c
- * AMD Amdgpu driver
- *
- * \author Gareth Hughes 
- */
-
 /*
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All Rights Reserved.
@@ -136,102 +129,235 @@ int amdgpu_gpu_recovery = -1; /* auto */
 int amdgpu_emu_mode = 0;
 uint amdgpu_smu_memory_pool_size = 0;
 
+/**
+ * DOC: vramlimit (int)
+ * Restrict the total amount of VRAM in MiB for testing.  The default is 0 
(Use full VRAM).
+ */
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 
+/**
+ * DOC: vis_vramlimit (int)
+ * Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 
0 (Use full CPU visible VRAM).
+ */
 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in 
megabytes");
 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
 
+/**
+ * DOC: gartsize (uint)
+ * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is 
-1 (The size depends on asic).
+ */
 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., 
-1=auto)");
 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
 
+/**
+ * DOC: gttsize (int)
+ * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's 
VRAM size if 3GB < VRAM < 3/4 RAM,
+ * otherwise 3/4 RAM size).
+ */
 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
 
+/**
+ * DOC: moverate (int)
+ * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
+ */
 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, 
etc., -1=auto, 0=1=disabled)");
 module_param_named(moverate, amdgpu_moverate, int, 0600);
 
+/**
+ * DOC: benchmark (int)
+ * Run benchmarks. The default is 0 (Skip benchmarks).
+ */
 MODULE_PARM_DESC(benchmark, "Run benchmark");
 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
 
+/**
+ * DOC: test (int)
+ * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, 
only set 1 to run test).
+ */
 MODULE_PARM_DESC(test, "Run tests");
 module_param_named(test, amdgpu_testing, int, 0444);
 
+/**
+ * DOC: audio (int)
+ * Set Audio. The default is -1 (Enabled), set 0 to disabled it.
+ */
 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
 module_param_named(audio, amdgpu_audio, int, 0444);
 
+/**
+ * DOC: disp_priority (int)
+ * Set display Priority (0 = auto, 1 = normal, 2 = high). The default is 0.
+ */
 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = 
high)");
 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
 
+/**
+ * DOC: hw_i2c (int)
+ * To enable hw i2c engine. The default is 0 (Disabled).
+ */
 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
 
+/**
+ * DOC: pcie_gen2 (int)
+ * To disable PCIE Gen2 mode (0 = disable, 1 = enable). The default is -1 
(auto, enabled).
+ */
 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = 
enable)");
 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
 
+/**
+ * DOC: msi (int)
+ * To disable MSI functionality (1 = enable, 0 = disable). The default is -1 
(auto, enabled).
+ */
 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
 module_param_named(msi, amdgpu_msi, int, 0444);
 
+/**
+ * DOC: lockup_timeout (int)
+ * Set GPU scheduler timeout value in ms. It must be > 0.  The default is 
1.
+ */
 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 
1)");
 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
 
+/**
+ * DOC: dpm (int)
+ * Override for dynamic power management setting (1 = enable, 0 = disable). 
The default is -1

[PATCH] drm/amdgpu: update documentation for amdgpu_drv.c

[Sonny Jiang]

Signed-off-by: Sonny Jiang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 117 
 1 file changed, 117 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 6841497..8e418e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -81,6 +81,123 @@
 #define KMS_DRIVER_MINOR   26
 #define KMS_DRIVER_PATCHLEVEL  0
 
+/**
+ * DOC: module_parameters
+ *
+ * - vramlimit (int) - Restrict the total amount of VRAM in MiB for testing.  
The default is 0 (Use full VRAM).
+ *
+ * - vis_vramlimit (int) - Restrict the amount of CPU visible VRAM in MiB for 
testing.  The default is 0 (Use full CPU visible VRAM).
+ *
+ * - gartsize (uint) - Restrict the size of GART in Mib (32, 64, etc.) for 
testing. The default is -1 (The size depends on asic).
+ *
+ * - gttsize (int) - Restrict the size of GTT domain in MiB for testing. The 
default is -1 (3/4th the size of RAM).
+ *
+ * - moverate (int) - Set maximum buffer migration rate in MB/s. The default 
is -1 (8 MB/s).
+ *
+ * - benchmark (int) - Run benchmarks. The default is 0 (Skip benchmarks).
+ *
+ * - test (int)  - Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 
0 (Skip test, only set 1 to run test).
+ *
+ * - audio (int) - Set Audio. The default is -1 (Enabled), set 0 to disabled 
it.
+ *
+ * - disp_priority (int) - Set display Priority (0 = auto, 1 = normal, 2 = 
high). The default is 0.
+ *
+ * - hw_i2c (int) - To enable hw i2c engine. The default is 0 (Disabled).
+ *
+ * - pcie_gen2 (int) - To disable PCIE Gen2 mode (0 = disable, 1 = enable). 
The default is -1 (auto enabled).
+ *
+ * - msi (int) - To disable MSI functionality (1 = enable, 0 = disable). The 
default is -1 (auto, enabled).
+ *
+ * - lockup_timeout (int) - Set GPU scheduler timeout value in ms. It must be 
> 0.  The default is 1.
+ *
+ * - dpm (int) - Override for dynamic power management setting (1 = enable, 0 
= disable). The default is -1 (auto).
+ *
+ * - fw_load_type (int) - Set different firmware loading type for debugging (0 
= direct, 1 = SMU, 2 = PSP). The default is -1 (auto).
+ *
+ * - aspm (int) - To disable ASPM (1 = enable, 0 = disable). The default is -1 
(auto enabled).
+ *
+ * - runpm (int) - Override for runtime power management control for dGPUs in 
PX/HG laptops. The amdgpu driver can dynamically power down
+ * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). 
Setting the value to 0 disables this functionality.
+ *
+ * - ip_block_mask (uint) - Override what IP blocks are enabled on the GPU.  
Each GPU is a collection of IP blocks (gfx, display, video,
+ * etc.). Use this parameter to disable specific blocks. Note that the IP 
blocks do not have a fixed index (e.g., you might have a device
+ * with multiple instances of an IP block) so the mask is board specific. The 
default is 0x (enable all blocks on a device).
+ *
+ * - bapm (int) - To disable BAPM (0 = disable). The default -1 (auto, enabled)
+ *
+ * - deep_color (int) - Set 1 to enable Deep Color support. The default is 0 
(disabled).
+ *
+ * - vm_size (int) - Override the size of the GPU's per client virtual address 
space in GiB.  The default is -1 (automatic for each asic).
+ *
+ * - vm_fragment_size (int) - Override VM fragment size in bits (4, 5, etc. 4 
= 64K, 9 = 2M). The default is -1 (automatic for each asic).
+ *
+ * - vm_block_size (int) - Override VM page table size in bits (default 
depending on vm_size and hw setup). The default is -1 (automatic for each asic).
+ *
+ * - vm_fault_stop (int) - Stop on VM fault for debugging (0 = never, 1 = 
print first, 2 = always). The default is 0 (No stop).
+ *
+ * - vm_debug (int) - Debug VM handling (0 = disabled, 1 = enabled). The 
default is 0 (Disabled).
+ *
+ * - vm_update_mode (int) - Override VM update mode.
+ * Updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = 
Both). The default is -1 (Only in large BAR(LB) systems Compute VM tables
+ * will be updated by CPU, otherwise 0, never)
+ *
+ * - vram_page_split (int) - Override the number of pages after we split VRAM 
allocations (default 512, -1 = disable). The default is 512.
+ *
+ * - exp_hw_support (int) - Enable experimental hw support (1 = enable). The 
default is 0 (disabled).
+ *
+ * - dc (int) - Disable Display Core driver for debugging (1 = enable, 0 = 
disable). The default is -1 (automatic for each asic).
+ *
+ * - sched_jobs (int) - Override the max number of jobs supported in the sw 
queue. The default is 32.
+ *
+ * - sched_hw_submission (int) - Override the max number of HW submissions. 
The default is 2.
+ *
+ * - ppfeaturemask (uint) - Override what power features are enabled. The 
default is 0x3fff (gfxoff(bit 15), overdriver(bit 14) disabled).
+ *
+ * - pcie_gen_cap (uint) - Override PCIE gen speed capabilities. The default 
is 0 (automatic for each asic).
+ *
+ * - pcie_