Re: [PATCH] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory

[Wang, Ken]

Reviewed-by: Ken Wang<ken.w...@amd.com>


From: Junwei Zhang <jerry.zh...@amd.com>
Sent: Wednesday, January 10, 2018 4:18:30 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Ken; Zhang, Jerry
Subject: [PATCH] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved 
memory

Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ae976e3..5f2ae77 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1069,7 +1069,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
 adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, 
mmGDS_VMID0_BASE);
-   adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
+   adev->gfx.ngg.gds_reserve_addr += SOC15_REG_OFFSET(GC, 0, 
mmGDS_VMID0_SIZE);

 /* Primitive Buffer */
 r = gfx_v9_0_ngg_create_buf(adev, >gfx.ngg.buf[NGG_PRIM],
@@ -1181,13 +1181,15 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)

 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
+   PACKET3_DMA_DATA_DST_SEL(0) |
 PACKET3_DMA_DATA_SRC_SEL(2)));
 amdgpu_ring_write(ring, 0);
 amdgpu_ring_write(ring, 0);
 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
 amdgpu_ring_write(ring, 0);
-   amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
-
+   amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_DAS |
+   PACKET3_DMA_DATA_CMD_RAW_WAIT |
+   adev->gfx.ngg.gds_reserve_size);

 gfx_v9_0_write_data_to_reg(ring, 0, false,
SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 
0);
--
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Remove check which is not valid for certain VBIOS

[Wang, Ken]

It fixes some headless board VBIOS which will be failed to load.


From: Alex Deucher <alexdeuc...@gmail.com>
Sent: Wednesday, November 8, 2017 10:38:37 PM
To: Wang, Ken
Cc: amd-gfx list
Subject: Re: [PATCH] drm/amdgpu: Remove check which is not valid for certain 
VBIOS

On Wed, Nov 8, 2017 at 1:49 AM,  <ken.w...@amd.com> wrote:
> From: Ken Wang <ken.w...@amd.com>

What cases does this fix?  I'm guessing VFCT or some other platform
method for getting the vbios?

Acked-by: Alex Deucher <alexander.deuc...@amd.com>

>
> Signed-off-by: Ken Wang <ken.w...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 6 --
>  1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> index c21adf6..057e1ec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> @@ -59,12 +59,6 @@ static bool check_atom_bios(uint8_t *bios, size_t size)
> return false;
> }
>
> -   tmp = bios[0x18] | (bios[0x19] << 8);
> -   if (bios[tmp + 0x14] != 0x0) {
> -   DRM_INFO("Not an x86 BIOS ROM\n");
> -   return false;
> -   }
> -
> bios_header_start = bios[0x48] | (bios[0x49] << 8);
> if (!bios_header_start) {
> DRM_INFO("Can't locate bios header\n");
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: correct reference clock value on vega10

[Wang, Ken]

got it, I will send another patch for reviewing.


From: Alex Deucher <alexdeuc...@gmail.com>
Sent: Wednesday, October 11, 2017 9:30:01 PM
To: Wang, Ken
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu: correct reference clock value on vega10

On Wed, Oct 11, 2017 at 4:48 AM, Wang, Ken <ken.w...@amd.com> wrote:
> From: Ken Wang <ken.w...@amd.com>
>
> Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
> Signed-off-by: Ken Wang <ken.w...@amd.com>

NAK.  We use 10khz units for all other asics.  We already multiply
this by 10 in amdgpu_kms.c before sending it to userspace:
/* return all clocks in KHz */
dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;

Just return adev->clock.spll.reference_freq.

Alex


> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 6 ++
>  1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 7839677..a510c8c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -279,10 +279,8 @@ static void soc15_init_golden_registers(struct
> amdgpu_device *adev)
>  }
>  static u32 soc15_get_xclk(struct amdgpu_device *adev)
>  {
> -   if (adev->asic_type == CHIP_VEGA10)
> -   return adev->clock.spll.reference_freq/4;
> -   else
> -   return adev->clock.spll.reference_freq;
> +   /* return the value in Khz instead of 10Khz*/
> +   return adev->clock.spll.reference_freq * 10;
>  }
>
>
> --
> 2.7.4
>
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: correct reference clock value on vega10

[Wang, Ken]

From: Ken Wang 

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..a510c8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -279,10 +279,8 @@ static void soc15_init_golden_registers(struct 
amdgpu_device *adev)
 }
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
-   if (adev->asic_type == CHIP_VEGA10)
-   return adev->clock.spll.reference_freq/4;
-   else
-   return adev->clock.spll.reference_freq;
+   /* return the value in Khz instead of 10Khz*/
+   return adev->clock.spll.reference_freq * 10;
 }


--
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Fw: [PATCH] drm/amdgpu: correct reference clock value on vega10

[Wang, Ken]

Hi,

   I have to forwards the review request because git send email seems not work 
correctly on my machine.



From: ken.w...@amd.com <ken.w...@amd.com>
Sent: Friday, September 29, 2017 16:38
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Ken
Subject: [PATCH] drm/amdgpu: correct reference clock value on vega10

From: Ken Wang <ken.w...@amd.com>

Change-Id: I377029075af1e2e002f7cfd793ddd58d8610e474
Signed-off-by: Ken Wang <ken.w...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7839677..631b1e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -280,7 +280,7 @@ static void soc15_init_golden_registers(struct 
amdgpu_device *adev)
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
 if (adev->asic_type == CHIP_VEGA10)
-   return adev->clock.spll.reference_freq/4;
+   return 27000;
 else
 return adev->clock.spll.reference_freq;
 }
--
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Add GPU reset functionality for Vega10

[Wang, Ken]

sure, thanks.


From: Christian König <ckoenig.leichtzumer...@gmail.com>
Sent: Friday, September 15, 2017 4:13:45 PM
To: Wang, Ken; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Add GPU reset functionality for Vega10

Am 15.09.2017 um 09:57 schrieb ken.w...@amd.com:
> From: Ken Wang <ken.w...@amd.com>
>
> V2
>
> Signed-off-by: Ken Wang <ken.w...@amd.com>

Acked-by: Christian König <christian.koe...@amd.com>

I would give an rb, but I can't judge if the PSP stuff is actually
correct, maybe wait for Alex to have a look as well.

Regards,
Christian.

> Change-Id: I6fd2c216a84747313f18db25a444be5ed43b4f4b
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  3 ++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 21 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h|  3 +++
>   drivers/gpu/drm/amd/amdgpu/psp_v10_0.c |  7 ++
>   drivers/gpu/drm/amd/amdgpu/psp_v10_0.h |  2 ++
>   drivers/gpu/drm/amd/amdgpu/psp_v3_1.c  | 34 
> ++
>   drivers/gpu/drm/amd/amdgpu/psp_v3_1.h  |  1 +
>   drivers/gpu/drm/amd/amdgpu/soc15.c | 27 
>   8 files changed, 83 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index fc1c5437..2ad9737 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2644,7 +2644,8 @@ static bool amdgpu_need_full_reset(struct amdgpu_device 
> *adev)
>if ((adev->ip_blocks[i].version->type == 
> AMD_IP_BLOCK_TYPE_GMC) ||
>(adev->ip_blocks[i].version->type == 
> AMD_IP_BLOCK_TYPE_SMC) ||
>(adev->ip_blocks[i].version->type == 
> AMD_IP_BLOCK_TYPE_ACP) ||
> - (adev->ip_blocks[i].version->type == 
> AMD_IP_BLOCK_TYPE_DCE)) {
> + (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) 
> ||
> +  adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) 
> {
>if (adev->ip_blocks[i].status.hang) {
>DRM_INFO("Some block need full reset!\n");
>return true;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 8a1ee97..8e53650 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -62,6 +62,7 @@ static int psp_sw_init(void *handle)
>psp->cmd_submit = psp_v3_1_cmd_submit;
>psp->compare_sram_data = psp_v3_1_compare_sram_data;
>psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
> + psp->mode1_reset = psp_v3_1_mode1_reset;
>break;
>case CHIP_RAVEN:
>psp->init_microcode = psp_v10_0_init_microcode;
> @@ -72,6 +73,7 @@ static int psp_sw_init(void *handle)
>psp->ring_destroy = psp_v10_0_ring_destroy;
>psp->cmd_submit = psp_v10_0_cmd_submit;
>psp->compare_sram_data = psp_v10_0_compare_sram_data;
> + psp->mode1_reset = psp_v10_0_mode1_reset;
>break;
>default:
>return -EINVAL;
> @@ -497,6 +499,22 @@ static int psp_resume(void *handle)
>return ret;
>   }
>
> +static bool psp_check_reset(void* handle)
> +{
> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +
> + if (adev->asic_type == CHIP_VEGA10)
> + return true;
> +
> + return false;
> +}
> +
> +static int psp_reset(void* handle)
> +{
> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + return psp_mode1_reset(>psp);
> +}
> +
>   static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
>enum AMDGPU_UCODE_ID ucode_type)
>   {
> @@ -540,8 +558,9 @@ const struct amd_ip_funcs psp_ip_funcs = {
>.suspend = psp_suspend,
>.resume = psp_resume,
>.is_idle = NULL,
> + .check_soft_reset = psp_check_reset,
>.wait_for_idle = NULL,
> - .soft_reset = NULL,
> + .soft_reset = psp_reset,
>.set_clockgating_state = psp_set_clockgating_state,
>.set_powergating_state = psp_set_powergating_state,
>   };
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> index 1b7d12d..ce465455 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.

Fw: [PATCH] drm/amdgpu: Add GPU reset functionality for Vega10

[Wang, Ken]

From: ken.w...@amd.com <ken.w...@amd.com>
Sent: Friday, September 15, 2017 14:57
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Ken
Subject: [PATCH] drm/amdgpu: Add GPU reset functionality for Vega10

From: Ken Wang <ken.w...@amd.com>

Signed-off-by: Ken Wang <ken.w...@amd.com>
Change-Id: I6fd2c216a84747313f18db25a444be5ed43b4f4b
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  7 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 10 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h|  3 +++
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c |  7 ++
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.h |  2 ++
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c  | 36 ++-
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.h  |  1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c | 39 --
 8 files changed, 89 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index fc1c5437..4196786 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2883,7 +2883,7 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
 int resched;
 bool need_full_reset, vram_lost = false;

-   if (!amdgpu_check_soft_reset(adev)) {
+   if (!amdgpu_check_soft_reset(adev) && (adev->asic_type != CHIP_VEGA10)) 
{
 DRM_INFO("No hardware hang detected. Did some blocks 
stall?\n");
 return 0;
 }
@@ -2910,6 +2910,10 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)

 need_full_reset = amdgpu_need_full_reset(adev);

+   /* no soft reset for vega10 right now*/
+   if (adev->asic_type == CHIP_VEGA10)
+   need_full_reset = true;
+
 if (!need_full_reset) {
 amdgpu_pre_soft_reset(adev);
 r = amdgpu_soft_reset(adev);
@@ -2924,6 +2928,7 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
 r = amdgpu_suspend(adev);

 retry:
+
 amdgpu_atombios_scratch_regs_save(adev);
 r = amdgpu_asic_reset(adev);
 amdgpu_atombios_scratch_regs_restore(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8a1ee97..6942b89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -62,6 +62,7 @@ static int psp_sw_init(void *handle)
 psp->cmd_submit = psp_v3_1_cmd_submit;
 psp->compare_sram_data = psp_v3_1_compare_sram_data;
 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
+   psp->mode1_reset = psp_v3_1_mode1_reset;
 break;
 case CHIP_RAVEN:
 psp->init_microcode = psp_v10_0_init_microcode;
@@ -72,6 +73,7 @@ static int psp_sw_init(void *handle)
 psp->ring_destroy = psp_v10_0_ring_destroy;
 psp->cmd_submit = psp_v10_0_cmd_submit;
 psp->compare_sram_data = psp_v10_0_compare_sram_data;
+   psp->mode1_reset = psp_v10_0_mode1_reset;
 break;
 default:
 return -EINVAL;
@@ -497,6 +499,12 @@ static int psp_resume(void *handle)
 return ret;
 }

+static int psp_reset(void* handle)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   return psp_mode1_reset(>psp);
+}
+
 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 enum AMDGPU_UCODE_ID ucode_type)
 {
@@ -541,7 +549,7 @@ const struct amd_ip_funcs psp_ip_funcs = {
 .resume = psp_resume,
 .is_idle = NULL,
 .wait_for_idle = NULL,
-   .soft_reset = NULL,
+   .soft_reset = psp_reset,
 .set_clockgating_state = psp_set_clockgating_state,
 .set_powergating_state = psp_set_powergating_state,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 1b7d12d..ce465455 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -76,6 +76,7 @@ struct psp_context
   struct amdgpu_firmware_info *ucode,
   enum AMDGPU_UCODE_ID ucode_type);
 bool (*smu_reload_quirk)(struct psp_context *psp);
+   int (*mode1_reset)(struct psp_context *psp);

 /* fence buffer */
 struct amdgpu_bo *fw_pri_bo;
@@ -139,6 +140,8 @@ struct amdgpu_psp_funcs {
 ((psp)->bootloader_load_sos ? 
(psp)->bootloader_load_sos((psp)) : 0)
 #define psp_smu_reload_quirk(psp) \
 ((psp)->smu_reload_quirk ? (psp)->smu_reload_quirk((psp)) : 
false)
+#define psp_mode1_reset(psp) \
+   ((psp)->mode1_reset ? (psp)->mode1_reset((psp)) : false)

 extern co

Re: [PATCH] drm/amdgpu: Add GPU reset functionality for Vega10

[Wang, Ken]

sorry about sending duplicated review, email server seems not working properly.


From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> on behalf of 
qingqing.w...@amd.com <qingqing.w...@amd.com>
Sent: Friday, September 15, 2017 3:05:56 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Ken
Subject: [PATCH] drm/amdgpu: Add GPU reset functionality for Vega10

From: Ken Wang <ken.w...@amd.com>

Signed-off-by: Ken Wang <ken.w...@amd.com>
Change-Id: I6fd2c216a84747313f18db25a444be5ed43b4f4b
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  7 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 10 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h|  3 +++
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c |  7 ++
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.h |  2 ++
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c  | 36 ++-
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.h  |  1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c | 39 --
 8 files changed, 89 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index fc1c5437..4196786 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2883,7 +2883,7 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
 int resched;
 bool need_full_reset, vram_lost = false;

-   if (!amdgpu_check_soft_reset(adev)) {
+   if (!amdgpu_check_soft_reset(adev) && (adev->asic_type != CHIP_VEGA10)) 
{
 DRM_INFO("No hardware hang detected. Did some blocks 
stall?\n");
 return 0;
 }
@@ -2910,6 +2910,10 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)

 need_full_reset = amdgpu_need_full_reset(adev);

+   /* no soft reset for vega10 right now*/
+   if (adev->asic_type == CHIP_VEGA10)
+   need_full_reset = true;
+
 if (!need_full_reset) {
 amdgpu_pre_soft_reset(adev);
 r = amdgpu_soft_reset(adev);
@@ -2924,6 +2928,7 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
 r = amdgpu_suspend(adev);

 retry:
+
 amdgpu_atombios_scratch_regs_save(adev);
 r = amdgpu_asic_reset(adev);
 amdgpu_atombios_scratch_regs_restore(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8a1ee97..6942b89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -62,6 +62,7 @@ static int psp_sw_init(void *handle)
 psp->cmd_submit = psp_v3_1_cmd_submit;
 psp->compare_sram_data = psp_v3_1_compare_sram_data;
 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
+   psp->mode1_reset = psp_v3_1_mode1_reset;
 break;
 case CHIP_RAVEN:
 psp->init_microcode = psp_v10_0_init_microcode;
@@ -72,6 +73,7 @@ static int psp_sw_init(void *handle)
 psp->ring_destroy = psp_v10_0_ring_destroy;
 psp->cmd_submit = psp_v10_0_cmd_submit;
 psp->compare_sram_data = psp_v10_0_compare_sram_data;
+   psp->mode1_reset = psp_v10_0_mode1_reset;
 break;
 default:
 return -EINVAL;
@@ -497,6 +499,12 @@ static int psp_resume(void *handle)
 return ret;
 }

+static int psp_reset(void* handle)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   return psp_mode1_reset(>psp);
+}
+
 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 enum AMDGPU_UCODE_ID ucode_type)
 {
@@ -541,7 +549,7 @@ const struct amd_ip_funcs psp_ip_funcs = {
 .resume = psp_resume,
 .is_idle = NULL,
 .wait_for_idle = NULL,
-   .soft_reset = NULL,
+   .soft_reset = psp_reset,
 .set_clockgating_state = psp_set_clockgating_state,
 .set_powergating_state = psp_set_powergating_state,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 1b7d12d..ce465455 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -76,6 +76,7 @@ struct psp_context
   struct amdgpu_firmware_info *ucode,
   enum AMDGPU_UCODE_ID ucode_type);
 bool (*smu_reload_quirk)(struct psp_context *psp);
+   int (*mode1_reset)(struct psp_context *psp);

 /* fence buffer */
 struct amdgpu_bo *fw_pri_bo;
@@ -139,6 +140,8 @@ struct amdgpu_psp_funcs {
 ((psp)->bootloader_load_sos ? 
(psp)->bootloader_load_sos((psp)) : 0)
 #define psp_smu_reload_quirk(psp) \
 ((psp)->s

Re: [PATCH] drm/amdgpu: fix S3 failure on specific platform

[Wang, Ken]

sure, I will add the delay to io_wreg.


From: Deucher, Alexander
Sent: Tuesday, July 4, 2017 12:47:38 PM
To: Wang, Ken; amd-gfx@lists.freedesktop.org
Cc: Wang, Ken
Subject: RE: [PATCH] drm/amdgpu: fix S3 failure on specific platform

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Ken Wang
> Sent: Tuesday, July 04, 2017 12:26 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wang, Ken
> Subject: [PATCH] drm/amdgpu: fix S3 failure on specific platform
>
> Change-Id: Ie932508ad6949f8bfc7c8db1f5874d3440d09fc6
> Signed-off-by: Ken Wang <qingqing.w...@amd.com>

Do we need to add this to the io_rreg and io_wreg functions as well?  Atom uses 
them for IIO tables.  Might also want to give a brief description of the 
problem.  Something like:
Certain MC registers need a delay after writing them to properly update in the 
init sequence.
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 
>  2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index ecc33c4..54c30fe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1702,6 +1702,9 @@ struct amdgpu_device {
>/* record hw reset is performed */
>bool has_hw_reset;
>
> + /* record last mm index being written through WREG32*/
> + unsigned long last_mm_index;
> +
>  };
>
>  static inline struct amdgpu_device *amdgpu_ttm_adev(struct
> ttm_bo_device *bdev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 21e504a..24b908c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -124,6 +124,10 @@ void amdgpu_mm_wreg(struct amdgpu_device
> *adev, uint32_t reg, uint32_t v,
>  {
>trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
>
> + if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
> + adev->last_mm_index = v;
> + }
> +
>if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
> amdgpu_sriov_runtime(adev)) {
>BUG_ON(in_interrupt());
>return amdgpu_virt_kiq_wreg(adev, reg, v);
> @@ -139,6 +143,10 @@ void amdgpu_mm_wreg(struct amdgpu_device
> *adev, uint32_t reg, uint32_t v,
>writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA
> * 4));
>spin_unlock_irqrestore(>mmio_idx_lock, flags);
>}
> +
> + if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev-
> >last_mm_index == 0x5702C) {
> + udelay(500);
> + }
>  }
>
>  u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/powerplay: add support for ATOM GFXCLK table v2.

[Wang, Ken]

Reviewed-by: Ken Wang


From: amd-gfx  on behalf of Rex Zhu 

Sent: Monday, June 19, 2017 6:05:16 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/powerplay: add support for ATOM GFXCLK table v2.

Change-Id: I42e3d7b684ee903ce3ced6135f954cea0d113503
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 14 +---
 .../gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h   |  9 +
 .../amd/powerplay/hwmgr/vega10_processpptables.c   | 42 +-
 3 files changed, 51 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index d9744b6..e2e2822 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -2864,6 +2864,7 @@ static int vega10_get_pp_table_entry_callback_func(struct 
pp_hwmgr *hwmgr,
 void *state, struct pp_power_state *power_state,
 void *pp_table, uint32_t classification_flag)
 {
+   ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2;
 struct vega10_power_state *vega10_power_state =
 cast_phw_vega10_power_state(&(power_state->hardware));
 struct vega10_performance_level *performance_level;
@@ -2940,11 +2941,16 @@ static int 
vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,

 performance_level = &(vega10_power_state->performance_levels
 
[vega10_power_state->performance_level_count++]);
-
 performance_level->soc_clock = socclk_dep_table->entries
-   [state_entry->ucSocClockIndexHigh].ulClk;
-   performance_level->gfx_clock = gfxclk_dep_table->entries
+   [state_entry->ucSocClockIndexHigh].ulClk;
+   if (gfxclk_dep_table->ucRevId == 0) {
+   performance_level->gfx_clock = gfxclk_dep_table->entries
 [state_entry->ucGfxClockIndexHigh].ulClk;
+   } else if (gfxclk_dep_table->ucRevId == 1) {
+   patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 
*)gfxclk_dep_table->entries;
+   performance_level->gfx_clock = 
patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk;
+   }
+
 performance_level->mem_clock = mclk_dep_table->entries
 [state_entry->ucMemClockIndexHigh].ulMemClk;
 return 0;
@@ -3348,7 +3354,6 @@ static int 
vega10_populate_and_upload_sclk_mclk_dpm_levels(
 dpm_table->
 
gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
 value = sclk;
-
 if 
(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 
PHM_PlatformCaps_OD6PlusinACSupport) ||
 
phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -3471,7 +3476,6 @@ static int 
vega10_populate_and_upload_sclk_mclk_dpm_levels(
 return result);
 }
 }
-
 return result;
 }

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
index 52beea3..b3e6300 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
@@ -144,6 +144,15 @@
 USHORT usAVFSOffset;/* AVFS 
Voltage offset */
 } ATOM_Vega10_GFXCLK_Dependency_Record;

+typedef struct _ATOM_Vega10_GFXCLK_Dependency_Record_V2 {
+   ULONG  ulClk;
+   UCHAR  ucVddInd;
+   USHORT usCKSVOffsetandDisable;
+   USHORT usAVFSOffset;
+   UCHAR  ucACGEnable;
+   UCHAR  ucReserved[3];
+} ATOM_Vega10_GFXCLK_Dependency_Record_V2;
+
 typedef struct _ATOM_Vega10_MCLK_Dependency_Record {
 ULONG  ulMemClk;/* Clock 
Frequency */
 UCHAR  ucVddInd;/* SOC_VDD 
index */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
index 2b892e4..1623644 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
@@ -585,6 +585,7 @@ static int get_gfxclk_voltage_dependency_table(
 uint32_t table_size, i;
 struct phm_ppt_v1_clock_voltage_dependency_table
 *clk_table;
+   ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2;

 PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
 "Invalid PowerPlay Table!", return -1);
@@ -601,18 

Re: [PATCH 2/2] drm/amdgpu: fix re-program vm invalidate eng address range for mmhub on resume

[Wang, Ken]

Reviewed-by: Ken Wang <qingqing.w...@amd.com>


From: Huang Rui <ray.hu...@amd.com>
Sent: Wednesday, May 17, 2017 3:38:49 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
Cc: Zhou, David(ChunMing); Wang, Ken; Huan, Alvin; Huang, Ray
Subject: [PATCH 2/2] drm/amdgpu: fix re-program vm invalidate eng address range 
for mmhub on resume

Signed-off-by: Huang Rui <ray.hu...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index dbfe48d..8979bc2 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -386,7 +386,7 @@ static int mmhub_v1_0_suspend(void *handle)

 static int mmhub_v1_0_resume(void *handle)
 {
-   return 0;
+   return mmhub_v1_0_hw_init(handle);
 }

 static bool mmhub_v1_0_is_idle(void *handle)
--
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/powerplay: disable engine spread spectrum feature on Vega10.

[Wang, Ken]

Reviewed-by: Ken Wang 


From: amd-gfx  on behalf of Rex Zhu 

Sent: Thursday, May 4, 2017 11:33:24 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/powerplay: disable engine spread spectrum feature on 
Vega10.

Vega10 atomfirmware do not have ASIC_InternalSS_Info table
so disable this feature by default in driver.

Change-Id: I2ef2c668fb41fc6c6f448c7c0f1812baf8e7b375
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 8baa890..e24e54c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -1535,7 +1535,11 @@ static int vega10_populate_single_gfx_level(struct 
pp_hwmgr *hwmgr,
 current_gfxclk_level->FbMult =
 cpu_to_le32(dividers.ulPll_fb_mult);
 /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */
-   current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
+   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+   PHM_PlatformCaps_EngineSpreadSpectrumSupport))
+   current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
+   else
+   current_gfxclk_level->SsOn = 0;
 current_gfxclk_level->SsFbMult =
 cpu_to_le32(dividers.ulPll_ss_fbsmult);
 current_gfxclk_level->SsSlewFrac =
--
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: add cu info wave_front_size

[Wang, Ken]

Reviewed-by: Ken Wang <qingqing.w...@amd.com>


From: Junwei Zhang <jerry.zh...@amd.com>
Sent: Friday, April 28, 2017 11:10:46 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; Wang, Ken; Zhang, Jerry
Subject: [PATCH] drm/amdgpu: add cu info wave_front_size

missed that for gfx v9 info export

Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 503010a..e330009 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -986,6 +986,7 @@ struct amdgpu_gfx_config {
 struct amdgpu_cu_info {
 uint32_t number; /* total active CU number */
 uint32_t ao_cu_mask;
+   uint32_t wave_front_size;
 uint32_t bitmap[4][4];
 };

--
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

答复: [PATCH] drm/amdgpu: fix to add buffer funcs check

[Wang, Ken]

Reviewed-by: Ken Wang


发件人: amd-gfx  代表 Huang Rui 

发送时间: 2017年4月11日 10:58:21
收件人: amd-gfx@lists.freedesktop.org; Deucher, Alexander
抄送: Huang, Ray
主题: [PATCH] drm/amdgpu: fix to add buffer funcs check

This patch fixes the case when buffer funcs is empty and bo evict is
executing. It must double check buffer funcs, otherwise, a NULL
pointer dereference kernel panic will be encountered.

 BUG: unable to handle kernel NULL pointer dereference at 01a4
 IP: [] amdgpu_evict_flags+0x3d/0xf0 [amdgpu]
 PGD 0

 Oops:  [#1] SMP
 Modules linked in: amdgpu(OE) ttm drm_kms_helper drm i2c_algo_bit fb_sys_fops 
syscopyarea sysfillrect sysimgblt fmem(OE) physmem_drv(OE) rpcsec_gss_krb5 
nfsv4 nfs fscache intel_rapl x86_pkg_temp_thermal intel_powerclamp 
snd_hda_codec_realtek snd_hda_codec_hdmi snd_hda_codec_generic kvm_intel 
snd_hda_intel snd_hda_codec kvm snd_hda_core joydev eeepc_wmi asus_wmi 
sparse_keymap snd_hwdep snd_pcm irqbypass crct10dif_pclmul snd_seq_midi 
snd_seq_midi_event snd_rawmidi snd_seq crc32_pclmul snd_seq_device 
ghash_clmulni_intel aesni_intel aes_x86_64 snd_timer lrw gf128mul mei_me snd 
glue_helper ablk_helper cryptd tpm_infineon mei lpc_ich serio_raw soundcore 
shpchp mac_hid nfsd auth_rpcgss nfs_acl lockd grace coretemp sunrpc parport_pc 
ppdev lp parport autofs4 hid_generic mxm_wmi r8169 usbhid ahci
  psmouse libahci nvme mii hid nvme_core wmi video
 CPU: 3 PID: 1627 Comm: kworker/u8:17 Tainted: G   OE   4.9.0-custom #1
 Hardware name: ASUS All Series/Z87-A, BIOS 1802 01/28/2014
 Workqueue: events_unbound async_run_entry_fn
 task: 88021e7057c0 task.stack: c9000262c000
 RIP: 0010:[]  [] 
amdgpu_evict_flags+0x3d/0xf0 [amdgpu]
 RSP: 0018:c9000262fb30  EFLAGS: 00010246
 RAX:  RBX: 88021e8a5858 RCX: 
 RDX: 0001 RSI: c9000262fb58 RDI: 88021e8a5800
 RBP: c9000262fb48 R08:  R09: 88021e8a5814
 R10: 1def8f01 R11: 88021def8c80 R12: c9000262fb58
 R13: 88021d2b1990 R14:  R15: 88021e8a5858
 FS:  () GS:88022ed8() knlGS:
 CS:  0010 DS:  ES:  CR0: 80050033
 CR2: 01a4 CR3: 01c07000 CR4: 001406e0
 DR0:  DR1:  DR2: 
 DR3:  DR6: fffe0ff0 DR7: 0400

Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index e00f66a..bbbdf50 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -221,7 +221,9 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 switch (bo->mem.mem_type) {
 case TTM_PL_VRAM:
 case AMDGPU_PL_DGMA:
-   if (adev->mman.buffer_funcs_ring->ready == false) {
+   if (adev->mman.buffer_funcs &&
+   adev->mman.buffer_funcs_ring &&
+   adev->mman.buffer_funcs_ring->ready == false) {
 amdgpu_ttm_placement_from_domain(abo, 
AMDGPU_GEM_DOMAIN_CPU);
 } else {
 amdgpu_ttm_placement_from_domain(abo, 
AMDGPU_GEM_DOMAIN_GTT);
--
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

答复: [PATCH] drm/amdgpu: fix memory leak in wait_all_fence

[Wang, Ken]

Reviewed-by: Ken Wang <qingqing.w...@amd.com>


发件人: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> 代表 Chunming Zhou 
<david1.z...@amd.com>
发送时间: 2017年4月7日 11:36:18
收件人: amd-gfx@lists.freedesktop.org; Wang, Ken
抄送: Zhou, David(ChunMing)
主题: [PATCH] drm/amdgpu: fix memory leak in wait_all_fence

Change-Id: Ib3e271e00e49f10152c1b3eace981a6bf78820de
Signed-off-by: Chunming Zhou <david1.z...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 25 +++--
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index de1c4c3..d842452 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1216,22 +1216,28 @@ static int amdgpu_cs_wait_all_fences(struct 
amdgpu_device *adev,
  struct drm_amdgpu_fence *fences)
 {
 uint32_t fence_count = wait->in.fence_count;
+   struct fence **array;
 unsigned int i;
 long r = 1;

+   array = kcalloc(fence_count, sizeof(struct fence *), GFP_KERNEL);
+
+   if (array == NULL)
+   return -ENOMEM;
 for (i = 0; i < fence_count; i++) {
 struct fence *fence;
 unsigned long timeout = 
amdgpu_gem_timeout(wait->in.timeout_ns);

 fence = amdgpu_cs_get_fence(adev, filp, [i]);
-   if (IS_ERR(fence))
-   return PTR_ERR(fence);
-   else if (!fence)
+   if (IS_ERR(fence)) {
+   r = PTR_ERR(fence);
+   goto err;
+   } else if (!fence)
 continue;
-
+   array[i] = fence;
 r = kcl_fence_wait_timeout(fence, true, timeout);
 if (r < 0)
-   return r;
+   goto err;

 if (r == 0)
 break;
@@ -1240,7 +1246,14 @@ static int amdgpu_cs_wait_all_fences(struct 
amdgpu_device *adev,
 memset(wait, 0, sizeof(*wait));
 wait->out.status = (r > 0);

-   return 0;
+   r = 0;
+
+err:
+   for (i = 0; i < fence_count; i++)
+   fence_put(array[i]);
+   kfree(array);
+
+   return r;
 }

 /**
--
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

答复: [PATCH 3/3] drm/amdgpu: use domain's gpu_offset for start addr

[Wang, Ken]

Reviewed-by: Ken Wang 


发件人: amd-gfx  代表 Flora Cui 

发送时间: 2016年8月18日 13:36:59
收件人: amd-gfx@lists.freedesktop.org
抄送: Cui, Flora
主题: [PATCH 3/3] drm/amdgpu: use domain's gpu_offset for start addr

Change-Id: I77610c286af4cf77bb508136fffc0c77c7cbc34b
Signed-off-by: Flora Cui 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 8 ++--
 2 files changed, 3 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index dbab3c0..2c08e1b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -530,11 +530,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
 *gpu_addr = amdgpu_bo_gpu_offset(bo);

 if (max_offset != 0) {
-   u64 domain_start;
-   if (domain == AMDGPU_GEM_DOMAIN_VRAM)
-   domain_start = bo->adev->mc.vram_start;
-   else
-   domain_start = bo->adev->mc.gtt_start;
+   u64 domain_start = 
bo->tbo.bdev->man[mem_type].gpu_offset;
 WARN_ON_ONCE(max_offset <
  (amdgpu_bo_gpu_offset(bo) - 
domain_start));
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 105bd22..8a12b24 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -257,10 +257,8 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,

 switch (old_mem->mem_type) {
 case TTM_PL_VRAM:
-   old_start += adev->mc.vram_start;
-   break;
 case TTM_PL_TT:
-   old_start += adev->mc.gtt_start;
+   old_start += bo->bdev->man[old_mem->mem_type].gpu_offset;
 break;
 default:
 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
@@ -268,10 +266,8 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 }
 switch (new_mem->mem_type) {
 case TTM_PL_VRAM:
-   new_start += adev->mc.vram_start;
-   break;
 case TTM_PL_TT:
-   new_start += adev->mc.gtt_start;
+   new_start += bo->bdev->man[new_mem->mem_type].gpu_offset;
 break;
 default:
 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
--
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

答复: [PATCH] drm/amd/powrplay: delete code set/unset deep_sleep/power_containment.

[Wang, Ken]

Reviewed-by: Ken Wang 


发件人: amd-gfx  代表 Rex Zhu 

发送时间: 2016年8月3日 14:42:01
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhu, Rex
主题: [PATCH] drm/amd/powrplay: delete code set/unset 
deep_sleep/power_containment.

they were controled by module parameter.

Change-Id: Ia492c811191be2246bc6d2c3569ec250f1e66572
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c   | 3 ---
 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c | 2 --
 drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c  | 3 +--
 3 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 8cc0df9..4015384 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -221,9 +221,6 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr 
*hwmgr)
 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 PHM_PlatformCaps_NonABMSupportInPPLib);

-   phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-  PHM_PlatformCaps_SclkDeepSleep);
-
 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 PHM_PlatformCaps_DynamicM3Arbiter);

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
index c3b2f51..f5992ea 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
@@ -57,8 +57,6 @@ void fiji_initialize_power_tune_defaults(struct pp_hwmgr 
*hwmgr)

 /* Assume disabled */
 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-   PHM_PlatformCaps_PowerContainment);
-   phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 PHM_PlatformCaps_CAC);
 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 PHM_PlatformCaps_SQRamping);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
index d8ca59b..da87127 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
@@ -3847,8 +3847,7 @@ static int iceland_hwmgr_backend_init(struct pp_hwmgr 
*hwmgr)
 PHM_PlatformCaps_GFXClockGatingManagedInCAIL);
 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 PHM_PlatformCaps_IcelandULPSSWWorkAround);
-   phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-   PHM_PlatformCaps_PowerContainment);
+

 /* iceland doesn't support UVD and VCE */
 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

答复: [PATCH 2/2] drm/amdgpu: use the kernel zone memory size as the max remote memory in amdgpu

[Wang, Ken]

Yeah, that's could be an issue, I have changed the logic and send the review 
again.


发件人: Alex Deucher <alexdeuc...@gmail.com>
发送时间: 2016年8月2日 12:56:07
收件人: Wang, Ken
抄送: amd-gfx list
主题: Re: [PATCH 2/2] drm/amdgpu: use the kernel zone memory size as the max 
remote memory in amdgpu

On Wed, Jul 27, 2016 at 7:21 AM, Ken Wang <qingqing.w...@amd.com> wrote:
> Change-Id: Ibf193cc2d9e20c3aefa1ce8ff24241dfbb6768ff
> Signed-off-by: Ken Wang <qingqing.w...@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  2 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 12 +++-
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   |  7 ++-
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   |  7 ++-
>  4 files changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 8bef7ec..b84153f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -2432,6 +2432,8 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device 
> *adev, struct ttm_tt *ttm,
>  void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, 
> u64 base);
>  void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
>  void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
> +u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev);
> +int amdgpu_ttm_global_init(struct amdgpu_device *adev);
>  void amdgpu_program_register_sequence(struct amdgpu_device *adev,
>  const u32 *registers,
>  const u32 array_size);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 145732a..5200381 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -34,6 +34,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -74,7 +75,7 @@ static void amdgpu_ttm_mem_global_release(struct 
> drm_global_reference *ref)
> ttm_mem_global_release(ref->object);
>  }
>
> -static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
> +int amdgpu_ttm_global_init(struct amdgpu_device *adev)
>  {
> struct drm_global_reference *global_ref;
> struct amdgpu_ring *ring;
> @@ -998,10 +999,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
> unsigned i, j;
> int r;
>
> -   r = amdgpu_ttm_global_init(adev);
> -   if (r) {
> -   return r;
> -   }
> /* No others user of address space so set it to 0 */
> r = ttm_bo_device_init(>mman.bdev,
>adev->mman.bo_global_ref.ref.object,
> @@ -1398,3 +1395,8 @@ static void amdgpu_ttm_debugfs_fini(struct 
> amdgpu_device *adev)
>
>  #endif
>  }
> +
> +u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev)
> +{
> +   return 
> ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object);
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index a3b6048..b6ae925 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -392,7 +392,7 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
>  * size equal to the 1024 or vram, whichever is larger.
>  */
> if (amdgpu_gart_size == -1)
> -   adev->mc.gtt_size = max((1024ULL << 20), 
> adev->mc.mc_vram_size);
> +   adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev);

Do we want to limit this to the min(amdgpu_ttm_get_gtt_mem_size, GPU
address space - vram)?  GPU address space is only 40 bits.  You could
theoretically have systems with a lot of system memory.

Alex


> else
> adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
>
> @@ -959,6 +959,11 @@ static int gmc_v7_0_sw_init(void *handle)
> return r;
> }
>
> +   r = amdgpu_ttm_global_init(adev);
> +   if (r) {
> +   return r;
> +   }
> +
> r = gmc_v7_0_mc_init(adev);
> if (r)
> return r;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 02b6872..d46d76b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -469,7 +469,7 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
>  * size equal to the 1024 or vram, whichever is larger.
>  */
>

答复: 答复: 答复: 答复: 答复: [PATCH] drm/amdgpu: adjust gtt memory size

[Wang, Ken]

Hi Christian,

   Patches has been updated and sent for reviewing in another thread, please 
take a look.


发件人: Christian König <deathsim...@vodafone.de>
发送时间: 2016年7月22日 21:02:56
收件人: Wang, Ken; Kuehling, Felix; amd-gfx@lists.freedesktop.org
主题: Re: 答复: 答复: 答复: 答复: [PATCH] drm/amdgpu: adjust gtt memory size

Yeah sounds good to me.

Could we make a global ttm function returning how much system memory can be 
used at the same time?

This way we could make those values depend on each other, e.g. when somebody 
modifies the TTM value we automatically change the GART size as well.

Regards,
Christian.

Am 22.07.2016 um 08:06 schrieb Wang, Ken:

thanks Felix,

   I see that logci in TTM as well, so choose 1/2 of system memory as up limit 
seems good enough here? if no object I will fix the overflow issue and send the 
review again.


发件人: amd-gfx 
<amd-gfx-boun...@lists.freedesktop.org><mailto:amd-gfx-boun...@lists.freedesktop.org>
 代表 Felix Kuehling <felix.kuehl...@amd.com><mailto:felix.kuehl...@amd.com>
发送时间: 2016年7月22日 3:19:38
收件人: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
主题: Re: 答复: 答复: 答复: [PATCH] drm/amdgpu: adjust gtt memory size


TTM limits system memory allocations to 1/2 system memory for regular 
processes, or 3/4 for privileged processes.


For compute we opted to make the GART bigger than system memory to allow for 
fragmentation. However, we argued that you don't really need GART for most 
buffers anyways, since they are never accessed in VMID 0. They need to be 
mapped in some VM page table, but never in the GART table. So I think the 
long-term goal should be to remove the need to allocate GART addresses for 
system memory BOs. Then you could get away with a quite small GART size.


Regards,

  Felix

On 16-07-21 08:04 AM, Christian König wrote:

we can add people in if necessary here. so the initial though of this change is 
with latest big memory GPU released, the remote memory goes very large, like 
Polaris10.

According to the windows WDDM, remote memory size is half of the system memory, 
I don't know what was discussed before, Please let me know if there're use case 
indeed need that big of remote memory.

Well that is at least something that makes sense.

Previous discussions where always settled around making GART bigger than VRAM 
and not the other way around.

Anyway I think a prerequisite to this is actually allowing half of system 
memory to be allocated for GART and I'm not sure if that is currently the case. 
TTM has a limitation for that as well, but I off hand don't remember how high 
much it was.

I think we should use the same value which TTM uses for the upper limit here.

Regards,
Christian.

Am 21.07.2016 um 13:56 schrieb Wang, Qingqing:

alright, I didn't realize you're not in that thread.

we can add people in if necessary here. so the initial though of this change is 
with latest big memory GPU released, the remote memory goes very large, like 
Polaris10.

According to the windows WDDM, remote memory size is half of the system memory, 
I don't know what was discussed before, Please let me know if there're use case 
indeed need that big of remote memory.


发件人: Christian König <deathsim...@vodafone.de><mailto:deathsim...@vodafone.de>
发送时间: 2016年7月21日 19:48:17
收件人: Wang, Qingqing; 
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
主题: Re: 答复: 答复: [PATCH] drm/amdgpu: adjust gtt memory size

Am 21.07.2016 um 13:15 schrieb Wang, Qingqing:

Actually that discussion was held long ago internally but we never got a 
conclusion on this IIRC. So we should probably continue the discussion on this 
thread now.

-there is a thread for this topic yesterday, some people are not in amd-gfx 
mail list, we'd better discuss in the internal thread.

No, exactly for this reason we have the public mailing list. I for example 
wasn't part of the internal thread either.

Christian.


发件人: Christian König <deathsim...@vodafone.de><mailto:deathsim...@vodafone.de>
发送时间: 2016年7月21日 17:48:41
收件人: Wang, Qingqing; 
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
主题: Re: 答复: [PATCH] drm/amdgpu: adjust gtt memory size

Am 21.07.2016 um 11:16 schrieb Wang, Qingqing:

This doesn't work on 32bit systems since totalram is a long (IIRC) and
so this will certainly overflow.

-- can you be more specific, how could the overflow happen?

Both values are 32bit on a 32bit system, so as soon as you have more than 4GB 
installed this will overflow.

You need to cast the long to a 64bit value to avoid that.



Additional if I remember correctly we didn't ended the discussion on
what to do here with a conclusion.

-- ok, since it happens in anther mail list, we should stop talking about it 
here, you can send out your ideas there.

Actually tha