[PATCH] drm/amdgpu/powerplay:avoid to show invalid DPM table info

2020-04-16 Thread Yuxian Dai 
for different ASIC support different the number of DPM levels,
we should avoid to show the invalid level value.
v1 -> v2:
follow the suggestion,clarifiy the description for this
change
Signed-off-by: Yuxian Dai 
Change-Id: I579ef417ddc8acb4a6cf15c60094743a72d9b050
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 281b7b6cf1a4..e4e7a352d032 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -296,6 +296,8 @@ static int renoir_print_clk_levels(struct smu_context *smu,
 
for (i = 0; i < count; i++) {
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
+   if (!value)
+   continue;
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
if (cur_value == value)
-- 
2.17.1

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[PATCH] drm/amdgpu/powerplay:avoid to show invalid DPM table info

2020-04-16 Thread Yuxian Dai 
for different ASIC support different the number of DPM levels,
we should avoid to show the invalid level value.
v1 -> v2:
follow the suggestion,clarifiy the description for this
change
Signed-off-by: Yuxian Dai 
Change-Id: I579ef417ddc8acb4a6cf15c60094743a72d9b050
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 281b7b6cf1a4..e4e7a352d032 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -296,6 +296,8 @@ static int renoir_print_clk_levels(struct smu_context *smu,
 
for (i = 0; i < count; i++) {
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
+   if (!value)
+   continue;
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
if (cur_value == value)
-- 
2.17.1

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[PATCH] drm/amdgpu/powerplay:avoid to show invalid DPM table info

2020-04-16 Thread Yuxian Dai 
for different ASIC support different the number of DPM levels,
we should avoid to show the invalid level value.
v1 -> v2:
follow the suggestion,clarifiy the description for this
change
Signed-off-by: Yuxian Dai 
Change-Id: I579ef417ddc8acb4a6cf15c60094743a72d9b050
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 281b7b6cf1a4..e4e7a352d032 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -296,6 +296,8 @@ static int renoir_print_clk_levels(struct smu_context *smu,
 
for (i = 0; i < count; i++) {
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
+   if (!value)
+   continue;
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
if (cur_value == value)
-- 
2.17.1

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[PATCH] drm/amdgpu/powerplay:avoid to show invalid DPM table info

2020-04-15 Thread Yuxian Dai 
we should avoid to show the invalid level value when the
DPM_LEVELS supported number changed

Signed-off-by: Yuxian Dai 
Change-Id: Ib66d0cf34a866fa6f0cedd1d5fc642f59236787d
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 281b7b6cf1a4..e4e7a352d032 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -296,6 +296,8 @@ static int renoir_print_clk_levels(struct smu_context *smu,
 
for (i = 0; i < count; i++) {
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
+   if (!value)
+   continue;
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
if (cur_value == value)
-- 
2.17.1

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[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK

2020-04-01 Thread Yuxian Dai 
1.Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
 FCLK
 UCLK
 MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2.we should show the current working clock freqency from clock table metric

Signed-off-by: Yuxian Dai 
Reviewed-by: Alex Deucher 
Reviewed-by: Huang Rui 
Reviewed-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 ++
 drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..c6b39a7026a8 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+   bool cur_value_match_level = false;
 
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,8 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+   if (cur_value == value)
+   cur_value_match_level = true;
}
 
+   if (!cur_value_match_level)
+   size += sprintf(buf + size, "   %uMhz *\n", cur_value);
+
return size;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq;\
break;  \
case SMU_MCLK:  \
-   freq = table->MemClocks[dpm_level].Freq;\
+   freq = table->FClocks[dpm_level].Freq;  \
break;  \
case SMU_DCEFCLK:   \
freq = table->DcfClocks[dpm_level].Freq;\
-- 
2.17.1

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[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK

2020-04-01 Thread Yuxian Dai 
From: "yuxia...@amd.com" 

1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
 FCLK
 UCLK
 MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric

Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai 
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 ++
 drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..5adc25c8f6f4 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+   bool cur_value_match_level = false;
 
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,7 +298,12 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+   if (cur_value == value) 
+   cur_value_match_level = true;
}
+   
+   if (!cur_value_match_level)
+   size += sprintf(buf + size, "   %uMhz *\n",cur_value);
 
return size;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq;\
break;  \
case SMU_MCLK:  \
-   freq = table->MemClocks[dpm_level].Freq;\
+   freq = table->FClocks[dpm_level].Freq;  \
break;  \
case SMU_DCEFCLK:   \
freq = table->DcfClocks[dpm_level].Freq;\
-- 
2.17.1

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[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK

2020-04-01 Thread Yuxian Dai 
From: "yuxia...@amd.com" 

1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
 FCLK
 UCLK
 MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric

Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai 
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 7 +++
 drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..3901b20196d7 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+   bool cur_value_match_level = false;
 
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,7 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+   if (cur_value == value) 
+   cur_value_match_level = true;
}
+   
+   if (!cur_value_match_level)
+   size += sprintf(buf + size, "   %uMhz *\n",cur_value);
+
 
return size;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq;\
break;  \
case SMU_MCLK:  \
-   freq = table->MemClocks[dpm_level].Freq;\
+   freq = table->FClocks[dpm_level].Freq;  \
break;  \
case SMU_DCEFCLK:   \
freq = table->DcfClocks[dpm_level].Freq;\
-- 
2.17.1

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[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK

2020-03-31 Thread Yuxian Dai 
From: "yuxia...@amd.com" 

1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
 FCLK
 UCLK
 MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric

Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai 
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 7 +++
 drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..30240fdff840 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+   bool cur_value_match_level = false;
 
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,7 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+   if(cur_value == value) 
+   cur_value_match_level = true;
}
+   
+   if(!cur_value_match_level)
+   size += sprintf(buf + size, "   %uMhz *\n",cur_value);
+
 
return size;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq;\
break;  \
case SMU_MCLK:  \
-   freq = table->MemClocks[dpm_level].Freq;\
+   freq = table->FClocks[dpm_level].Freq;  \
break;  \
case SMU_DCEFCLK:   \
freq = table->DcfClocks[dpm_level].Freq;\
-- 
2.17.1

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[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK

2020-03-31 Thread Yuxian Dai 
From: "yuxia...@amd.com" 

1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
 FCLK
 UCLK
 MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric

Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai 
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 8 
 drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..5c5d3f974532 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,6 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+   bool cur_value_match_level = false;
 
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
@@ -297,6 +298,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+   if(cur_value == value) {
+   cur_value_match_level = true;
+   }
+   }
+   
+   if(!cur_value_match_level) {
+   size += sprintf(buf + size, "   %uMhz *\n",cur_value);
}
 
return size;
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq;\
break;  \
case SMU_MCLK:  \
-   freq = table->MemClocks[dpm_level].Freq;\
+   freq = table->FClocks[dpm_level].Freq;  \
break;  \
case SMU_DCEFCLK:   \
freq = table->DcfClocks[dpm_level].Freq;\
-- 
2.17.1

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[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK

2020-03-31 Thread Yuxian Dai 
From: "yuxia...@amd.com" 

1,Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
 FCLK
 UCLK
 MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2,we should show the current working clock freqency from clock table metric

Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai 
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 9 -
 drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7bf52ecba01d..32e7a3c05cd4 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -239,7 +239,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
-
+   bool cur_value_match_level = false;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
 
@@ -297,6 +297,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
+   if(cur_value == value) {
+   cur_value_match_level = true;
+   }
+   }
+   
+   if(!cur_value_match_level) {
+   size += sprintf(buf + size, "   %uMhz *\n",cur_value);
}
 
return size;
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq;\
break;  \
case SMU_MCLK:  \
-   freq = table->MemClocks[dpm_level].Freq;\
+   freq = table->FClocks[dpm_level].Freq;  \
break;  \
case SMU_DCEFCLK:   \
freq = table->DcfClocks[dpm_level].Freq;\
-- 
2.17.1

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[PATCH] drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK for DPM states consist of three entities :FCLK, UCLK, MEMCLK all these three clk change together , MEMCLK from FCLK.

2020-03-31 Thread Yuxian Dai 
From: "yuxia...@amd.com" 

Change-Id: Ia45f3069fc7ae56db495cb5a3865e2c50c550774
Signed-off-by: Yuxian Dai 
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
index 2a390ddd37dd..89cd6da118a3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
freq = table->SocClocks[dpm_level].Freq;\
break;  \
case SMU_MCLK:  \
-   freq = table->MemClocks[dpm_level].Freq;\
+   freq = table->FClocks[dpm_level].Freq;  \
break;  \
case SMU_DCEFCLK:   \
freq = table->DcfClocks[dpm_level].Freq;\
-- 
2.17.1

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