[PATCH] drm/amd/display: Modify comments to match the code
[Why]
This line of code was modified. However, the comment
was remaining unchanged.
[How]
Change "200ms" to "3000ms", which matches the code.
Also add another line of comment, which tells people where
the value came from.
Signed-off-by: Zhan Liu
---
drivers/gpu/drm/amd/display/dc/dc_helper.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c
b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 8da4576e2908..4973d50c4fb9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -485,7 +485,11 @@ void generic_reg_wait(const struct dc_context *ctx,
return;
}
- /* something is terribly wrong if time out is > 200ms. (5Hz) */
+ /*
+* Something is terribly wrong if time out is > 3000ms.
+* 3000ms is defined by SMU timeout value.
+*
+*/
ASSERT(delay_between_poll_us * time_out_num_tries <= 300);
for (i = 0; i <= time_out_num_tries; i++) {
--
2.17.1
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[PATCH] drm/amd/display: Change mmhub_9_4_0_ headers to mmhub_1_0_ ones.
[Why] Kernal won't compile without this patch. That is because mmhub_9_4_0_ headers are obsolete. All contents within mmhub_9_4_0_ headers are inherited by their corresponding mmhub_1_0_ ones. [How] Change mmhub_9_4_0_ headers to their corresponding mmhub_1_0_ ones. Signed-off-by: Zhan Liu --- drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 305bb0841563..53ab88ef71f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -63,8 +63,8 @@ #include "soc15_hw_ip.h" #include "vega10_ip_offset.h" #include "nbio/nbio_6_1_offset.h" -#include "mmhub/mmhub_9_4_0_offset.h" -#include "mmhub/mmhub_9_4_0_sh_mask.h" +#include "mmhub/mmhub_1_0_offset.h" +#include "mmhub/mmhub_1_0_sh_mask.h" #include "reg_helper.h" #include "dce100/dce100_resource.h" -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amd/display: Modify comments to match the code
[Why]
This line of code was modified. However, comments
remained unchanged. As a result, comments and code are
mismatching.
[How]
Modifying comments to reflect code. At the same time,
explaining why the value was changed from 200ms to
3000ms.
Signed-off-by: Zhan Liu
---
drivers/gpu/drm/amd/display/dc/dc_helper.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c
b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 8da4576e2908..e41befa067ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -485,7 +485,12 @@ void generic_reg_wait(const struct dc_context *ctx,
return;
}
- /* something is terribly wrong if time out is > 200ms. (5Hz) */
+ /*
+* Something is terribly wrong if time out is > 3000ms.
+* 3000ms is the maximum time needed for SMU to pass values back.
+* This value comes from experiments.
+*
+*/
ASSERT(delay_between_poll_us * time_out_num_tries <= 300);
for (i = 0; i <= time_out_num_tries; i++) {
--
2.21.0
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drm/amd/display: Modify comments to match the code
[Why]
This line of code was modified. However, comments
remained unchanged. As a result, comments and code are
mismatching.
[How]
Modifying comments to reflect code. At the same time,
explaining why the value was changed from 200ms to
3000ms.
Signed-off-by: Zhan Liu
---
drivers/gpu/drm/amd/display/dc/dc_helper.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c
b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 8da4576e2908..e41befa067ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -485,7 +485,12 @@ void generic_reg_wait(const struct dc_context *ctx,
return;
}
- /* something is terribly wrong if time out is > 200ms. (5Hz) */
+ /*
+* Something is terribly wrong if time out is > 3000ms.
+* 3000ms is the maximum time needed for SMU to pass values back.
+* This value comes from experiments.
+*
+*/
ASSERT(delay_between_poll_us * time_out_num_tries <= 300);
for (i = 0; i <= time_out_num_tries; i++) {
--
2.21.0
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[PATCH] drm/amd/display: Get NV14 specific ip params as needed
[Why]
NV14 is using its own ip params that's different from other
DCN2.0 ASICs.
[How]
Add ASIC revision check to make sure NV14 gets correct
ip params.
Signed-off-by: Zhan Liu
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index dbc0a4a7c284..3dd2b2429ae2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3245,6 +3245,9 @@ static struct _vcs_dpi_soc_bounding_box_st
*get_asic_rev_soc_bb(
static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
uint32_t hw_internal_rev)
{
+ if (ASICREV_IS_NAVI14_M(hw_internal_rev))
+ return &dcn2_0_nv14_ip;
+
/* NV12 and NV10 */
return &dcn2_0_ip;
}
--
2.17.1
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[PATCH] drm/amd/display: Loading NV10/14 Bounding Box Data Directly From Code
[Why]
NV10/14 has released. Its time to get NV10/14 bounding box
directly from code.
[How]
Retrieve NV10/14 bounding box data directly from code.
Signed-off-by: Zhan Liu
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 199 +++---
1 file changed, 121 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2ccfd84a7da4..4115b595e36e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -83,8 +83,6 @@
#include "amdgpu_socbb.h"
-/* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */
-#define SOC_BOUNDING_BOX_VALID false
#define DC_LOGGER_INIT(logger)
struct _vcs_dpi_ip_params_st dcn2_0_ip = {
@@ -3271,12 +3196,12 @@ static bool init_soc_bounding_box(struct dc *dc,
DC_LOGGER_INIT(dc->ctx->logger);
- if (!bb && !SOC_BOUNDING_BOX_VALID) {
+ if (!bb) {
DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
return false;
}
- if (bb && !SOC_BOUNDING_BOX_VALID) {
+ if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
int i;
dcn2_0_nv12_soc.sr_exit_time_us =
@@ -3380,6 +3305,108 @@ static bool init_soc_bounding_box(struct dc *dc,
}
}
+ if (bb && (ASICREV_IS_NAVI14_M(dc->ctx->asic_id.hw_internal_rev) ||
ASICREV_IS_NAVI10_P(dc->ctx->asic_id.hw_internal_rev))) {
+ dcn2_0_soc.sr_exit_time_us = 8.6;
+ dcn2_0_soc.sr_enter_plus_exit_time_us = 10.9;
+ dcn2_0_soc.urgent_latency_us = 4.0;
+ dcn2_0_soc.urgent_latency_pixel_data_only_us = 4.0;
+ dcn2_0_soc.urgent_latency_pixel_mixed_with_vm_data_us = 4.0;
+ dcn2_0_soc.urgent_latency_vm_data_only_us = 4.0;
+
dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096;
+
dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096;
+ dcn2_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes
= 4096;
+ dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0;
+ dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
40.0;
+ dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0;
+ dcn2_0_soc.max_avg_sdp_bw_use_normal_percent = 40.0;
+ dcn2_0_soc.max_avg_dram_bw_use_normal_percent = 40.0;
+ dcn2_0_soc.writeback_latency_us = 12.0;
+ dcn2_0_soc.ideal_dram_bw_after_urgent_percent = 40.0;
+ dcn2_0_soc.max_request_size_bytes = 256;
+ dcn2_0_soc.dram_channel_width_bytes = 2;
+ dcn2_0_soc.fabric_datapath_to_dcn_data_return_bytes = 64;
+ dcn2_0_soc.dcn_downspread_percent = 0.5;
+ dcn2_0_soc.downspread_percent = 0.38;
+ dcn2_0_soc.dram_page_open_time_ns = 50.0;
+ dcn2_0_soc.dram_rw_turnaround_time_ns = 17.5;
+ dcn2_0_soc.dram_return_buffer_per_channel_bytes = 8192;
+ dcn2_0_soc.round_trip_ping_latency_dcfclk_cycles = 131;
+ dcn2_0_soc.urgent_out_of_order_return_per_channel_bytes = 256;
+ dcn2_0_soc.channel_interleave_bytes = 256;
+ dcn2_0_soc.num_banks = 8;
+ dcn2_0_soc.num_chans = 16;
+ dcn2_0_soc.vmm_page_size_bytes = 4096;
+ dcn2_0_soc.dram_clock_change_latency_us = 404.0;
+ dcn2_0_soc.dummy_pstate_latency_us = 5.0;
+ dcn2_0_soc.writeback_dram_clock_change_latency_us = 23.0;
+ dcn2_0_soc.return_bus_width_bytes = 64;
+ dcn2_0_soc.dispclk_dppclk_vco_speed_mhz = 3850;
+ dcn2_0_soc.xfc_bus_transport_time_us = 20;
+ dcn2_0_soc.xfc_xbuf_latency_tolerance_us = 4;
+ dcn2_0_soc.use_urgent_burst_bw = 0;
+ dcn2_0_soc.num_states = 5;
+
+ dcn2_0_soc.clock_limits[0].state = 0;
+ dcn2_0_soc.clock_limits[0].dcfclk_mhz = 560.0;
+ dcn2_0_soc.clock_limits[0].fabricclk_mhz = 560.0;
+ dcn2_0_soc.clock_limits[0].dispclk_mhz = 513.0;
+ dcn2_0_soc.clock_limits[0].dppclk_mhz = 513.0;
+ dcn2_0_soc.clock_limits[0].phyclk_mhz = 540.0;
+ dcn2_0_soc.clock_limits[0].socclk_mhz = 560.0;
+ dcn2_0_soc.clock_limits[0].dscclk_mhz = 171.0;
+ dcn2_0_soc.clock_limits[0].dram_speed_mts = 8960.0;
+
+ dcn2_0_soc.clock_limits[1].state = 1;
+ dcn2_0_soc.clock_limits[1].dcfclk_mhz = 694.0;
+ dcn2_0_soc.clock_limits[1].fabricclk_mhz = 694.0;
+ dcn2_0_soc.clock_limits[1].dispcl
[PATCH v2] drm/amd/display: Loading NV10/14 Bounding Box Data Directly from Code
[Why]
NV10/14 has released. Its time to get NV10/14 bounding box
directly from code.
[How]
Retrieve NV10/14 bounding box data directly from code.
Retrieve NV12 bounding box data from firmware.
Signed-off-by: Zhan Liu
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2ccfd84a7da4..2a158ff5f0a5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -83,8 +83,6 @@
#include "amdgpu_socbb.h"
-/* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */
-#define SOC_BOUNDING_BOX_VALID false
#define DC_LOGGER_INIT(logger)
struct _vcs_dpi_ip_params_st dcn2_0_ip = {
@@ -3271,12 +3269,13 @@ static bool init_soc_bounding_box(struct dc *dc,
DC_LOGGER_INIT(dc->ctx->logger);
- if (!bb && !SOC_BOUNDING_BOX_VALID) {
+ /* TODO: upstream NV12 bounding box when its launched */
+ if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
return false;
}
- if (bb && !SOC_BOUNDING_BOX_VALID) {
+ if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
int i;
dcn2_0_nv12_soc.sr_exit_time_us =
--
2.17.1
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[PATCH v2] drm/amd/powerplay: Copy watermark to SMU
[Why]
Watermark value was expected to copy to SMU
within navi10_display_config_changed(). But
navi10_display_config_changed() is never called.
As a result, the watermark value is never
copied to SMU.
[How]
At end of navi10_set_watermarks_table,
copy watermark to SMU.
Signed-off-by: Zhan Liu
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 15403b7979d6..ad6775c6839f 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1472,6 +1472,17 @@ static int navi10_set_watermarks_table(struct
smu_context *smu,
clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
}
+ /* Pass data to smu controller */
+ if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+ !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+ ret = smu_write_watermarks_table(smu);
+ if (ret) {
+ pr_err("Failed to update WMTABLE!");
+ return ret;
+ }
+ smu->watermarks_bitmap |= WATERMARKS_LOADED;
+ }
+
return 0;
}
--
2.17.1
Hi all,
Navi10 has been upstreamed, so I will directly mail v2 patch
to amd-gfx. Please kindly review this patch again.
Thanks,
Zhan
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[PATCH v3] drm/amd/powerplay: Copy watermark to SMU
[Why]
Watermark value was expected to copy to SMU
within navi10_display_config_changed(). But
navi10_display_config_changed() is never called.
As a result, the watermark value is never
copied to SMU.
[How]
At end of navi10_set_watermarks_table,
copy watermark to SMU.
Signed-off-by: Zhan Liu
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 15403b7979d6..f4cdd78492fa 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1472,6 +1472,17 @@ static int navi10_set_watermarks_table(struct
smu_context *smu,
clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
}
+ /* Pass data to smu controller */
+ if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+ !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+ int ret = smu_write_watermarks_table(smu);
+ if (ret) {
+ pr_err("Failed to update WMTABLE!");
+ return ret;
+ }
+ smu->watermarks_bitmap |= WATERMARKS_LOADED;
+ }
+
return 0;
}
--
2.17.1
Fix a typo here.
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[PATCH] drm/amd/powerplay: Add SMU WMTABLE Validity Check for Renoir
[Why]
SMU watermark table (WMTABLE) validity check is
missing on Renoir. This validity check is very
useful for checking whether WMTABLE is updated successfully.
[How]
Add SMU watermark validity check.
Signed-off-by: Zhan Liu
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 89a54f8e08d3..81520b0fca68 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -777,9 +777,17 @@ static int renoir_set_watermarks_table(
}
/* pass data to smu controller */
- ret = smu_write_watermarks_table(smu);
+ if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+ !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+ ret = smu_write_watermarks_table(smu);
+ if (ret) {
+ pr_err("Failed to update WMTABLE!");
+ return ret;
+ }
+ smu->watermarks_bitmap |= WATERMARKS_LOADED;
+ }
- return ret;
+ return 0;
}
static int renoir_get_power_profile_mode(struct smu_context *smu,
--
2.17.1
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[PATCH] drm/amd/display: Avoid HPD IRQ in GPU reset state
[Why]
If GPU is in reset state, force enabling link will cause
unexpected behaviour.
[How]
Avoid handling HPD IRQ when GPU is in reset state.
Signed-off-by: Zhan Liu
Change-Id: I29d80501e44096068e98b5d5984e63822dfcef82
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index cc048c348a92..58b59152a8be 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2769,15 +2769,15 @@ static void handle_hpd_rx_irq(void *param)
}
}
- if (!amdgpu_in_reset(adev))
+ if (!amdgpu_in_reset(adev)) {
mutex_lock(&adev->dm.dc_lock);
#ifdef CONFIG_DRM_AMD_DC_HDCP
result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL);
#else
result = dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL);
#endif
- if (!amdgpu_in_reset(adev))
mutex_unlock(&adev->dm.dc_lock);
+ }
out:
if (result && !is_mst_root_connector) {
--
2.25.1
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[PATCH] drm/amdgpu: Do not change amdgpu framebuffer format during page flip
[Why] Driver cannot change amdgpu framebuffer (afb) format while doing page flip. Force system doing so will cause ioctl error, and result in breaking several functionalities including FreeSync. If afb format is forced to change during page flip, following message will appear in dmesg.log: "[drm:drm_mode_page_flip_ioctl [drm]] Page flip is not allowed to change frame buffer format." [How] Do not change afb format while doing page flip. It is okay to check whether afb format is valid here, however, forcing afb format change shouldn't happen here. Signed-off-by: Zhan Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index a638709e9c92..0efebd592b65 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -831,8 +831,6 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) modifier); if (!format_info) return -EINVAL; - - afb->base.format = format_info; } } -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amdgpu: Do not change amdgpu framebuffer format during page flip
[Why] Driver cannot change amdgpu framebuffer (afb) format while doing page flip. Force system doing so will cause ioctl error, and result in breaking several functionalities including FreeSync. If afb format is forced to change during page flip, following message will appear in dmesg.log: "[drm:drm_mode_page_flip_ioctl [drm]] Page flip is not allowed to change frame buffer format." [How] Do not change afb format while doing page flip. It is okay to check whether afb format is valid here, however, forcing afb format change shouldn't happen here. Signed-off-by: Zhan Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Thanks Nick and Bas. Here is my second patch for review. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index a638709e9c92..8a12e27ff4ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -832,7 +832,8 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) if (!format_info) return -EINVAL; - afb->base.format = format_info; + if (!afb->base.format) + afb->base.format = format_info; } } -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/display: Remove aconnector condition check for dpcd read
[Why]
Aconnector is not necessary to be NULL in order to read dpcd
successfully.
Actually if we rely on checking aconnector here, we won't be able
to turn off all displays before doing display detection. That will
cause some MST hubs not able to light up.
[How]
Remove aconnector check when turning off all displays at
hardware initialization stage.
Signed-off-by: Zhan Liu
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 36 ---
1 file changed, 14 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 9f41efddc9bc..6f33f3f0d023 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1332,31 +1332,23 @@ void dcn10_init_hw(struct dc *dc)
if (dc->links[i]->connector_signal !=
SIGNAL_TYPE_DISPLAY_PORT)
continue;
- /*
-* core_link_read_dpcd() will invoke
dm_helpers_dp_read_dpcd(),
-* which needs to read dpcd info with the help of
aconnector.
-* If aconnector (dc->links[i]->prev) is NULL, then
dpcd status
-* cannot be read.
-*/
- if (dc->links[i]->priv) {
- /* if any of the displays are lit up turn them
off */
- status = core_link_read_dpcd(dc->links[i],
DP_SET_POWER,
-
&dpcd_power_state, sizeof(dpcd_power_state));
- if (status == DC_OK && dpcd_power_state ==
DP_POWER_STATE_D0) {
- /* blank dp stream before power off
receiver*/
- if
(dc->links[i]->link_enc->funcs->get_dig_frontend) {
- unsigned int fe =
dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
-
- for (j = 0; j <
dc->res_pool->stream_enc_count; j++) {
- if (fe ==
dc->res_pool->stream_enc[j]->id) {
-
dc->res_pool->stream_enc[j]->funcs->dp_blank(
-
dc->res_pool->stream_enc[j]);
- break;
- }
+ /* if any of the displays are lit up turn them off */
+ status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
+ &dpcd_power_state,
sizeof(dpcd_power_state));
+ if (status == DC_OK && dpcd_power_state ==
DP_POWER_STATE_D0) {
+ /* blank dp stream before power off receiver*/
+ if
(dc->links[i]->link_enc->funcs->get_dig_frontend) {
+ unsigned int fe =
dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
+
+ for (j = 0; j <
dc->res_pool->stream_enc_count; j++) {
+ if (fe ==
dc->res_pool->stream_enc[j]->id) {
+
dc->res_pool->stream_enc[j]->funcs->dp_blank(
+
dc->res_pool->stream_enc[j]);
+ break;
}
}
- dp_receiver_power_ctrl(dc->links[i],
false);
}
+ dp_receiver_power_ctrl(dc->links[i], false);
}
}
}
--
2.17.1
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[PATCH] drm/amd/display: Don't disable DP PHY when link loss happens
[Why] There is a use case that link loss happens accidentally, and we need to recover that link loss as soon as possible. Under this circumstance, DP PHY will perform link training, then try to recover the link that's just lost. However, if link PHY is disabled by code here, then DP display will never come back again. [How] Don't disable DP transmitter and its encoder, even if link loss is detected. Signed-off-by: Zhan Liu --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 38b0f4347383..49f48d432923 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2876,7 +2876,6 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd return false; previous_link_settings = link->cur_link_settings; - dp_disable_link_phy(link, pipe_ctx->stream->signal); perform_link_training_with_retries(&previous_link_settings, true, LINK_TRAINING_ATTEMPTS, -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/display: Move drm_dp_mst_atomic_check() to the front of dc_validate_global_state()
[Why]
Need to do atomic check first, then validate global state.
If not, when connecting both MST and HDMI displays and
set a bad mode via xrandr, system will hang.
[How]
Move drm_dp_mst_atomic_check() to the front of
dc_validate_global_state().
Signed-off-by: Zhan Liu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index eed3ed7180fd..805d8d84ebb8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8256,6 +8256,16 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
goto fail;
#endif
+ /*
+* Perform validation of MST topology in the state:
+* We need to perform MST atomic check before calling
+* dc_validate_global_state(), or there is a chance
+* to get stuck in an infinite loop and hang eventually.
+*/
+ ret = drm_dp_mst_atomic_check(state);
+ if (ret)
+ goto fail;
+
if (dc_validate_global_state(dc, dm_state->context, false) !=
DC_OK) {
ret = -EINVAL;
goto fail;
@@ -8284,10 +8294,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
dc_retain_state(old_dm_state->context);
}
}
- /* Perform validation of MST topology in the state*/
- ret = drm_dp_mst_atomic_check(state);
- if (ret)
- goto fail;
/* Store the overall update type for use later in atomic check. */
for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
--
2.17.1
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[PATCH] drm/amd/display: Add aconnector condition check for dpcd read
[Why]
core_link_read_dpcd() will invoke dm_helpers_dp_read_dpcd(),
which needs to read dpcd info with the help of aconnector.
If aconnector (dc->links[i]->prev) is NULL, then dpcd status
cannot be read.
As a result, dpcd read fails and a line of error will be
printed out in dmesg.log as:
"*ERROR* Failed to found connector for link!"
[How]
Make sure that aconnector (dc->links[i]->prev) is not NULL,
then read dpcd status.
Signed-off-by: Zhan Liu
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 42fcfee2c31b..92e1574073fd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1331,11 +1331,20 @@ void dcn10_init_hw(struct dc *dc)
if (dc->links[i]->connector_signal !=
SIGNAL_TYPE_DISPLAY_PORT) {
continue;
}
- /* if any of the displays are lit up turn them off */
- status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
-&dpcd_power_state,
sizeof(dpcd_power_state));
- if (status == DC_OK && dpcd_power_state ==
DP_POWER_STATE_D0) {
- dp_receiver_power_ctrl(dc->links[i], false);
+
+ /*
+* core_link_read_dpcd() will invoke
dm_helpers_dp_read_dpcd(),
+* which needs to read dpcd info with the help of
aconnector.
+* If aconnector (dc->links[i]->prev) is NULL, then
dpcd status
+* cannot be read.
+*/
+ if (dc->links[i]->priv) {
+ /* if any of the displays are lit up turn them
off */
+ status = core_link_read_dpcd(dc->links[i],
DP_SET_POWER,
+
&dpcd_power_state, sizeof(dpcd_power_state));
+ if (status == DC_OK && dpcd_power_state ==
DP_POWER_STATE_D0) {
+ dp_receiver_power_ctrl(dc->links[i],
false);
+ }
}
}
}
--
2.17.1
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