RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
This one looks better
You can put my RB
Thanks
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Wan, Gavin
Sent: Saturday, May 23, 2020 3:41 AM
To: Alex Deucher
Cc: amd-gfx list
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
HI Alex,
I fixed it as your suggestion.
Thanks,
Gavin
-Original Message-
From: Alex Deucher
Sent: Friday, May 22, 2020 3:11 PM
To: Wan, Gavin
Cc: amd-gfx list
Subject: Re: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
On Fri, May 22, 2020 at 2:20 PM Gavin Wan wrote:
>
> For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side.
> The Guest should not program CP_INT_CNTL_RING0 again.
>
> Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
> Signed-off-by: Gavin Wan
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index bd5dd4f64311..39275bf79448 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct
> amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct
> amdgpu_device *adev,
>bool enable) {
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
This needs to be below the stack variable declarations or you'll get a warning.
Alex
> u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
>
> tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
> CNTX_BUSY_INT_ENABLE,
> --
> 2.25.1
>
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Re: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
On Fri, May 22, 2020 at 3:39 PM Gavin Wan wrote:
>
> For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side.
> The Guest should not program CP_INT_CNTL_RING0 again.
>
> Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
> Signed-off-by: Gavin Wan
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index bd5dd4f64311..4d6928cfc269 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4558,7 +4558,12 @@ static void gfx_v10_0_constants_init(struct
> amdgpu_device *adev)
> static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
>bool enable)
> {
> - u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
> + u32 tmp;
> +
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> + tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
>
> tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
> enable ? 1 : 0);
> --
> 2.25.1
>
> ___
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> amd-gfx@lists.freedesktop.org
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RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
HI Alex,
I fixed it as your suggestion.
Thanks,
Gavin
-Original Message-
From: Alex Deucher
Sent: Friday, May 22, 2020 3:11 PM
To: Wan, Gavin
Cc: amd-gfx list
Subject: Re: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
On Fri, May 22, 2020 at 2:20 PM Gavin Wan wrote:
>
> For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side.
> The Guest should not program CP_INT_CNTL_RING0 again.
>
> Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
> Signed-off-by: Gavin Wan
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index bd5dd4f64311..39275bf79448 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct
> amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct
> amdgpu_device *adev,
>bool enable) {
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
This needs to be below the stack variable declarations or you'll get a warning.
Alex
> u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
>
> tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
> CNTX_BUSY_INT_ENABLE,
> --
> 2.25.1
>
> ___
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> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CGa
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[PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side.
The Guest should not program CP_INT_CNTL_RING0 again.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..4d6928cfc269 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,7 +4558,12 @@ static void gfx_v10_0_constants_init(struct
amdgpu_device *adev)
static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
bool enable)
{
- u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
+ u32 tmp;
+
+ if (amdgpu_sriov_vf(adev))
+ return;
+
+ tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
enable ? 1 : 0);
--
2.25.1
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Re: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
On Fri, May 22, 2020 at 2:20 PM Gavin Wan wrote:
>
> For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side.
> The Guest should not program CP_INT_CNTL_RING0 again.
>
> Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
> Signed-off-by: Gavin Wan
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index bd5dd4f64311..39275bf79448 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct
> amdgpu_device *adev)
> static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
>bool enable)
> {
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
This needs to be below the stack variable declarations or you'll get a warning.
Alex
> u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
>
> tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
> --
> 2.25.1
>
> ___
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RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
Fixed it as Monk and Hawking suggestion. Now it only has one checking in
function gfx_v10_0_enable_gui_idle_interrupt.
BTW, I update the commit, but it send out an another email.
Thanks,
Gavin
-Original Message-
From: Zhang, Hawking
Sent: Friday, May 22, 2020 2:17 AM
To: Liu, Monk ; Chen, Guchun ; Wan,
Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Or make it in more reasonable place.
Regards,
Hawking
-Original Message-
From: Zhang, Hawking
Sent: Friday, May 22, 2020 14:16
To: Liu, Monk ; Chen, Guchun ; Wan,
Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Yes, please try best effort to not introduce guest/one_vf/mult_vf check.
Regards,
Hawking
-Original Message-
From: Liu, Monk
Sent: Friday, May 22, 2020 14:12
To: Liu, Monk ; Zhang, Hawking ; Chen,
Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
Gavin
Looks the only place you need to change is the part of avoid touching
"CP_INT_CNTL_RING0" which is handled by GIM now
Others looks not needed at all
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Liu, Monk
Sent: Friday, May 22, 2020 1:52 PM
To: Zhang, Hawking ; Chen, Guchun ;
Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
Sounds a good idea
@Wan, Gavin can you try hawking's advice ?
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Friday, May 22, 2020 1:09 PM
To: Chen, Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Can we leverage existing CG flags to control this rather than add
amdgpu_sriov_vf(adev) check everywhere?
If GC CG feature is programmed by host. We can just mask out the following
flags for guest driver case (amdgpu_sriov_vf(adev)).
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS
There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually
add unnecessary sustaining effort.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Chen, Guchun
Sent: Friday, May 22, 2020 11:47
To: Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
[Guchun]This coding style is not correct. You should put the check after the
declare of 'u32 tmp'.
Maybe it's better to split below line to declare and execution parts
respectively.
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+
[PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side.
The Guest should not program CP_INT_CNTL_RING0 again.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..39275bf79448 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev)
static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
--
2.25.1
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RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
[AMD Public Use]
Or make it in more reasonable place.
Regards,
Hawking
-Original Message-
From: Zhang, Hawking
Sent: Friday, May 22, 2020 14:16
To: Liu, Monk ; Chen, Guchun ; Wan,
Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Yes, please try best effort to not introduce guest/one_vf/mult_vf check.
Regards,
Hawking
-Original Message-
From: Liu, Monk
Sent: Friday, May 22, 2020 14:12
To: Liu, Monk ; Zhang, Hawking ; Chen,
Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
Gavin
Looks the only place you need to change is the part of avoid touching
"CP_INT_CNTL_RING0" which is handled by GIM now
Others looks not needed at all
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Liu, Monk
Sent: Friday, May 22, 2020 1:52 PM
To: Zhang, Hawking ; Chen, Guchun ;
Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
Sounds a good idea
@Wan, Gavin can you try hawking's advice ?
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Friday, May 22, 2020 1:09 PM
To: Chen, Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Can we leverage existing CG flags to control this rather than add
amdgpu_sriov_vf(adev) check everywhere?
If GC CG feature is programmed by host. We can just mask out the following
flags for guest driver case (amdgpu_sriov_vf(adev)).
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS
There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually
add unnecessary sustaining effort.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Chen, Guchun
Sent: Friday, May 22, 2020 11:47
To: Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
[Guchun]This coding style is not correct. You should put the check after the
declare of 'u32 tmp'.
Maybe it's better to split below line to declare and execution parts
respectively.
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags &
RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
[AMD Public Use]
Yes, please try best effort to not introduce guest/one_vf/mult_vf check.
Regards,
Hawking
-Original Message-
From: Liu, Monk
Sent: Friday, May 22, 2020 14:12
To: Liu, Monk ; Zhang, Hawking ; Chen,
Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
Gavin
Looks the only place you need to change is the part of avoid touching
"CP_INT_CNTL_RING0" which is handled by GIM now
Others looks not needed at all
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Liu, Monk
Sent: Friday, May 22, 2020 1:52 PM
To: Zhang, Hawking ; Chen, Guchun ;
Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
Sounds a good idea
@Wan, Gavin can you try hawking's advice ?
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Friday, May 22, 2020 1:09 PM
To: Chen, Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Can we leverage existing CG flags to control this rather than add
amdgpu_sriov_vf(adev) check everywhere?
If GC CG feature is programmed by host. We can just mask out the following
flags for guest driver case (amdgpu_sriov_vf(adev)).
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS
There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually
add unnecessary sustaining effort.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Chen, Guchun
Sent: Friday, May 22, 2020 11:47
To: Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
[Guchun]This coding style is not correct. You should put the check after the
declare of 'u32 tmp'.
Maybe it's better to split below line to declare and execution parts
respectively.
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static
int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
Gavin
Looks the only place you need to change is the part of avoid touching
"CP_INT_CNTL_RING0" which is handled by GIM now
Others looks not needed at all
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Liu, Monk
Sent: Friday, May 22, 2020 1:52 PM
To: Zhang, Hawking ; Chen, Guchun ;
Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
Sounds a good idea
@Wan, Gavin can you try hawking's advice ?
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Friday, May 22, 2020 1:09 PM
To: Chen, Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Can we leverage existing CG flags to control this rather than add
amdgpu_sriov_vf(adev) check everywhere?
If GC CG feature is programmed by host. We can just mask out the following
flags for guest driver case (amdgpu_sriov_vf(adev)).
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS
There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually
add unnecessary sustaining effort.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Chen, Guchun
Sent: Friday, May 22, 2020 11:47
To: Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
[Guchun]This coding style is not correct. You should put the check after the
declare of 'u32 tmp'.
Maybe it's better to split below line to declare and execution parts
respectively.
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static
int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
--
2.25.1
___
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amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
Sounds a good idea
@Wan, Gavin can you try hawking's advice ?
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Friday, May 22, 2020 1:09 PM
To: Chen, Guchun ; Wan, Gavin ;
amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Can we leverage existing CG flags to control this rather than add
amdgpu_sriov_vf(adev) check everywhere?
If GC CG feature is programmed by host. We can just mask out the following
flags for guest driver case (amdgpu_sriov_vf(adev)).
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS
There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually
add unnecessary sustaining effort.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Chen, Guchun
Sent: Friday, May 22, 2020 11:47
To: Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
[Guchun]This coding style is not correct. You should put the check after the
declare of 'u32 tmp'.
Maybe it's better to split below line to declare and execution parts
respectively.
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static
int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
--
2.25.1
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RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
[AMD Public Use]
Can we leverage existing CG flags to control this rather than add
amdgpu_sriov_vf(adev) check everywhere?
If GC CG feature is programmed by host. We can just mask out the following
flags for guest driver case (amdgpu_sriov_vf(adev)).
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS
There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually
add unnecessary sustaining effort.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Chen, Guchun
Sent: Friday, May 22, 2020 11:47
To: Wan, Gavin ; amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for
SRIOV.
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
[Guchun]This coding style is not correct. You should put the check after the
declare of 'u32 tmp'.
Maybe it's better to split below line to declare and execution parts
respectively.
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static
int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
--
2.25.1
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RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
[AMD Public Use]
Please see one comment below.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
[Guchun]This coding style is not correct. You should put the check after the
declare of 'u32 tmp'.
Maybe it's better to split below line to declare and execution parts
respectively.
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static
int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
--
2.25.1
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RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
Reviewed-by: Monk Liu
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Gavin Wan
Sent: Friday, May 22, 2020 3:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wan, Gavin
Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should not program
CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device
*adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@
-6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static
int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
--
2.25.1
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Re: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
On Thu, May 21, 2020 at 3:53 PM Gavin Wan wrote:
>
> For SRIOV, since the CGCG is set on host side. The Guest should
> not program CGCG again.
>
> The patch ignores setting CGCG for SRIOV.
>
> Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
> Signed-off-by: Gavin Wan
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index bd5dd4f64311..52b6e4759cf3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct
> amdgpu_device *adev)
> static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
>bool enable)
> {
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
>
> tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
> @@ -6842,6 +6845,9 @@ static void
> gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
> {
> uint32_t data, def;
>
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> /* It is disabled by HW by default */
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
> /* 0 - Disable some blocks' MGCG */
> @@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
> amdgpu_device *adev,
> {
> uint32_t data, def;
>
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> /* Enable 3D CGCG/CGLS */
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
> /* write cmd to clear cgcg/cgls ov */
> @@ -6953,6 +6962,9 @@ static void
> gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
> {
> uint32_t def, data;
>
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
> def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
> /* unset CGCG override */
> @@ -6994,6 +7006,9 @@ static void
> gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
> static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
> bool enable)
> {
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> amdgpu_gfx_rlc_enter_safe_mode(adev);
>
> if (enable) {
> --
> 2.25.1
>
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[PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
For SRIOV, since the CGCG is set on host side. The Guest should
not program CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev)
static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
@@ -6842,6 +6845,9 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
{
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev,
{
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */
@@ -6953,6 +6962,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
{
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
--
2.25.1
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