RE: [PATCH] drm/amd/display: Update watermark values for DCN301

2022-01-28 Thread Liu, Zhan
[Public]

> -Original Message-
> From: amd-gfx  On Behalf Of Agustin
> Gutierrez
> Sent: 2022/January/28, Friday 6:07 PM
> To: amd-gfx@lists.freedesktop.org; Gutierrez, Agustin
> 
> Cc: Gutierrez, Agustin 
> Subject: [PATCH] drm/amd/display: Update watermark values for DCN301
>
> [Why]
> There is underflow / visual corruption DCN301, for high
> bandwidth MST DSC configurations such as 2x1440p144 or 2x4k60.
>
> [How]
> Use up-to-date watermark values for DCN301.
>
> Signed-off-by: Agustin Gutierrez 

Looks good to me.

Reviewed-by: Zhan Liu 

> ---
>  .../amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c   | 16 
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> index 48005def1164..bc4ddc36fe58 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> @@ -570,32 +570,32 @@ static struct wm_table lpddr5_wm_table = {
>   .wm_inst = WM_A,
>   .wm_type = WM_TYPE_PSTATE_CHG,
>   .pstate_latency_us = 11.65333,
> - .sr_exit_time_us = 7.95,
> - .sr_enter_plus_exit_time_us = 9,
> + .sr_exit_time_us = 13.5,
> + .sr_enter_plus_exit_time_us = 16.5,
>   .valid = true,
>   },
>   {
>   .wm_inst = WM_B,
>   .wm_type = WM_TYPE_PSTATE_CHG,
>   .pstate_latency_us = 11.65333,
> - .sr_exit_time_us = 9.82,
> - .sr_enter_plus_exit_time_us = 11.196,
> + .sr_exit_time_us = 13.5,
> + .sr_enter_plus_exit_time_us = 16.5,
>   .valid = true,
>   },
>   {
>   .wm_inst = WM_C,
>   .wm_type = WM_TYPE_PSTATE_CHG,
>   .pstate_latency_us = 11.65333,
> - .sr_exit_time_us = 9.89,
> - .sr_enter_plus_exit_time_us = 11.24,
> + .sr_exit_time_us = 13.5,
> + .sr_enter_plus_exit_time_us = 16.5,
>   .valid = true,
>   },
>   {
>   .wm_inst = WM_D,
>   .wm_type = WM_TYPE_PSTATE_CHG,
>   .pstate_latency_us = 11.65333,
> - .sr_exit_time_us = 9.748,
> - .sr_enter_plus_exit_time_us = 11.102,
> + .sr_exit_time_us = 13.5,
> + .sr_enter_plus_exit_time_us = 16.5,
>   .valid = true,
>   },
>   }
> --
> 2.25.1



[PATCH] drm/amd/display: Update watermark values for DCN301

2022-01-28 Thread Agustin Gutierrez
[Why]
There is underflow / visual corruption DCN301, for high
bandwidth MST DSC configurations such as 2x1440p144 or 2x4k60.

[How]
Use up-to-date watermark values for DCN301.

Signed-off-by: Agustin Gutierrez 
---
 .../amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c   | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
index 48005def1164..bc4ddc36fe58 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
@@ -570,32 +570,32 @@ static struct wm_table lpddr5_wm_table = {
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 7.95,
-   .sr_enter_plus_exit_time_us = 9,
+   .sr_exit_time_us = 13.5,
+   .sr_enter_plus_exit_time_us = 16.5,
.valid = true,
},
{
.wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 9.82,
-   .sr_enter_plus_exit_time_us = 11.196,
+   .sr_exit_time_us = 13.5,
+   .sr_enter_plus_exit_time_us = 16.5,
.valid = true,
},
{
.wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 9.89,
-   .sr_enter_plus_exit_time_us = 11.24,
+   .sr_exit_time_us = 13.5,
+   .sr_enter_plus_exit_time_us = 16.5,
.valid = true,
},
{
.wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 9.748,
-   .sr_enter_plus_exit_time_us = 11.102,
+   .sr_exit_time_us = 13.5,
+   .sr_enter_plus_exit_time_us = 16.5,
.valid = true,
},
}
-- 
2.25.1