Re: [PATCH] drm/amd/pm: support ss metrics read for smu11
On 5/11/2022 1:14 PM, Lazar, Lijo wrote:
On 5/11/2022 12:51 PM, Sathishkumar S wrote:
support reading smartshift apu and dgpu power for smu11 based asic
v2: add new version of SmuMetrics and make calculation more readable
(Lijo)
v3: avoid calculations that result in -ve values and skip related checks
v4: use the current power limit on dGPU and exclude smu 11_0_7 (Lijo)
Signed-off-by: Sathishkumar S
Acked-by: Alex Deucher
---
.../pmfw_if/smu11_driver_if_sienna_cichlid.h | 63 +++
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 161 ++
2 files changed, 187 insertions(+), 37 deletions(-)
diff --git
a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
index 08f0bb2af5d2..280d42778f28 100644
---
a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
+++
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
@@ -1540,11 +1540,74 @@ typedef struct {
} SmuMetrics_V3_t;
+typedef struct {
+ uint32_t CurrClock[PPCLK_COUNT];
+
+ uint16_t AverageGfxclkFrequencyPreDs;
+ uint16_t AverageGfxclkFrequencyPostDs;
+ uint16_t AverageFclkFrequencyPreDs;
+ uint16_t AverageFclkFrequencyPostDs;
+ uint16_t AverageUclkFrequencyPreDs;
+ uint16_t AverageUclkFrequencyPostDs;
+
+
+ uint16_t AverageGfxActivity;
+ uint16_t AverageUclkActivity;
+ uint8_t CurrSocVoltageOffset;
+ uint8_t CurrGfxVoltageOffset;
+ uint8_t CurrMemVidOffset;
+ uint8_t Padding8;
+ uint16_t AverageSocketPower;
+ uint16_t TemperatureEdge;
+ uint16_t TemperatureHotspot;
+ uint16_t TemperatureMem;
+ uint16_t TemperatureVrGfx;
+ uint16_t TemperatureVrMem0;
+ uint16_t TemperatureVrMem1;
+ uint16_t TemperatureVrSoc;
+ uint16_t TemperatureLiquid0;
+ uint16_t TemperatureLiquid1;
+ uint16_t TemperaturePlx;
+ uint16_t Padding16;
+ uint32_t AccCnt;
+ uint8_t ThrottlingPercentage[THROTTLER_COUNT];
+
+
+ uint8_t LinkDpmLevel;
+ uint8_t CurrFanPwm;
+ uint16_t CurrFanSpeed;
+
+ //BACO metrics, PMFW-1721
+ //metrics for D3hot entry/exit and driver ARM msgs
+ uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
+ uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];
+ uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];
+
+ //PMFW-4362
+ uint32_t EnergyAccumulator;
+ uint16_t AverageVclk0Frequency;
+ uint16_t AverageDclk0Frequency;
+ uint16_t AverageVclk1Frequency;
+ uint16_t AverageDclk1Frequency;
+ uint16_t VcnUsagePercentage0;
+ uint16_t VcnUsagePercentage1;
+ uint8_t PcieRate;
+ uint8_t PcieWidth;
+ uint16_t AverageGfxclkFrequencyTarget;
+
+ uint8_t ApuSTAPMSmartShiftLimit;
+ uint8_t AverageApuSocketPower;
+ uint8_t ApuSTAPMLimit;
+ uint8_t Padding8_2;
+
+} SmuMetrics_V4_t;
+
typedef struct {
union {
SmuMetrics_t SmuMetrics;
SmuMetrics_V2_t SmuMetrics_V2;
SmuMetrics_V3_t SmuMetrics_V3;
+ SmuMetrics_V4_t SmuMetrics_V4;
I see some extra indentation here .
I used tab and the current code here is using 4 spaces, will match it to
existing code.
};
uint32_t Spare[1];
diff --git
a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 86ab276b6b0b..503439754f08 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -585,6 +585,102 @@ static uint32_t
sienna_cichlid_get_throttler_status_locked(struct smu_context *s
return throttler_status;
}
+static int sienna_cichlid_get_power_limit(struct smu_context *smu,
+ uint32_t *current_power_limit,
+ uint32_t *default_power_limit,
+ uint32_t *max_power_limit)
+{
+ struct smu_11_0_7_powerplay_table *powerplay_table =
+ (struct smu_11_0_7_powerplay_table
*)smu->smu_table.power_play_table;
+ uint32_t power_limit, od_percent;
+ uint16_t *table_member;
+
+ GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
+
+ if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
+ power_limit =
+ table_member[PPT_THROTTLER_PPT0];
+ }
+
+ if (current_power_limit)
+ *current_power_limit = power_limit;
+ if (default_power_limit)
+ *default_power_limit = power_limit;
+
+ if (max_power_limit) {
+ if (smu->od_enabled) {
+ od_percent =
+ le32_to_cpu(powerplay_table->overdrive_table.max[
+ SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
+
+ dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d
(default: %d)\n",
+ od_percent, power_limit);
+
+ power_limit *= (100 + od_percent);
+ power_limit /= 100;
+ }
+ *max_power_limit = power_limit;
+ }
+
+ return 0;
+}
+
+static void sienna_cichlid_get_smartsh
Re: [PATCH] drm/amd/pm: support ss metrics read for smu11
On 5/11/2022 12:51 PM, Sathishkumar S wrote:
support reading smartshift apu and dgpu power for smu11 based asic
v2: add new version of SmuMetrics and make calculation more readable (Lijo)
v3: avoid calculations that result in -ve values and skip related checks
v4: use the current power limit on dGPU and exclude smu 11_0_7 (Lijo)
Signed-off-by: Sathishkumar S
Acked-by: Alex Deucher
---
.../pmfw_if/smu11_driver_if_sienna_cichlid.h | 63 +++
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 161 ++
2 files changed, 187 insertions(+), 37 deletions(-)
diff --git
a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
index 08f0bb2af5d2..280d42778f28 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
@@ -1540,11 +1540,74 @@ typedef struct {
} SmuMetrics_V3_t;
+typedef struct {
+ uint32_t CurrClock[PPCLK_COUNT];
+
+ uint16_t AverageGfxclkFrequencyPreDs;
+ uint16_t AverageGfxclkFrequencyPostDs;
+ uint16_t AverageFclkFrequencyPreDs;
+ uint16_t AverageFclkFrequencyPostDs;
+ uint16_t AverageUclkFrequencyPreDs;
+ uint16_t AverageUclkFrequencyPostDs;
+
+
+ uint16_t AverageGfxActivity;
+ uint16_t AverageUclkActivity;
+ uint8_t CurrSocVoltageOffset;
+ uint8_t CurrGfxVoltageOffset;
+ uint8_t CurrMemVidOffset;
+ uint8_t Padding8;
+ uint16_t AverageSocketPower;
+ uint16_t TemperatureEdge;
+ uint16_t TemperatureHotspot;
+ uint16_t TemperatureMem;
+ uint16_t TemperatureVrGfx;
+ uint16_t TemperatureVrMem0;
+ uint16_t TemperatureVrMem1;
+ uint16_t TemperatureVrSoc;
+ uint16_t TemperatureLiquid0;
+ uint16_t TemperatureLiquid1;
+ uint16_t TemperaturePlx;
+ uint16_t Padding16;
+ uint32_t AccCnt;
+ uint8_t ThrottlingPercentage[THROTTLER_COUNT];
+
+
+ uint8_t LinkDpmLevel;
+ uint8_t CurrFanPwm;
+ uint16_t CurrFanSpeed;
+
+ //BACO metrics, PMFW-1721
+ //metrics for D3hot entry/exit and driver ARM msgs
+ uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
+ uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];
+ uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];
+
+ //PMFW-4362
+ uint32_t EnergyAccumulator;
+ uint16_t AverageVclk0Frequency;
+ uint16_t AverageDclk0Frequency;
+ uint16_t AverageVclk1Frequency;
+ uint16_t AverageDclk1Frequency;
+ uint16_t VcnUsagePercentage0;
+ uint16_t VcnUsagePercentage1;
+ uint8_t PcieRate;
+ uint8_t PcieWidth;
+ uint16_t AverageGfxclkFrequencyTarget;
+
+ uint8_t ApuSTAPMSmartShiftLimit;
+ uint8_t AverageApuSocketPower;
+ uint8_t ApuSTAPMLimit;
+ uint8_t Padding8_2;
+
+} SmuMetrics_V4_t;
+
typedef struct {
union {
SmuMetrics_t SmuMetrics;
SmuMetrics_V2_t SmuMetrics_V2;
SmuMetrics_V3_t SmuMetrics_V3;
+ SmuMetrics_V4_t SmuMetrics_V4;
I see some extra indentation here .
};
uint32_t Spare[1];
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 86ab276b6b0b..503439754f08 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -585,6 +585,102 @@ static uint32_t
sienna_cichlid_get_throttler_status_locked(struct smu_context *s
return throttler_status;
}
+static int sienna_cichlid_get_power_limit(struct smu_context *smu,
+ uint32_t *current_power_limit,
+ uint32_t *default_power_limit,
+ uint32_t *max_power_limit)
+{
+ struct smu_11_0_7_powerplay_table *powerplay_table =
+ (struct smu_11_0_7_powerplay_table
*)smu->smu_table.power_play_table;
+ uint32_t power_limit, od_percent;
+ uint16_t *table_member;
+
+ GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
+
+ if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
+ power_limit =
+ table_member[PPT_THROTTLER_PPT0];
+ }
+
+ if (current_power_limit)
+ *current_power_limit = power_limit;
+ if (default_power_limit)
+ *default_power_limit = power_limit;
+
+ if (max_power_limit) {
+ if (smu->od_enabled) {
+ od_percent =
+
le32_to_cpu(powerplay_table->overdrive_table.max[
+
SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
+
+ dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d
(default: %d)\n
[PATCH] drm/amd/pm: support ss metrics read for smu11
support reading smartshift apu and dgpu power for smu11 based asic
v2: add new version of SmuMetrics and make calculation more readable (Lijo)
v3: avoid calculations that result in -ve values and skip related checks
v4: use the current power limit on dGPU and exclude smu 11_0_7 (Lijo)
Signed-off-by: Sathishkumar S
Acked-by: Alex Deucher
---
.../pmfw_if/smu11_driver_if_sienna_cichlid.h | 63 +++
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 161 ++
2 files changed, 187 insertions(+), 37 deletions(-)
diff --git
a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
index 08f0bb2af5d2..280d42778f28 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
@@ -1540,11 +1540,74 @@ typedef struct {
} SmuMetrics_V3_t;
+typedef struct {
+ uint32_t CurrClock[PPCLK_COUNT];
+
+ uint16_t AverageGfxclkFrequencyPreDs;
+ uint16_t AverageGfxclkFrequencyPostDs;
+ uint16_t AverageFclkFrequencyPreDs;
+ uint16_t AverageFclkFrequencyPostDs;
+ uint16_t AverageUclkFrequencyPreDs;
+ uint16_t AverageUclkFrequencyPostDs;
+
+
+ uint16_t AverageGfxActivity;
+ uint16_t AverageUclkActivity;
+ uint8_t CurrSocVoltageOffset;
+ uint8_t CurrGfxVoltageOffset;
+ uint8_t CurrMemVidOffset;
+ uint8_t Padding8;
+ uint16_t AverageSocketPower;
+ uint16_t TemperatureEdge;
+ uint16_t TemperatureHotspot;
+ uint16_t TemperatureMem;
+ uint16_t TemperatureVrGfx;
+ uint16_t TemperatureVrMem0;
+ uint16_t TemperatureVrMem1;
+ uint16_t TemperatureVrSoc;
+ uint16_t TemperatureLiquid0;
+ uint16_t TemperatureLiquid1;
+ uint16_t TemperaturePlx;
+ uint16_t Padding16;
+ uint32_t AccCnt;
+ uint8_t ThrottlingPercentage[THROTTLER_COUNT];
+
+
+ uint8_t LinkDpmLevel;
+ uint8_t CurrFanPwm;
+ uint16_t CurrFanSpeed;
+
+ //BACO metrics, PMFW-1721
+ //metrics for D3hot entry/exit and driver ARM msgs
+ uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
+ uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];
+ uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];
+
+ //PMFW-4362
+ uint32_t EnergyAccumulator;
+ uint16_t AverageVclk0Frequency;
+ uint16_t AverageDclk0Frequency;
+ uint16_t AverageVclk1Frequency;
+ uint16_t AverageDclk1Frequency;
+ uint16_t VcnUsagePercentage0;
+ uint16_t VcnUsagePercentage1;
+ uint8_t PcieRate;
+ uint8_t PcieWidth;
+ uint16_t AverageGfxclkFrequencyTarget;
+
+ uint8_t ApuSTAPMSmartShiftLimit;
+ uint8_t AverageApuSocketPower;
+ uint8_t ApuSTAPMLimit;
+ uint8_t Padding8_2;
+
+} SmuMetrics_V4_t;
+
typedef struct {
union {
SmuMetrics_t SmuMetrics;
SmuMetrics_V2_t SmuMetrics_V2;
SmuMetrics_V3_t SmuMetrics_V3;
+ SmuMetrics_V4_t SmuMetrics_V4;
};
uint32_t Spare[1];
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 86ab276b6b0b..503439754f08 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -585,6 +585,102 @@ static uint32_t
sienna_cichlid_get_throttler_status_locked(struct smu_context *s
return throttler_status;
}
+static int sienna_cichlid_get_power_limit(struct smu_context *smu,
+ uint32_t *current_power_limit,
+ uint32_t *default_power_limit,
+ uint32_t *max_power_limit)
+{
+ struct smu_11_0_7_powerplay_table *powerplay_table =
+ (struct smu_11_0_7_powerplay_table
*)smu->smu_table.power_play_table;
+ uint32_t power_limit, od_percent;
+ uint16_t *table_member;
+
+ GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
+
+ if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
+ power_limit =
+ table_member[PPT_THROTTLER_PPT0];
+ }
+
+ if (current_power_limit)
+ *current_power_limit = power_limit;
+ if (default_power_limit)
+ *default_power_limit = power_limit;
+
+ if (max_power_limit) {
+ if (smu->od_enabled) {
+ od_percent =
+
le32_to_cpu(powerplay_table->overdrive_table.max[
+
SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
+
+ dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d
(default: %d)\n",
+ od_percent, power_limit);
+
+ power_limit *
