Re: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kenneth Feng
在 2020/8/6 下午5:42，“Gao, Likun” 写入:
From: Likun Gao
Update drive if file for sienna_cichlid.
Signed-off-by: Likun Gao
Change-Id: If405461cfbe0133ceb61fa123272b2e53db99755
---
.../drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h | 6 +++---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git
a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index aa2708fccb6d..5ef9c92f57c4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x34
+#define SMU11_DRIVER_IF_VERSION 0x35
#define PPTABLE_Sienna_Cichlid_SMU_VERSION 5
@@ -127,7 +127,7 @@
#define FEATURE_DF_CSTATE_BIT 45
#define FEATURE_2_STEP_PSTATE_BIT 46
#define FEATURE_SMNCLK_DPM_BIT 47
-#define FEATURE_SPARE_48_BIT48
+#define FEATURE_PERLINK_GMIDOWN_BIT 48
#define FEATURE_GFX_EDC_BIT 49
#define FEATURE_SPARE_50_BIT50
#define FEATURE_SPARE_51_BIT51
@@ -169,7 +169,7 @@ typedef enum {
#define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN 0x0200
#define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x0400
#define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCEFCLK 0x0800
-#define DPM_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x1000
+#define DPM_OVERRIDE_ENABLE_FAST_FCLK_TIMER 0x1000
#define DPM_OVERRIDE_DISABLE_VCN_PG 0x2000
#define DPM_OVERRIDE_DISABLE_FMAX_VMAX 0x4000
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 6a42331aba8a..737b6d14372c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x33
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x35
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x3
/* MP Apertures */
--
2.25.1
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[PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
From: Likun Gao
Update drive if file for sienna_cichlid.
Signed-off-by: Likun Gao
Change-Id: If405461cfbe0133ceb61fa123272b2e53db99755
---
.../drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h | 6 +++---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index aa2708fccb6d..5ef9c92f57c4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x34
+#define SMU11_DRIVER_IF_VERSION 0x35
#define PPTABLE_Sienna_Cichlid_SMU_VERSION 5
@@ -127,7 +127,7 @@
#define FEATURE_DF_CSTATE_BIT 45
#define FEATURE_2_STEP_PSTATE_BIT 46
#define FEATURE_SMNCLK_DPM_BIT 47
-#define FEATURE_SPARE_48_BIT48
+#define FEATURE_PERLINK_GMIDOWN_BIT 48
#define FEATURE_GFX_EDC_BIT 49
#define FEATURE_SPARE_50_BIT50
#define FEATURE_SPARE_51_BIT51
@@ -169,7 +169,7 @@ typedef enum {
#define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN 0x0200
#define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x0400
#define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCEFCLK 0x0800
-#define DPM_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x1000
+#define DPM_OVERRIDE_ENABLE_FAST_FCLK_TIMER 0x1000
#define DPM_OVERRIDE_DISABLE_VCN_PG 0x2000
#define DPM_OVERRIDE_DISABLE_FMAX_VMAX 0x4000
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 6a42331aba8a..737b6d14372c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x33
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x35
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x3
/* MP Apertures */
--
2.25.1
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Re: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kenneth Feng
在 2020/7/24 下午5:39，“Gao, Likun” 写入:
From: Likun Gao
Update sienna_cichlid driver if header and related files.
Support new smu metrics for pre & postDS frequency.
Signed-off-by: Likun Gao
Change-Id: I5446256fd7082a1d51df4ade3828bf5fa1ea3e7f
---
.../inc/smu11_driver_if_sienna_cichlid.h | 21 +--
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 11 +++---
3 files changed, 24 insertions(+), 10 deletions(-)
diff --git
a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index b2232e24d82f..aa2708fccb6d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x33
+#define SMU11_DRIVER_IF_VERSION 0x34
#define PPTABLE_Sienna_Cichlid_SMU_VERSION 5
@@ -968,9 +968,15 @@ typedef struct {
typedef struct {
uint32_t CurrClock[PPCLK_COUNT];
- uint16_t AverageGfxclkFrequency;
- uint16_t AverageFclkFrequency;
- uint16_t AverageUclkFrequency ;
+
+ uint16_t AverageGfxclkFrequencyPreDs;
+ uint16_t AverageGfxclkFrequencyPostDs;
+ uint16_t AverageFclkFrequencyPreDs;
+ uint16_t AverageFclkFrequencyPostDs;
+ uint16_t AverageUclkFrequencyPreDs ;
+ uint16_t AverageUclkFrequencyPostDs ;
+
+
uint16_t AverageGfxActivity;
uint16_t AverageUclkActivity ;
uint8_t CurrSocVoltageOffset ;
@@ -988,6 +994,7 @@ typedef struct {
uint16_t TemperatureLiquid0;
uint16_t TemperatureLiquid1;
uint16_t TemperaturePlx;
+ uint16_t Padding16 ;
uint32_t ThrottlerStatus ;
uint8_t LinkDpmLevel;
@@ -1006,8 +1013,10 @@ typedef struct {
uint16_t AverageDclk0Frequency ;
uint16_t AverageVclk1Frequency ;
uint16_t AverageDclk1Frequency ;
- uint16_t VcnActivityPercentage ; //place holder, David N. to provide
full sequence
- uint16_t padding16_2;
+ uint16_t VcnActivityPercentage ; //place holder, David N. to provide
full sequence
+ uint8_t PcieRate ;
+ uint8_t PcieWidth ;
+
} SmuMetrics_t;
typedef struct {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 429f5aa8924a..9504f9954fd3 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x33
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x2
/* MP Apertures */
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index dcc5d25a7894..f64a1be94cb8 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -70,6 +70,8 @@
FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
+#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
+
static struct cmn2asic_msg_mapping
sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage,PPSMC_MSG_TestMessage, 1),
MSG_MAP(GetSmuVersion,PPSMC_MSG_GetSmuVersion, 1),
@@ -443,13 +445,16 @@ static int sienna_cichlid_get_smu_metrics_data(struct
smu_context *smu,
*value = metrics->CurrClock[PPCLK_DCEFCLK];
break;
case METRICS_AVERAGE_GFXCLK:
-*value = metrics->AverageGfxclkFrequency;
+if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
+*value = metrics->AverageGfxclkFrequencyPostDs;
+else
+*value = metrics->AverageGfxclkFrequencyPreDs;
break;
case METRICS_AVERAGE_FCLK:
-*value = metrics->AverageFclkFrequency;
+*value = metrics->AverageFclkFrequencyPostDs;
break;
case METRICS_AVERAGE_UCLK:
-*value = metrics->AverageUclkFrequency;
+*value = metrics->AverageUclkFrequencyPostDs;
break;
case METRICS_AVERAGE_GFXACTIVITY:
*value = metrics->AverageGfxActivity;
--
2.25.1
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RE: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
[AMD Official Use Only - Internal Distribution Only]
See my comments below.
-Original Message-
From: Gao, Likun
Sent: Friday, July 24, 2020 5:39 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth
; Chen, Jiansong (Simon) ; Gao,
Likun
Subject: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
From: Likun Gao
Update sienna_cichlid driver if header and related files.
Support new smu metrics for pre & postDS frequency.
Signed-off-by: Likun Gao
Change-Id: I5446256fd7082a1d51df4ade3828bf5fa1ea3e7f
---
.../inc/smu11_driver_if_sienna_cichlid.h | 21 +--
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 11 +++---
3 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index b2232e24d82f..aa2708fccb6d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if // any structure is
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x33
+#define SMU11_DRIVER_IF_VERSION 0x34
#define PPTABLE_Sienna_Cichlid_SMU_VERSION 5
@@ -968,9 +968,15 @@ typedef struct {
typedef struct {
uint32_t CurrClock[PPCLK_COUNT];
- uint16_t AverageGfxclkFrequency;
- uint16_t AverageFclkFrequency;
- uint16_t AverageUclkFrequency ;
+
+ uint16_t AverageGfxclkFrequencyPreDs; uint16_t
+ AverageGfxclkFrequencyPostDs; uint16_t AverageFclkFrequencyPreDs;
+ uint16_t AverageFclkFrequencyPostDs; uint16_t
+ AverageUclkFrequencyPreDs ; uint16_t AverageUclkFrequencyPostDs ;
+
+
uint16_t AverageGfxActivity;
uint16_t AverageUclkActivity ;
uint8_t CurrSocVoltageOffset ;
@@ -988,6 +994,7 @@ typedef struct {
uint16_t TemperatureLiquid0;
uint16_t TemperatureLiquid1;
uint16_t TemperaturePlx;
+ uint16_t Padding16 ;
uint32_t ThrottlerStatus ;
uint8_t LinkDpmLevel;
@@ -1006,8 +1013,10 @@ typedef struct {
uint16_t AverageDclk0Frequency ;
uint16_t AverageVclk1Frequency ;
uint16_t AverageDclk1Frequency ;
- uint16_t VcnActivityPercentage ; //place holder, David N. to provide full
sequence
- uint16_t padding16_2;
+ uint16_t VcnActivityPercentage ; //place holder, David N. to provide full
sequence
+ uint8_t PcieRate ;
+ uint8_t PcieWidth ;
+
} SmuMetrics_t;
typedef struct {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 429f5aa8924a..9504f9954fd3 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36 #define
SMU11_DRIVER_IF_VERSION_NV12 0x33 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x2
/* MP Apertures */
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index dcc5d25a7894..f64a1be94cb8 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -70,6 +70,8 @@
FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
+#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
+
static struct cmn2asic_msg_mapping
sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage,PPSMC_MSG_TestMessage, 1),
MSG_MAP(GetSmuVersion,PPSMC_MSG_GetSmuVersion, 1),
@@ -443,13 +445,16 @@ static int sienna_cichlid_get_smu_metrics_data(struct
smu_context *smu,
*value = metrics->CurrClock[PPCLK_DCEFCLK];
break;
case METRICS_AVERAGE_GFXCLK:
-*value = metrics->AverageGfxclkFrequency;
+if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
+*value = metrics->AverageGfxclkFrequencyPostDs;
+else
+*value = metrics->AverageGfxclkFrequencyPreDs;
break;
[Jiansong] why fclk and uclk don't follow similar change as gfxclk, since all
will enter DS when in idle state.
case METRICS_AVERAGE_FCLK:
-*value = metrics->AverageFclkFrequency;
+*value = metrics->AverageFclkFrequencyPostDs;
break;
case METRICS_AVERAGE_UCLK:
-*value = metrics->AverageUclkFrequency;
+*value = metrics->AverageUclkFrequencyPostDs;
break;
case METRICS_AVERAGE_GFXACTIVITY:
*value = metrics->AverageGfxActivity;
--
2.25.1
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RE: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kenneth Feng
Best Regards
Kenneth
-Original Message-
From: Gao, Likun
Sent: Friday, July 10, 2020 11:10 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth
; Gao, Likun
Subject: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
From: Likun Gao
Update sienna_cichlid driver if header and related files.
Signed-off-by: Likun Gao
Change-Id: If303e7fca32ebf922ee5d918855bbaca8dc61d38
---
.../inc/smu11_driver_if_sienna_cichlid.h| 17 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
.../gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 -
3 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index 302c2bcf9404..b2232e24d82f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,9 +27,9 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if // any structure is
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x32
+#define SMU11_DRIVER_IF_VERSION 0x33
-#define PPTABLE_Sienna_Cichlid_SMU_VERSION 4
+#define PPTABLE_Sienna_Cichlid_SMU_VERSION 5
#define NUM_GFXCLK_DPM_LEVELS 16
#define NUM_SMNCLK_DPM_LEVELS 2
@@ -128,7 +128,7 @@
#define FEATURE_2_STEP_PSTATE_BIT 46
#define FEATURE_SMNCLK_DPM_BIT 47
#define FEATURE_SPARE_48_BIT48
-#define FEATURE_SPARE_49_BIT49
+#define FEATURE_GFX_EDC_BIT 49
#define FEATURE_SPARE_50_BIT50
#define FEATURE_SPARE_51_BIT51
#define FEATURE_SPARE_52_BIT52
@@ -564,6 +564,12 @@ typedef enum {
TDC_THROTTLER_COUNT
} TDC_THROTTLER_e;
+typedef enum {
+ CUSTOMER_VARIANT_ROW,
+ CUSTOMER_VARIANT_FALCON,
+ CUSTOMER_VARIANT_COUNT,
+} CUSTOMER_VARIANT_e;
+
// Used for 2-step UCLK DPM change workaround typedef struct {
uint16_t Fmin;
@@ -786,7 +792,10 @@ typedef struct {
QuadraticInt_tReservedEquation3;
// SECTION: Sku Reserved
- uint32_t SkuReserved[15];
+ uint8_t CustomerVariant;
+ uint8_t Spare[3];
+ uint32_t SkuReserved[14];
+
// MAJOR SECTION: BOARD PARAMETERS
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index d07bf4fe6e4a..b2f65438ad8d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36 #define
SMU11_DRIVER_IF_VERSION_NV12 0x33 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x32
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33
/* MP Apertures */
#define MP0_Public 0x0380
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index dc5ca9121db5..3efa41444ddf 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -2317,7 +2317,6 @@ static void sienna_cichlid_dump_pptable(struct
smu_context *smu)
dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n",
pptable->SkuReserved[11]);
dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n",
pptable->SkuReserved[12]);
dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n",
pptable->SkuReserved[13]);
- dev_info(smu->adev->dev, "SkuReserved[14] = 0x%x\n",
pptable->SkuReserved[14]);
dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n",
pptable->GamingClk[0]);
dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n",
pptable->GamingClk[1]);
--
2.25.1
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[PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
From: Likun Gao
Update sienna_cichlid driver if header and related files.
Signed-off-by: Likun Gao
Change-Id: If303e7fca32ebf922ee5d918855bbaca8dc61d38
---
.../inc/smu11_driver_if_sienna_cichlid.h| 17 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
.../gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 -
3 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index 302c2bcf9404..b2232e24d82f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,9 +27,9 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x32
+#define SMU11_DRIVER_IF_VERSION 0x33
-#define PPTABLE_Sienna_Cichlid_SMU_VERSION 4
+#define PPTABLE_Sienna_Cichlid_SMU_VERSION 5
#define NUM_GFXCLK_DPM_LEVELS 16
#define NUM_SMNCLK_DPM_LEVELS 2
@@ -128,7 +128,7 @@
#define FEATURE_2_STEP_PSTATE_BIT 46
#define FEATURE_SMNCLK_DPM_BIT 47
#define FEATURE_SPARE_48_BIT48
-#define FEATURE_SPARE_49_BIT49
+#define FEATURE_GFX_EDC_BIT 49
#define FEATURE_SPARE_50_BIT50
#define FEATURE_SPARE_51_BIT51
#define FEATURE_SPARE_52_BIT52
@@ -564,6 +564,12 @@ typedef enum {
TDC_THROTTLER_COUNT
} TDC_THROTTLER_e;
+typedef enum {
+ CUSTOMER_VARIANT_ROW,
+ CUSTOMER_VARIANT_FALCON,
+ CUSTOMER_VARIANT_COUNT,
+} CUSTOMER_VARIANT_e;
+
// Used for 2-step UCLK DPM change workaround
typedef struct {
uint16_t Fmin;
@@ -786,7 +792,10 @@ typedef struct {
QuadraticInt_tReservedEquation3;
// SECTION: Sku Reserved
- uint32_t SkuReserved[15];
+ uint8_t CustomerVariant;
+ uint8_t Spare[3];
+ uint32_t SkuReserved[14];
+
// MAJOR SECTION: BOARD PARAMETERS
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index d07bf4fe6e4a..b2f65438ad8d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x33
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x32
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33
/* MP Apertures */
#define MP0_Public 0x0380
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index dc5ca9121db5..3efa41444ddf 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -2317,7 +2317,6 @@ static void sienna_cichlid_dump_pptable(struct
smu_context *smu)
dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n",
pptable->SkuReserved[11]);
dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n",
pptable->SkuReserved[12]);
dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n",
pptable->SkuReserved[13]);
- dev_info(smu->adev->dev, "SkuReserved[14] = 0x%x\n",
pptable->SkuReserved[14]);
dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n",
pptable->GamingClk[0]);
dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n",
pptable->GamingClk[1]);
--
2.25.1
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[PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
From: Likun Gao
Update sienna_cichlid driver if header and related files.
Signed-off-by: Likun Gao
Change-Id: If303e7fca32ebf922ee5d918855bbaca8dc61d38
---
.../inc/smu11_driver_if_sienna_cichlid.h| 17 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
.../gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 -
3 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index 302c2bcf9404..b2232e24d82f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,9 +27,9 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x32
+#define SMU11_DRIVER_IF_VERSION 0x33
-#define PPTABLE_Sienna_Cichlid_SMU_VERSION 4
+#define PPTABLE_Sienna_Cichlid_SMU_VERSION 5
#define NUM_GFXCLK_DPM_LEVELS 16
#define NUM_SMNCLK_DPM_LEVELS 2
@@ -128,7 +128,7 @@
#define FEATURE_2_STEP_PSTATE_BIT 46
#define FEATURE_SMNCLK_DPM_BIT 47
#define FEATURE_SPARE_48_BIT48
-#define FEATURE_SPARE_49_BIT49
+#define FEATURE_GFX_EDC_BIT 49
#define FEATURE_SPARE_50_BIT50
#define FEATURE_SPARE_51_BIT51
#define FEATURE_SPARE_52_BIT52
@@ -564,6 +564,12 @@ typedef enum {
TDC_THROTTLER_COUNT
} TDC_THROTTLER_e;
+typedef enum {
+ CUSTOMER_VARIANT_ROW,
+ CUSTOMER_VARIANT_FALCON,
+ CUSTOMER_VARIANT_COUNT,
+} CUSTOMER_VARIANT_e;
+
// Used for 2-step UCLK DPM change workaround
typedef struct {
uint16_t Fmin;
@@ -786,7 +792,10 @@ typedef struct {
QuadraticInt_tReservedEquation3;
// SECTION: Sku Reserved
- uint32_t SkuReserved[15];
+ uint8_t CustomerVariant;
+ uint8_t Spare[3];
+ uint32_t SkuReserved[14];
+
// MAJOR SECTION: BOARD PARAMETERS
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index d07bf4fe6e4a..b2f65438ad8d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x33
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x32
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33
/* MP Apertures */
#define MP0_Public 0x0380
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index dc5ca9121db5..3efa41444ddf 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -2317,7 +2317,6 @@ static void sienna_cichlid_dump_pptable(struct
smu_context *smu)
dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n",
pptable->SkuReserved[11]);
dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n",
pptable->SkuReserved[12]);
dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n",
pptable->SkuReserved[13]);
- dev_info(smu->adev->dev, "SkuReserved[14] = 0x%x\n",
pptable->SkuReserved[14]);
dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n",
pptable->GamingClk[0]);
dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n",
pptable->GamingClk[1]);
--
2.25.1
___
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RE: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kenneth Feng
Best Regards
Kenneth
-Original Message-
From: Gao, Likun
Sent: Wednesday, June 3, 2020 12:36 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Quan, Evan ; Gao,
Likun
Subject: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
From: Likun Gao
Update sienna_cichlid driver if header file to match pptable changes.
Signed-off-by: Likun Gao
Change-Id: Ie0652935d512124c03f16ae75c44e134567ef5da
---
.../inc/smu11_driver_if_sienna_cichlid.h| 17 ++---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index bdffba1f0086..5322f6da3071 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if // any structure is
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x30
+#define SMU11_DRIVER_IF_VERSION 0x31
#define PPTABLE_Sienna_Cichlid_SMU_VERSION 4
@@ -914,12 +914,14 @@ typedef struct {
uint16_t GfxActivityLpfTau;
uint16_t UclkActivityLpfTau;
uint16_t SocketPowerLpfTau;
+ uint16_t VcnClkAverageLpfTau;
+ uint16_t padding16;
} DriverSmuConfig_t;
typedef struct {
DriverSmuConfig_t DriverSmuConfig;
- uint32_t Spare[8];
+ uint32_t Spare[7];
// Padding - ignore
uint32_t MmHubPadding[8]; // SMU internal use
} DriverSmuConfigExternal_t;
@@ -984,11 +986,20 @@ typedef struct {
uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];
uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];
+
+ //PMFW-4362
+ uint32_t EnergyAccumulator;
+ uint16_t AverageVclk0Frequency ;
+ uint16_t AverageDclk0Frequency ;
+ uint16_t AverageVclk1Frequency ;
+ uint16_t AverageDclk1Frequency ;
+ uint16_t VcnActivityPercentage ; //place holder, David N. to provide
+ full sequence uint16_t padding16_2;
} SmuMetrics_t;
typedef struct {
SmuMetrics_t SmuMetrics;
- uint32_t Spare[5];
+ uint32_t Spare[1];
// Padding - ignore
uint32_t MmHubPadding[8]; // SMU internal use
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 4ad3f07891fe..282eb45e7b86 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -31,7 +31,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36 #define
SMU11_DRIVER_IF_VERSION_NV12 0x33 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x30
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x31
/* MP Apertures */
#define MP0_Public 0x0380
--
2.25.1
___
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[PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
From: Likun Gao
Update sienna_cichlid driver if header file to match pptable changes.
Signed-off-by: Likun Gao
Change-Id: Ie0652935d512124c03f16ae75c44e134567ef5da
---
.../inc/smu11_driver_if_sienna_cichlid.h| 17 ++---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index bdffba1f0086..5322f6da3071 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x30
+#define SMU11_DRIVER_IF_VERSION 0x31
#define PPTABLE_Sienna_Cichlid_SMU_VERSION 4
@@ -914,12 +914,14 @@ typedef struct {
uint16_t GfxActivityLpfTau;
uint16_t UclkActivityLpfTau;
uint16_t SocketPowerLpfTau;
+ uint16_t VcnClkAverageLpfTau;
+ uint16_t padding16;
} DriverSmuConfig_t;
typedef struct {
DriverSmuConfig_t DriverSmuConfig;
- uint32_t Spare[8];
+ uint32_t Spare[7];
// Padding - ignore
uint32_t MmHubPadding[8]; // SMU internal use
} DriverSmuConfigExternal_t;
@@ -984,11 +986,20 @@ typedef struct {
uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];
uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];
+
+ //PMFW-4362
+ uint32_t EnergyAccumulator;
+ uint16_t AverageVclk0Frequency ;
+ uint16_t AverageDclk0Frequency ;
+ uint16_t AverageVclk1Frequency ;
+ uint16_t AverageDclk1Frequency ;
+ uint16_t VcnActivityPercentage ; //place holder, David N. to provide full
sequence
+ uint16_t padding16_2;
} SmuMetrics_t;
typedef struct {
SmuMetrics_t SmuMetrics;
- uint32_t Spare[5];
+ uint32_t Spare[1];
// Padding - ignore
uint32_t MmHubPadding[8]; // SMU internal use
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 4ad3f07891fe..282eb45e7b86 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -31,7 +31,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x33
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x30
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x31
/* MP Apertures */
#define MP0_Public 0x0380
--
2.25.1
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