Re: [PATCH] drm/amd/pp: Implement get_performance_level for legacy dgpu
Hi Rex, On 2018-07-05 04:00 PM, Rex Zhu wrote: > display can get clock info through this function. > implement this function for vega10 and old asics. > from vega12, there is no power state management. so need other > interface to notify display the clock info > > Signed-off-by: Rex Zhu This change broke amdgpu initialization with my Tonga with DC enabled, see the attached kernel log excerpt. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer Jul 6 15:19:56 kaveri kernel: [ 55.653436] BUG: unable to handle kernel paging request at ed016177eaea Jul 6 15:19:56 kaveri kernel: [ 55.653448] PGD 43f370067 P4D 43f370067 PUD 0 Jul 6 15:19:56 kaveri kernel: [ 55.653457] Oops: [#1] SMP KASAN NOPTI Jul 6 15:19:56 kaveri kernel: [ 55.653462] CPU: 2 PID: 4371 Comm: Xorg Tainted: G OE 4.18.0-rc1+ #110 Jul 6 15:19:56 kaveri kernel: [ 55.653466] Hardware name: Micro-Star International Co., Ltd. MS-7A34/B350 TOMAHAWK (MS-7A34), BIOS 1.80 09/13/2017 Jul 6 15:19:56 kaveri kernel: [ 55.653551] RIP: 0010:dce_update_clocks+0x41c/0x790 [amdgpu] Jul 6 15:19:56 kaveri kernel: [ 55.653553] Code: 7b 03 00 00 41 39 e8 45 8b 7d 14 0f 83 69 01 00 00 44 89 c5 48 b8 00 00 00 00 00 fc ff df 49 8d 7c ed 50 48 89 f9 48 c1 e9 03 <0f> b6 04 01 84 c0 74 08 3c 03 0f 8e 2b 03 00 00 4c 89 f1 48 b8 00 Jul 6 15:19:56 kaveri kernel: [ 55.653616] RSP: 0018:8803d2aff2d8 EFLAGS: 00010212 Jul 6 15:19:56 kaveri kernel: [ 55.653621] RAX: dc00 RBX: 8803e4dc5f14 RCX: 11016177eaea Jul 6 15:19:56 kaveri kernel: [ 55.653624] RDX: RSI: RDI: 880b0bbf5750 Jul 6 15:19:56 kaveri kernel: [ 55.653627] RBP: e4dc5f00 R08: e4dc5f00 R09: ed007dc14567 Jul 6 15:19:56 kaveri kernel: [ 55.653630] R10: 8803d2aff380 R11: ed007dc14566 R12: 11007a55fe5d Jul 6 15:19:56 kaveri kernel: [ 55.653633] R13: 8803e4dc5f00 R14: 8803d2aff3b0 R15: Jul 6 15:19:56 kaveri kernel: [ 55.653637] FS: 7f6c226a5dc0() GS:8803ee08() knlGS: Jul 6 15:19:56 kaveri kernel: [ 55.653640] CS: 0010 DS: ES: CR0: 80050033 Jul 6 15:19:56 kaveri kernel: [ 55.653643] CR2: ed016177eaea CR3: 0003c08d CR4: 003406e0 Jul 6 15:19:56 kaveri kernel: [ 55.653646] Call Trace: Jul 6 15:19:56 kaveri kernel: [ 55.653727] ? dce110_set_safe_displaymarks+0x12e/0x260 [amdgpu] Jul 6 15:19:56 kaveri kernel: [ 55.653808] ? dce_clock_read_ss_info+0x420/0x420 [amdgpu] Jul 6 15:19:56 kaveri kernel: [ 55.653885] ? generic_reg_update_ex+0x228/0x500 [amdgpu] Jul 6 15:19:56 kaveri kernel: [ 55.653967] dce100_set_bandwidth+0x22b/0x300 [amdgpu] Jul 6 15:19:56 kaveri kernel: [ 55.654047] ? dce100_pplib_apply_display_requirements+0x1b0/0x1b0 [amdgpu] Jul 6 15:19:56 kaveri kernel: [ 55.654053] ? rcu_read_lock_sched_held+0xdc/0x110 Jul 6 15:19:56 kaveri kernel: [ 55.654134] ? bios_set_scratch_acc_mode_change+0x176/0x220 [amdgpu] Jul 6 15:19:56 kaveri kernel: [ 55.654213] dc_commit_state+0x700/0x16b0 [amdgpu] Jul 6 15:19:56 kaveri kernel: [ 55.654295] ? dc_destroy+0x90/0x90 [amdgpu] Jul 6 15:19:56 kaveri kernel: [ 55.654316] ? drm_dev_dbg+0x1a0/0x1a0 [drm] Jul 6 15:19:56 kaveri kernel: [ 55.654401] amdgpu_dm_atomic_commit_tail+0x961/0x3f90 [amdgpu] Jul 6 15:19:56 kaveri kernel: [ 55.654409] ? mark_held_locks+0xa8/0xf0 Jul 6 15:19:56 kaveri kernel: [ 55.654414] ? trace_hardirqs_on_caller+0x381/0x570 Jul 6 15:19:56 kaveri kernel: [ 55.654419] ? _raw_spin_unlock_irq+0x29/0x40 Jul 6 15:19:56 kaveri kernel: [ 55.654424] ? wait_for_completion_timeout+0xc1/0x390 Jul 6 15:19:56 kaveri kernel: [ 55.654435] ? drm_atomic_helper_swap_state+0x7a2/0x15b0 [drm_kms_helper] Jul 6 15:19:56 kaveri kernel: [ 55.654512] ? amdgpu_dm_do_flip+0xab0/0xab0 [amdgpu] Jul 6 15:19:56 kaveri kernel: [ 55.654517] ? lock_downgrade+0x5e0/0x5e0 Jul 6 15:19:56 kaveri kernel: [ 55.654593] ? dm_plane_helper_prepare_fb+0x291/0xb00 [amdgpu] Jul 6 15:19:56 kaveri kernel: [ 55.654607] ? drm_atomic_helper_wait_for_dependencies+0x255/0x7d0 [drm_kms_helper] Jul 6 15:19:56 kaveri kernel: [ 55.654620] commit_tail+0x9a/0xf0 [drm_kms_helper] Jul 6 15:19:56 kaveri kernel: [ 55.654632] drm_atomic_helper_commit+0x179/0x240 [drm_kms_helper] Jul 6 15:19:56 kaveri kernel: [ 55.654645] drm_atomic_helper_set_config+0xbb/0x100 [drm_kms_helper] Jul 6 15:19:56 kaveri kernel: [ 55.654665] __drm_mode_set_config_internal+0x199/0x4f0 [drm] Jul 6 15:19:56 kaveri kernel: [ 55.654686] drm_mode_setcrtc+0x83f/0xf60 [drm] Jul 6 15:19:56 kaveri kernel: [ 55.654710] ? drm_mode_getcrtc+0x760/0x760 [drm] Jul 6 15:19:56 kaveri kernel: [ 55.654716] ? refcount_inc+0x30/0x30 Jul 6 15:19:56 kaveri kernel: [ 55.654722] ?
Re: [PATCH] drm/amd/pp: Implement get_performance_level for legacy dgpu
On Thu, Jul 5, 2018 at 10:00 AM, Rex Zhu wrote:
> display can get clock info through this function.
> implement this function for vega10 and old asics.
> from vega12, there is no power state management. so need other
> interface to notify display the clock info
>
> Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
> ---
> .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 2 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 24
> ++
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 24
> ++
> 3 files changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> index 53207e7..b05b153 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> @@ -357,7 +357,7 @@ int phm_get_clock_info(struct pp_hwmgr *hwmgr, const
> struct pp_hw_power_state *s
> PHM_PerformanceLevelDesignation designation)
> {
> int result;
> - PHM_PerformanceLevel performance_level;
> + PHM_PerformanceLevel performance_level = {0};
>
> PHM_FUNC_CHECK(hwmgr);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 077b799..8eaaa6b 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -5006,6 +5006,29 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr
> *hwmgr, long *input, uint
> return 0;
> }
>
> +static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct
> pp_hw_power_state *state,
> + PHM_PerformanceLevelDesignation designation,
> uint32_t index,
> + PHM_PerformanceLevel *level)
> +{
> + const struct smu7_power_state *ps;
> + struct smu7_hwmgr *data;
> + uint32_t i;
> +
> + if (level == NULL || hwmgr == NULL || state == NULL)
> + return -EINVAL;
> +
> + data = hwmgr->backend;
> + ps = cast_const_phw_smu7_power_state(state);
> +
> + i = index > ps->performance_level_count - 1 ?
> + ps->performance_level_count - 1 : index;
> +
> + level->coreClock = ps->performance_levels[i].engine_clock;
> + level->memory_clock = ps->performance_levels[i].memory_clock;
> +
> + return 0;
> +}
> +
> static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
> .backend_init = _hwmgr_backend_init,
> .backend_fini = _hwmgr_backend_fini,
> @@ -5062,6 +5085,7 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr
> *hwmgr, long *input, uint
> .set_power_limit = smu7_set_power_limit,
> .get_power_profile_mode = smu7_get_power_profile_mode,
> .set_power_profile_mode = smu7_set_power_profile_mode,
> + .get_performance_level = smu7_get_performance_level,
> };
>
> uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index eb37316..5c03df4 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4837,6 +4837,29 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr
> *hwmgr,
> return 0;
> }
>
> +static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct
> pp_hw_power_state *state,
> + PHM_PerformanceLevelDesignation designation,
> uint32_t index,
> + PHM_PerformanceLevel *level)
> +{
> + const struct vega10_power_state *ps;
> + struct vega10_hwmgr *data;
> + uint32_t i;
> +
> + if (level == NULL || hwmgr == NULL || state == NULL)
> + return -EINVAL;
> +
> + data = hwmgr->backend;
> + ps = cast_const_phw_vega10_power_state(state);
> +
> + i = index > ps->performance_level_count - 1 ?
> + ps->performance_level_count - 1 : index;
> +
> + level->coreClock = ps->performance_levels[i].gfx_clock;
> + level->memory_clock = ps->performance_levels[i].mem_clock;
> +
> + return 0;
> +}
> +
> static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
> .backend_init = vega10_hwmgr_backend_init,
> .backend_fini = vega10_hwmgr_backend_fini,
> @@ -4896,6 +4919,7 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr
> *hwmgr,
> .set_power_profile_mode = vega10_set_power_profile_mode,
> .set_power_limit = vega10_set_power_limit,
> .odn_edit_dpm_table = vega10_odn_edit_dpm_table,
> + .get_performance_level = vega10_get_performance_level,
> };
>
> int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
> --
> 1.9.1
>
> ___
> amd-gfx
[PATCH] drm/amd/pp: Implement get_performance_level for legacy dgpu
display can get clock info through this function.
implement this function for vega10 and old asics.
from vega12, there is no power state management. so need other
interface to notify display the clock info
Signed-off-by: Rex Zhu
---
.../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 24 ++
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 24 ++
3 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 53207e7..b05b153 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -357,7 +357,7 @@ int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct
pp_hw_power_state *s
PHM_PerformanceLevelDesignation designation)
{
int result;
- PHM_PerformanceLevel performance_level;
+ PHM_PerformanceLevel performance_level = {0};
PHM_FUNC_CHECK(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 077b799..8eaaa6b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -5006,6 +5006,29 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr
*hwmgr, long *input, uint
return 0;
}
+static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct
pp_hw_power_state *state,
+ PHM_PerformanceLevelDesignation designation,
uint32_t index,
+ PHM_PerformanceLevel *level)
+{
+ const struct smu7_power_state *ps;
+ struct smu7_hwmgr *data;
+ uint32_t i;
+
+ if (level == NULL || hwmgr == NULL || state == NULL)
+ return -EINVAL;
+
+ data = hwmgr->backend;
+ ps = cast_const_phw_smu7_power_state(state);
+
+ i = index > ps->performance_level_count - 1 ?
+ ps->performance_level_count - 1 : index;
+
+ level->coreClock = ps->performance_levels[i].engine_clock;
+ level->memory_clock = ps->performance_levels[i].memory_clock;
+
+ return 0;
+}
+
static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.backend_init = _hwmgr_backend_init,
.backend_fini = _hwmgr_backend_fini,
@@ -5062,6 +5085,7 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr
*hwmgr, long *input, uint
.set_power_limit = smu7_set_power_limit,
.get_power_profile_mode = smu7_get_power_profile_mode,
.set_power_profile_mode = smu7_set_power_profile_mode,
+ .get_performance_level = smu7_get_performance_level,
};
uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index eb37316..5c03df4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4837,6 +4837,29 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr
*hwmgr,
return 0;
}
+static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct
pp_hw_power_state *state,
+ PHM_PerformanceLevelDesignation designation,
uint32_t index,
+ PHM_PerformanceLevel *level)
+{
+ const struct vega10_power_state *ps;
+ struct vega10_hwmgr *data;
+ uint32_t i;
+
+ if (level == NULL || hwmgr == NULL || state == NULL)
+ return -EINVAL;
+
+ data = hwmgr->backend;
+ ps = cast_const_phw_vega10_power_state(state);
+
+ i = index > ps->performance_level_count - 1 ?
+ ps->performance_level_count - 1 : index;
+
+ level->coreClock = ps->performance_levels[i].gfx_clock;
+ level->memory_clock = ps->performance_levels[i].mem_clock;
+
+ return 0;
+}
+
static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
.backend_init = vega10_hwmgr_backend_init,
.backend_fini = vega10_hwmgr_backend_fini,
@@ -4896,6 +4919,7 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr
*hwmgr,
.set_power_profile_mode = vega10_set_power_profile_mode,
.set_power_limit = vega10_set_power_limit,
.odn_edit_dpm_table = vega10_odn_edit_dpm_table,
+ .get_performance_level = vega10_get_performance_level,
};
int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
--
1.9.1
___
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