[PATCH] drm/amdgpu/gfx10: fix mixed declaration and code warning

[Alex Deucher]

Move the declaration up to the top of the function.

Fixes: 631d55e089eaa8 ("drm/amdgpu: Add error message when programing registers 
fails")
Cc: Roy Sun 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ca06fb137cac..d102cfd36ba2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1493,6 +1493,7 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, 
u32 offset, u32 v, uint32
uint32_t i = 0;
uint32_t retries = 5;
u32 ret = 0;
+   u32 tmp;
 
scratch_reg0 = adev->rmmio +
   (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + 
mmSCRATCH_REG0) * 4;
@@ -1526,7 +1527,6 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, 
u32 offset, u32 v, uint32
writel(v, scratch_reg0);
writel(offset | flag, scratch_reg1);
writel(1, spare_int);
-   u32 tmp;
 
for (i = 0; i < retries; i++) {
tmp = readl(scratch_reg1);
-- 
2.31.1

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Re: [PATCH] drm/amdgpu/gfx10: fix mixed declaration and code warning

[Christian König]

Am 21.07.21 um 05:14 schrieb Alex Deucher:

Move the declaration up to the top of the function.

Fixes: 631d55e089eaa8 ("drm/amdgpu: Add error message when programing registers 
fails")
Cc: Roy Sun 
Signed-off-by: Alex Deucher 


Acked-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ca06fb137cac..d102cfd36ba2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1493,6 +1493,7 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, 
u32 offset, u32 v, uint32
uint32_t i = 0;
uint32_t retries = 5;
u32 ret = 0;
+   u32 tmp;
  
  	scratch_reg0 = adev->rmmio +

   (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + 
mmSCRATCH_REG0) * 4;
@@ -1526,7 +1527,6 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, 
u32 offset, u32 v, uint32
writel(v, scratch_reg0);
writel(offset | flag, scratch_reg1);
writel(1, spare_int);
-   u32 tmp;
  
  		for (i = 0; i < retries; i++) {

tmp = readl(scratch_reg1);


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