RE: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc
Ok, see you newly patch DCFCLK_DPM_LEVELS has been aligned well.
Thanks,
Prike
> -Original Message-
> From: amd-gfx On Behalf Of Liang,
> Prike
> Sent: Wednesday, October 16, 2019 10:22 AM
> To: Wu, Hersen ; amd-gfx@lists.freedesktop.org
> Cc: Wentland, Harry ; Wang, Kevin(Yang)
> ; Wu, Hersen
> Subject: RE: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support
> dc
>
> Regards the comment inline, saw you have fixed the not enable
> CONFIG_DRM_AMD_DC_DCN2_1 potential compile issue.
>
> BTW, would you help clarify why PP_SMU_NUM_DCFCLK_DPM_LEVELS is
> different from the smu12_driver_if.h define NUM_DCFCLK_DPM_LEVELS .
> Is there can track the macro definition update ?
>
> Thanks,
> Prike
> > -Original Message-
> > From: Liang, Prike
> > Sent: Friday, October 11, 2019 10:34 PM
> > To: Hersen Wu ; amd-gfx@lists.freedesktop.org
> > Cc: Wu, Hersen ; Wang, Kevin(Yang)
> > ; Wentland, Harry
> > Subject: RE: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support
> > dc
> >
> >
> >
> > > -Original Message-
> > > From: amd-gfx On Behalf Of
> > > Hersen Wu
> > > Sent: Thursday, October 10, 2019 10:58 PM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Wu, Hersen ; Wang, Kevin(Yang)
> > > ; Wentland, Harry
>
> > > Subject: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support
> > > dc
> > >
> > > there are two paths for renoir dc access smu.
> > > one dc access smu directly using bios smc
> > > interface: set disply, dprefclk, etc.
> > > another goes through pplib for get dpm clock table and set watermmark.
> > >
> > > Signed-off-by: Hersen Wu
> > > ---
> > > .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 16 +---
> > > drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 35 +++
> > > .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 16 ++--
> > > drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 96
> > > +++
> > > drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 39
> > > 5 files changed, 141 insertions(+), 61 deletions(-)
> > >
> > > diff --git
> > > a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> > > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> > > index f4cfa0caeba8..95564b8de3ce 100644
> > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> > > +++
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> > > @@ -589,10 +589,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
> > > if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
> > > pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
> > >
> > > &wm_with_clock_ranges);
> > > - else if (adev->smu.funcs &&
> > > - adev->smu.funcs->set_watermarks_for_clock_ranges)
> > > + else
> > > smu_set_watermarks_for_clock_ranges(&adev->smu,
> > > - &wm_with_clock_ranges);
> > > + &wm_with_clock_ranges);
> > > }
> > >
> > > void pp_rv_set_pme_wa_enable(struct pp_smu *pp) @@ -665,7 +664,6
> > @@
> > > enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp, {
> > > const struct dc_context *ctx = pp->dm;
> > > struct amdgpu_device *adev = ctx->driver_context;
> > > - struct smu_context *smu = &adev->smu;
> > > struct dm_pp_wm_sets_with_clock_ranges_soc15
> > > wm_with_clock_ranges;
> > > struct dm_pp_clock_range_for_dmif_wm_set_soc15
> > > *wm_dce_clocks =
> > > wm_with_clock_ranges.wm_dmif_clocks_ranges;
> > > @@ -708,15 +706,7 @@ enum pp_smu_status
> > pp_nv_set_wm_ranges(struct
> > > pp_smu *pp,
> > > ranges->writer_wm_sets[i].min_drain_clk_mhz *
> > 1000;
> > > }
> > >
> > > - if (!smu->funcs)
> > > - return PP_SMU_RESULT_UNSUPPORTED;
> > > -
> > > - /* 0: successful or smu.funcs->set_watermarks_for_clock_ranges =
> > > NULL;
> > > - * 1: fail
> > > - */
> > > - if (smu_set_watermarks_for_clock_ranges(&adev->smu,
> > > - &wm_with_clock_ranges))
> > > - return PP_SMU_RESULT_UNSUPPORTED;
> > > + smu_set_watermarks_for_clock_ranges(&adev->smu,
> > > &wm_with_clock_ranges);
> &
RE: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc
Regards the comment inline, saw you have fixed the not enable
CONFIG_DRM_AMD_DC_DCN2_1 potential compile issue.
BTW, would you help clarify why PP_SMU_NUM_DCFCLK_DPM_LEVELS is different from
the smu12_driver_if.h define NUM_DCFCLK_DPM_LEVELS .
Is there can track the macro definition update ?
Thanks,
Prike
> -Original Message-
> From: Liang, Prike
> Sent: Friday, October 11, 2019 10:34 PM
> To: Hersen Wu ; amd-gfx@lists.freedesktop.org
> Cc: Wu, Hersen ; Wang, Kevin(Yang)
> ; Wentland, Harry
> Subject: RE: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support
> dc
>
>
>
> > -Original Message-
> > From: amd-gfx On Behalf Of
> > Hersen Wu
> > Sent: Thursday, October 10, 2019 10:58 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Wu, Hersen ; Wang, Kevin(Yang)
> > ; Wentland, Harry
> > Subject: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc
> >
> > there are two paths for renoir dc access smu.
> > one dc access smu directly using bios smc
> > interface: set disply, dprefclk, etc.
> > another goes through pplib for get dpm clock table and set watermmark.
> >
> > Signed-off-by: Hersen Wu
> > ---
> > .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 16 +---
> > drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 35 +++
> > .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 16 ++--
> > drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 96
> > +++
> > drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 39
> > 5 files changed, 141 insertions(+), 61 deletions(-)
> >
> > diff --git
> > a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> > index f4cfa0caeba8..95564b8de3ce 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> > @@ -589,10 +589,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
> > if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
> > pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
> >
> > &wm_with_clock_ranges);
> > - else if (adev->smu.funcs &&
> > -adev->smu.funcs->set_watermarks_for_clock_ranges)
> > + else
> > smu_set_watermarks_for_clock_ranges(&adev->smu,
> > - &wm_with_clock_ranges);
> > + &wm_with_clock_ranges);
> > }
> >
> > void pp_rv_set_pme_wa_enable(struct pp_smu *pp) @@ -665,7 +664,6
> @@
> > enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp, {
> > const struct dc_context *ctx = pp->dm;
> > struct amdgpu_device *adev = ctx->driver_context;
> > - struct smu_context *smu = &adev->smu;
> > struct dm_pp_wm_sets_with_clock_ranges_soc15
> > wm_with_clock_ranges;
> > struct dm_pp_clock_range_for_dmif_wm_set_soc15
> > *wm_dce_clocks =
> > wm_with_clock_ranges.wm_dmif_clocks_ranges;
> > @@ -708,15 +706,7 @@ enum pp_smu_status
> pp_nv_set_wm_ranges(struct
> > pp_smu *pp,
> > ranges->writer_wm_sets[i].min_drain_clk_mhz *
> 1000;
> > }
> >
> > - if (!smu->funcs)
> > - return PP_SMU_RESULT_UNSUPPORTED;
> > -
> > - /* 0: successful or smu.funcs->set_watermarks_for_clock_ranges =
> > NULL;
> > -* 1: fail
> > -*/
> > - if (smu_set_watermarks_for_clock_ranges(&adev->smu,
> > - &wm_with_clock_ranges))
> > - return PP_SMU_RESULT_UNSUPPORTED;
> > + smu_set_watermarks_for_clock_ranges(&adev->smu,
> > &wm_with_clock_ranges);
> >
> > return PP_SMU_RESULT_OK;
> > }
> > diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > index c9266ea70331..1b71c38cdf96 100644
> > --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > @@ -1834,6 +1834,41 @@ int smu_set_mp1_state(struct smu_context
> *smu,
> > return ret;
> > }
> >
> > +int smu_write_watermarks_table(struct smu_context *smu) {
> > + int ret = 0;
> > + struct smu_table_context *smu_table = &smu->smu_table;
> > + struct smu_table *table = NULL;
> > +
> > + table = &smu_table->tables[SMU_TABLE_WATERMARKS];
> > +
> > + if (!table->cpu_addr)
> > + ret
RE: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc
Please split the get_dpm_clock_table relates into a separate patch.
Other than that, the patch is reviewed-by: Evan Quan
Regards,
Evan
-Original Message-
From: amd-gfx On Behalf Of Hersen Wu
Sent: Thursday, October 10, 2019 10:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wu, Hersen ; Wang, Kevin(Yang) ;
Wentland, Harry
Subject: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc
there are two paths for renoir dc access smu.
one dc access smu directly using bios smc
interface: set disply, dprefclk, etc.
another goes through pplib for get dpm clock
table and set watermmark.
Signed-off-by: Hersen Wu
---
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 16 +---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 35 +++
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 16 ++--
drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 96 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 39
5 files changed, 141 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index f4cfa0caeba8..95564b8de3ce 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -589,10 +589,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
&wm_with_clock_ranges);
- else if (adev->smu.funcs &&
-adev->smu.funcs->set_watermarks_for_clock_ranges)
+ else
smu_set_watermarks_for_clock_ranges(&adev->smu,
- &wm_with_clock_ranges);
+ &wm_with_clock_ranges);
}
void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
@@ -665,7 +664,6 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
{
const struct dc_context *ctx = pp->dm;
struct amdgpu_device *adev = ctx->driver_context;
- struct smu_context *smu = &adev->smu;
struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
wm_with_clock_ranges.wm_dmif_clocks_ranges;
@@ -708,15 +706,7 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
}
- if (!smu->funcs)
- return PP_SMU_RESULT_UNSUPPORTED;
-
- /* 0: successful or smu.funcs->set_watermarks_for_clock_ranges = NULL;
-* 1: fail
-*/
- if (smu_set_watermarks_for_clock_ranges(&adev->smu,
- &wm_with_clock_ranges))
- return PP_SMU_RESULT_UNSUPPORTED;
+ smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);
return PP_SMU_RESULT_OK;
}
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c9266ea70331..1b71c38cdf96 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1834,6 +1834,41 @@ int smu_set_mp1_state(struct smu_context *smu,
return ret;
}
+int smu_write_watermarks_table(struct smu_context *smu)
+{
+ int ret = 0;
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *table = NULL;
+
+ table = &smu_table->tables[SMU_TABLE_WATERMARKS];
+
+ if (!table->cpu_addr)
+ return -EINVAL;
+
+ ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
+ true);
+
+ return ret;
+}
+
+int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
+{
+ int ret = 0;
+ struct smu_table *watermarks =
&smu->smu_table.tables[SMU_TABLE_WATERMARKS];
+ void *table = watermarks->cpu_addr;
+
+ if (!smu->disable_watermark &&
+ smu_feature_is_enabled(smu,
SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+ smu_feature_is_enabled(smu,
SMU_FEATURE_DPM_SOCCLK_BIT)) {
+ smu_set_watermarks_table(smu, table, clock_ranges);
+ smu->watermarks_bitmap |= WATERMARKS_EXIST;
+ smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
+ }
+
+ return ret;
+}
+
const struct amd_ip_funcs smu_ip_funcs = {
.name = "smu",
.early_init = smu_early_init,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ccf711c327c8..1469146da1aa 100644
--- a/drivers/gpu/drm/amd/powerplay
RE: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc
> -Original Message-
> From: amd-gfx On Behalf Of
> Hersen Wu
> Sent: Thursday, October 10, 2019 10:58 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wu, Hersen ; Wang, Kevin(Yang)
> ; Wentland, Harry
> Subject: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc
>
> there are two paths for renoir dc access smu.
> one dc access smu directly using bios smc
> interface: set disply, dprefclk, etc.
> another goes through pplib for get dpm clock table and set watermmark.
>
> Signed-off-by: Hersen Wu
> ---
> .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 16 +---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 35 +++
> .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 16 ++--
> drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 96
> +++
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 39
> 5 files changed, 141 insertions(+), 61 deletions(-)
>
> diff --git
> a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index f4cfa0caeba8..95564b8de3ce 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -589,10 +589,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
> if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
> pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
>
> &wm_with_clock_ranges);
> - else if (adev->smu.funcs &&
> - adev->smu.funcs->set_watermarks_for_clock_ranges)
> + else
> smu_set_watermarks_for_clock_ranges(&adev->smu,
> - &wm_with_clock_ranges);
> + &wm_with_clock_ranges);
> }
>
> void pp_rv_set_pme_wa_enable(struct pp_smu *pp) @@ -665,7 +664,6
> @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp, {
> const struct dc_context *ctx = pp->dm;
> struct amdgpu_device *adev = ctx->driver_context;
> - struct smu_context *smu = &adev->smu;
> struct dm_pp_wm_sets_with_clock_ranges_soc15
> wm_with_clock_ranges;
> struct dm_pp_clock_range_for_dmif_wm_set_soc15
> *wm_dce_clocks =
> wm_with_clock_ranges.wm_dmif_clocks_ranges;
> @@ -708,15 +706,7 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct
> pp_smu *pp,
> ranges->writer_wm_sets[i].min_drain_clk_mhz *
> 1000;
> }
>
> - if (!smu->funcs)
> - return PP_SMU_RESULT_UNSUPPORTED;
> -
> - /* 0: successful or smu.funcs->set_watermarks_for_clock_ranges =
> NULL;
> - * 1: fail
> - */
> - if (smu_set_watermarks_for_clock_ranges(&adev->smu,
> - &wm_with_clock_ranges))
> - return PP_SMU_RESULT_UNSUPPORTED;
> + smu_set_watermarks_for_clock_ranges(&adev->smu,
> &wm_with_clock_ranges);
>
> return PP_SMU_RESULT_OK;
> }
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index c9266ea70331..1b71c38cdf96 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1834,6 +1834,41 @@ int smu_set_mp1_state(struct smu_context *smu,
> return ret;
> }
>
> +int smu_write_watermarks_table(struct smu_context *smu) {
> + int ret = 0;
> + struct smu_table_context *smu_table = &smu->smu_table;
> + struct smu_table *table = NULL;
> +
> + table = &smu_table->tables[SMU_TABLE_WATERMARKS];
> +
> + if (!table->cpu_addr)
> + return -EINVAL;
> +
> + ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table-
> >cpu_addr,
> + true);
> +
> + return ret;
> +}
> +
> +int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
> + struct dm_pp_wm_sets_with_clock_ranges_soc15
> *clock_ranges) {
> + int ret = 0;
> + struct smu_table *watermarks = &smu-
> >smu_table.tables[SMU_TABLE_WATERMARKS];
> + void *table = watermarks->cpu_addr;
> +
> + if (!smu->disable_watermark &&
> + smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_DCEFCLK_BIT) &&
> + smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_SOCCLK_BIT)) {
> + smu_set_watermarks_table(smu, table, clock_ranges);
> + smu->watermarks_bitmap |= WATERMARKS_EXIST;
> + smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
> + }
> +
> + return ret;
> +}
Re: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc
it looks fine for me.
Reviewed-by: Kevin Wang
Best Regards,
Kevin
From: Hersen Wu
Sent: Thursday, October 10, 2019 10:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry ; Wang, Kevin(Yang)
; Wu, Hersen
Subject: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc
there are two paths for renoir dc access smu.
one dc access smu directly using bios smc
interface: set disply, dprefclk, etc.
another goes through pplib for get dpm clock
table and set watermmark.
Signed-off-by: Hersen Wu
---
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 16 +---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 35 +++
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 16 ++--
drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 96 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 39
5 files changed, 141 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index f4cfa0caeba8..95564b8de3ce 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -589,10 +589,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
&wm_with_clock_ranges);
- else if (adev->smu.funcs &&
-adev->smu.funcs->set_watermarks_for_clock_ranges)
+ else
smu_set_watermarks_for_clock_ranges(&adev->smu,
- &wm_with_clock_ranges);
+ &wm_with_clock_ranges);
}
void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
@@ -665,7 +664,6 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
{
const struct dc_context *ctx = pp->dm;
struct amdgpu_device *adev = ctx->driver_context;
- struct smu_context *smu = &adev->smu;
struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
wm_with_clock_ranges.wm_dmif_clocks_ranges;
@@ -708,15 +706,7 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
}
- if (!smu->funcs)
- return PP_SMU_RESULT_UNSUPPORTED;
-
- /* 0: successful or smu.funcs->set_watermarks_for_clock_ranges = NULL;
-* 1: fail
-*/
- if (smu_set_watermarks_for_clock_ranges(&adev->smu,
- &wm_with_clock_ranges))
- return PP_SMU_RESULT_UNSUPPORTED;
+ smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);
return PP_SMU_RESULT_OK;
}
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c9266ea70331..1b71c38cdf96 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1834,6 +1834,41 @@ int smu_set_mp1_state(struct smu_context *smu,
return ret;
}
+int smu_write_watermarks_table(struct smu_context *smu)
+{
+ int ret = 0;
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *table = NULL;
+
+ table = &smu_table->tables[SMU_TABLE_WATERMARKS];
+
+ if (!table->cpu_addr)
+ return -EINVAL;
+
+ ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
+ true);
+
+ return ret;
+}
+
+int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
+{
+ int ret = 0;
+ struct smu_table *watermarks =
&smu->smu_table.tables[SMU_TABLE_WATERMARKS];
+ void *table = watermarks->cpu_addr;
+
+ if (!smu->disable_watermark &&
+ smu_feature_is_enabled(smu,
SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+ smu_feature_is_enabled(smu,
SMU_FEATURE_DPM_SOCCLK_BIT)) {
+ smu_set_watermarks_table(smu, table, clock_ranges);
+ smu->watermarks_bitmap |= WATERMARKS_EXIST;
+ smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
+ }
+
+ return ret;
+}
+
const struct amd_ip_funcs smu_ip_funcs = {
.name = "smu",
.early_init = smu_early_init,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ccf711c327c8..1469146da1aa 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/
[PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc
there are two paths for renoir dc access smu.
one dc access smu directly using bios smc
interface: set disply, dprefclk, etc.
another goes through pplib for get dpm clock
table and set watermmark.
Signed-off-by: Hersen Wu
---
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 16 +---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 35 +++
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 16 ++--
drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 96 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 39
5 files changed, 141 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index f4cfa0caeba8..95564b8de3ce 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -589,10 +589,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
&wm_with_clock_ranges);
- else if (adev->smu.funcs &&
-adev->smu.funcs->set_watermarks_for_clock_ranges)
+ else
smu_set_watermarks_for_clock_ranges(&adev->smu,
- &wm_with_clock_ranges);
+ &wm_with_clock_ranges);
}
void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
@@ -665,7 +664,6 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
{
const struct dc_context *ctx = pp->dm;
struct amdgpu_device *adev = ctx->driver_context;
- struct smu_context *smu = &adev->smu;
struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
wm_with_clock_ranges.wm_dmif_clocks_ranges;
@@ -708,15 +706,7 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
}
- if (!smu->funcs)
- return PP_SMU_RESULT_UNSUPPORTED;
-
- /* 0: successful or smu.funcs->set_watermarks_for_clock_ranges = NULL;
-* 1: fail
-*/
- if (smu_set_watermarks_for_clock_ranges(&adev->smu,
- &wm_with_clock_ranges))
- return PP_SMU_RESULT_UNSUPPORTED;
+ smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);
return PP_SMU_RESULT_OK;
}
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c9266ea70331..1b71c38cdf96 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1834,6 +1834,41 @@ int smu_set_mp1_state(struct smu_context *smu,
return ret;
}
+int smu_write_watermarks_table(struct smu_context *smu)
+{
+ int ret = 0;
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *table = NULL;
+
+ table = &smu_table->tables[SMU_TABLE_WATERMARKS];
+
+ if (!table->cpu_addr)
+ return -EINVAL;
+
+ ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
+ true);
+
+ return ret;
+}
+
+int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
+{
+ int ret = 0;
+ struct smu_table *watermarks =
&smu->smu_table.tables[SMU_TABLE_WATERMARKS];
+ void *table = watermarks->cpu_addr;
+
+ if (!smu->disable_watermark &&
+ smu_feature_is_enabled(smu,
SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+ smu_feature_is_enabled(smu,
SMU_FEATURE_DPM_SOCCLK_BIT)) {
+ smu_set_watermarks_table(smu, table, clock_ranges);
+ smu->watermarks_bitmap |= WATERMARKS_EXIST;
+ smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
+ }
+
+ return ret;
+}
+
const struct amd_ip_funcs smu_ip_funcs = {
.name = "smu",
.early_init = smu_early_init,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ccf711c327c8..1469146da1aa 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -468,6 +468,7 @@ struct pptable_funcs {
int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool
asic_default);
int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type
clk_type,
uint32_t dpm_level, uint32_t *freq);
+ int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks
*clock_table);
};
struct smu_funcs
@@ -493,7 +494,6 @@ struct smu_funcs
int (*set_min_dcef_deep_sleep)(struct sm
