subject:"\[PATCH\] drm\/amdgpu\: Modify register access in sdma_v5_2 to use

[PATCH] drm/amdgpu: Modify register access in sdma_v5_2 to use _SOC15 macros

2021-06-04 Thread Rohit Khaire

In SRIOV environment, KMD should access SDMA registers
with RLCG if GC indirect access flag enabled.

Using _SOC15 read/write macros ensures that they go
through RLC when the flag is enabled.

Signed-off-by: Rohit Khaire 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 70 +-
 1 file changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 98059bce692f..62bc8bd7f9f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -495,12 +495,12 @@ static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
amdgpu_ttm_set_buffer_funcs_status(adev, false);
 
for (i = 0; i < adev->sdma.num_instances; i++) {
-   rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_CNTL));
+   rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_CNTL));
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 
0);
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), 
rb_cntl);
-   ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_IB_CNTL));
+   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_CNTL), rb_cntl);
+   ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_IB_CNTL));
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 
0);
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), 
ib_cntl);
+   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_IB_CNTL), ib_cntl);
}
 }
 
@@ -558,11 +558,11 @@ static void sdma_v5_2_ctx_switch_enable(struct 
amdgpu_device *adev, bool enable)
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
AUTO_CTXSW_ENABLE, enable ? 1 : 0);
if (enable && amdgpu_sdma_phase_quantum) {
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_PHASE0_QUANTUM),
+   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_PHASE0_QUANTUM),
   phase_quantum);
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_PHASE1_QUANTUM),
+   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_PHASE1_QUANTUM),
   phase_quantum);
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_PHASE2_QUANTUM),
+   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_PHASE2_QUANTUM),
   phase_quantum);
}
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), 
f32_cntl);
@@ -620,62 +620,62 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device 
*adev)
ring = >sdma.instance[i].ring;
wb_offset = (ring->rptr_offs * 4);
 
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
+   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 
/* Set ring buffer size in dwords */
rb_bufsz = order_base_2(ring->ring_size / 4);
-   rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_CNTL));
+   rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_CNTL));
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, 
rb_bufsz);
 #ifdef __BIG_ENDIAN
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 
RB_SWAP_ENABLE, 1);
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
RPTR_WRITEBACK_SWAP_ENABLE, 1);
 #endif
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), 
rb_cntl);
+   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_CNTL), rb_cntl);
 
/* Initialize the ring buffer's read and write pointers */
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 
0);
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_RPTR_HI), 0);
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 
0);
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_WPTR_HI), 0);
+   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_RPTR), 0);
+   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_RPTR_HI), 0);
+   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_WPTR), 0);
+   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_WPTR_HI), 0);
 
/* setup the wptr shadow polling */
wptr_gpu_addr

Re: [PATCH] drm/amdgpu: Modify register access in sdma_v5_2 to use _SOC15 macros

2021-06-04 Thread Alex Deucher

On Fri, Jun 4, 2021 at 3:08 PM Rohit Khaire  wrote:
>
> In SRIOV environment, KMD should access SDMA registers
> with RLCG if GC indirect access flag enabled.
>
> Using _SOC15 read/write macros ensures that they go
> through RLC when the flag is enabled.
>
> Signed-off-by: Rohit Khaire 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 70 +-
>  1 file changed, 35 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index 98059bce692f..62bc8bd7f9f2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -495,12 +495,12 @@ static void sdma_v5_2_gfx_stop(struct amdgpu_device 
> *adev)
> amdgpu_ttm_set_buffer_funcs_status(adev, false);
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> -   rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_RB_CNTL));
> +   rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, 
> i, mmSDMA0_GFX_RB_CNTL));
> rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 
> RB_ENABLE, 0);
> -   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_RB_CNTL), rb_cntl);
> -   ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_IB_CNTL));
> +   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_RB_CNTL), rb_cntl);
> +   ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, 
> i, mmSDMA0_GFX_IB_CNTL));
> ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, 
> IB_ENABLE, 0);
> -   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_IB_CNTL), ib_cntl);
> +   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_IB_CNTL), ib_cntl);
> }
>  }
>
> @@ -558,11 +558,11 @@ static void sdma_v5_2_ctx_switch_enable(struct 
> amdgpu_device *adev, bool enable)
> f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
> AUTO_CTXSW_ENABLE, enable ? 1 : 0);
> if (enable && amdgpu_sdma_phase_quantum) {
> -   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_PHASE0_QUANTUM),
> +   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_PHASE0_QUANTUM),
>phase_quantum);
> -   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_PHASE1_QUANTUM),
> +   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_PHASE1_QUANTUM),
>phase_quantum);
> -   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_PHASE2_QUANTUM),
> +   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_PHASE2_QUANTUM),
>phase_quantum);
> }
> WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), 
> f32_cntl);
> @@ -620,62 +620,62 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device 
> *adev)
> ring = >sdma.instance[i].ring;
> wb_offset = (ring->rptr_offs * 4);
>
> -   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
> +   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
>
> /* Set ring buffer size in dwords */
> rb_bufsz = order_base_2(ring->ring_size / 4);
> -   rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_RB_CNTL));
> +   rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, 
> i, mmSDMA0_GFX_RB_CNTL));
> rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, 
> rb_bufsz);
>  #ifdef __BIG_ENDIAN
> rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 
> RB_SWAP_ENABLE, 1);
> rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
> RPTR_WRITEBACK_SWAP_ENABLE, 1);
>  #endif
> -   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_RB_CNTL), rb_cntl);
> +   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_RB_CNTL), rb_cntl);
>
> /* Initialize the ring buffer's read and write pointers */
> -   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_RB_RPTR), 0);
> -   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_RB_RPTR_HI), 0);
> -   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_RB_WPTR), 0);
> -   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_RB_WPTR_HI), 0);
> +   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
> mmSDMA0_GFX_RB_RPTR), 0);
> +   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
>

[PATCH] drm/amdgpu: Modify register access in sdma_v5_2 to use _SOC15 macros

Re: [PATCH] drm/amdgpu: Modify register access in sdma_v5_2 to use _SOC15 macros

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