Re: [PATCH] drm/amdgpu: Skip specific mmhub and sdma registers accessing under sriov

2023-01-12 Thread Alex Deucher 
On Wed, Jan 11, 2023 at 2:53 AM Yifan Zha  wrote:
>
> [Why]
> SDMA0_CNTL and MMHUB system aperture related registers are blocked by L1 
> Policy.
> Therefore, they cannot be accessed by VF and loged in violation.
>
> [How]
> For MMHUB registers, they will be programmed by PF. So VF will skip to 
> program them in mmhubv3_0.
> For SDMA0_CNTL which is a PF_only register, VF don't need to program it in 
> sdma_v6_0.
>
> Signed-off-by: Yifan Zha 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c | 34 -
>  drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c  | 10 +---
>  2 files changed, 23 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c 
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
> index e9dcd6fcde7f..ae9cd1a4cfee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
> @@ -169,23 +169,23 @@ static void mmhub_v3_0_init_system_aperture_regs(struct 
> amdgpu_device *adev)
> uint64_t value;
> uint32_t tmp;
>
> -   if (!amdgpu_sriov_vf(adev)) {
> -   /*
> -* the new L1 policy will block SRIOV guest from writing
> -* these regs, and they will be programed at host.
> -* so skip programing these regs.
> -*/
> -   /* Disable AGP. */
> -   WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
> -   WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0);
> -   WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FF);
> -
> -   /* Program the system aperture low logical page number. */
> -   WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
> -adev->gmc.vram_start >> 18);
> -   WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
> -adev->gmc.vram_end >> 18);
> -   }
> +   if (amdgpu_sriov_vf(adev))
> +   return;
> +
> +   /*
> +* the new L1 policy will block SRIOV guest from writing
> +* these regs, and they will be programed at host.
> +* so skip programing these regs.
> +*/
> +   /* Disable AGP. */
> +   WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
> +   WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0);
> +   WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FF);
> +   /* Program the system aperture low logical page number. */
> +   WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
> +adev->gmc.vram_start >> 18);
> +   WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
> +adev->gmc.vram_end >> 18);
>
> /* Set default page address. */
> value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> index bf1fa5e8d2f9..6fe292a2486b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> @@ -1403,10 +1403,12 @@ static int sdma_v6_0_set_trap_irq_state(struct 
> amdgpu_device *adev,
>
> u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);
>
> -   sdma_cntl = RREG32(reg_offset);
> -   sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
> -  state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
> -   WREG32(reg_offset, sdma_cntl);
> +   if (!amdgpu_sriov_vf(adev)) {
> +   sdma_cntl = RREG32(reg_offset);
> +   sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
> +   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
> +   WREG32(reg_offset, sdma_cntl);
> +   }
>
> return 0;
>  }
> --
> 2.25.1
>

[PATCH] drm/amdgpu: Skip specific mmhub and sdma registers accessing under sriov

2023-01-10 Thread Yifan Zha 
[Why]
SDMA0_CNTL and MMHUB system aperture related registers are blocked by L1 Policy.
Therefore, they cannot be accessed by VF and loged in violation.

[How]
For MMHUB registers, they will be programmed by PF. So VF will skip to program 
them in mmhubv3_0.
For SDMA0_CNTL which is a PF_only register, VF don't need to program it in 
sdma_v6_0.

Signed-off-by: Yifan Zha 
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c | 34 -
 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c  | 10 +---
 2 files changed, 23 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
index e9dcd6fcde7f..ae9cd1a4cfee 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
@@ -169,23 +169,23 @@ static void mmhub_v3_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
uint64_t value;
uint32_t tmp;
 
-   if (!amdgpu_sriov_vf(adev)) {
-   /*
-* the new L1 policy will block SRIOV guest from writing
-* these regs, and they will be programed at host.
-* so skip programing these regs.
-*/
-   /* Disable AGP. */
-   WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
-   WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0);
-   WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FF);
-
-   /* Program the system aperture low logical page number. */
-   WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
-   WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
-   }
+   if (amdgpu_sriov_vf(adev))
+   return;
+
+   /*
+* the new L1 policy will block SRIOV guest from writing
+* these regs, and they will be programed at host.
+* so skip programing these regs.
+*/
+   /* Disable AGP. */
+   WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
+   WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0);
+   WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FF);
+   /* Program the system aperture low logical page number. */
+   WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
+adev->gmc.vram_start >> 18);
+   WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+adev->gmc.vram_end >> 18);
 
/* Set default page address. */
value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index bf1fa5e8d2f9..6fe292a2486b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -1403,10 +1403,12 @@ static int sdma_v6_0_set_trap_irq_state(struct 
amdgpu_device *adev,
 
u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);
 
-   sdma_cntl = RREG32(reg_offset);
-   sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
-  state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
-   WREG32(reg_offset, sdma_cntl);
+   if (!amdgpu_sriov_vf(adev)) {
+   sdma_cntl = RREG32(reg_offset);
+   sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
+   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+   WREG32(reg_offset, sdma_cntl);
+   }
 
return 0;
 }
-- 
2.25.1