RE: [PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for SRIOV
[AMD Public Use]
You shall by pass get_rev_id function call, instead of adding the check in the
callback function.
For each hw generation, there could be several callback function implementation
depending on whether the mmRCC_DEV0_EPF0_STRAP0 can be re-used.
It's error prone if we just take the change in specific callback. There is no
guarantee people remember to add this check next time when working on the
implementation.
Regards,
Hawking
-Original Message-
From: Khaire, Rohit
Sent: Tuesday, September 22, 2020 04:55
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben ; Koenig, Christian
; Deucher, Alexander ;
Xiao, Jack ; Zhang, Hawking ; Xu,
Feifei ; Wang, Kevin(Yang) ; Yuan,
Xiaojie ; Li, Rong (Zero) ; Min, Frank
; Khaire, Rohit
Subject: [PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for
SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 7429f30398b9..4f611cd68940 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -51,8 +51,19 @@ static void nbio_v2_3_remap_hdp_registers(struct
amdgpu_device *adev)
static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev) {
- u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+ u32 tmp;
+
+ if (amdgpu_sriov_vf(adev)) {
+ /* workaround on rev_id for sriov
+* guest vm gets 0x when reading RCC_DEV0_EPF0_STRAP0,
+* as a consequence, the rev_id and external_rev_id are wrong.
+*
+* workaround it by using PCI revision id.
+*/
+ return adev->pdev->revision;
+ }
+ tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
--
2.17.1
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[PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 7429f30398b9..4f611cd68940 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -51,8 +51,19 @@ static void nbio_v2_3_remap_hdp_registers(struct
amdgpu_device *adev)
static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
{
- u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+ u32 tmp;
+
+ if (amdgpu_sriov_vf(adev)) {
+ /* workaround on rev_id for sriov
+* guest vm gets 0x when reading RCC_DEV0_EPF0_STRAP0,
+* as a consequence, the rev_id and external_rev_id are wrong.
+*
+* workaround it by using PCI revision id.
+*/
+ return adev->pdev->revision;
+ }
+ tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
--
2.17.1
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[PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 7429f30398b9..78cb48bafa4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -51,8 +51,20 @@ static void nbio_v2_3_remap_hdp_registers(struct
amdgpu_device *adev)
static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
{
- u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+ u32 tmp;
+
+ if (amdgpu_sriov_vf(adev)) {
+ /* workaround on rev_id for sriov
+* guest vm gets 0x when reading RCC_DEV0_EPF0_STRAP0,
+* as a consequence, the rev_id and external_rev_id are wrong.
+*
+* workaround it by hardcoding the rev_id to 0,
+*(which is the default value)
+*/
+ return adev->pdev->revision;
+ }
+ tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
--
2.17.1
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RE: [PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for SRIOV
[AMD Public Use]
Hi Alex,
I discussed this with my team, we are fine with PCI_REVISION_ID for SRIOV.
I am resending my patch with the change you suggested.
Thanks
Rohit
-Original Message-
From: Alex Deucher
Sent: September 14, 2020 1:16 AM
To: Khaire, Rohit
Cc: amd-gfx list
Subject: Re: [PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue
for SRIOV
On Fri, Sep 11, 2020 at 6:03 PM Rohit Khaire wrote:
>
> Signed-off-by: Rohit Khaire
> ---
> drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 14 +-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> index 7429f30398b9..fdfa075e6d5a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> @@ -51,8 +51,20 @@ static void nbio_v2_3_remap_hdp_registers(struct
> amdgpu_device *adev)
>
> static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev) {
> - u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
> + u32 tmp;
>
> + /*
> +* On SRIOV VF RCC_DEV0_EPF0_STRAP is blocked.
> +* So we read rev_id from PCI config space.
> +*/
> + if (amdgpu_sriov_vf(adev)) {
> + pci_read_config_dword(adev->pdev, PCI_REVISION_ID, );
This is not going to do what you want. The pci revision id is not the
same as the ati rev id. If you actually want the pci revision id, we
already have it in adev->pdev->revision, no need to fetch it directly.
Alex
> + /* Revision ID is the least significant 8 bits */
> + tmp &= 0xFF;
> + return tmp;
> + }
> +
> + tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
> tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
> tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
>
> --
> 2.17.1
>
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Re: [PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for SRIOV
On Fri, Sep 11, 2020 at 6:03 PM Rohit Khaire wrote:
>
> Signed-off-by: Rohit Khaire
> ---
> drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 14 +-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> index 7429f30398b9..fdfa075e6d5a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> @@ -51,8 +51,20 @@ static void nbio_v2_3_remap_hdp_registers(struct
> amdgpu_device *adev)
>
> static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
> {
> - u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
> + u32 tmp;
>
> + /*
> +* On SRIOV VF RCC_DEV0_EPF0_STRAP is blocked.
> +* So we read rev_id from PCI config space.
> +*/
> + if (amdgpu_sriov_vf(adev)) {
> + pci_read_config_dword(adev->pdev, PCI_REVISION_ID, );
This is not going to do what you want. The pci revision id is not the
same as the ati rev id. If you actually want the pci revision id, we
already have it in adev->pdev->revision, no need to fetch it directly.
Alex
> + /* Revision ID is the least significant 8 bits */
> + tmp &= 0xFF;
> + return tmp;
> + }
> +
> + tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
> tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
> tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
>
> --
> 2.17.1
>
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[PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 7429f30398b9..fdfa075e6d5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -51,8 +51,20 @@ static void nbio_v2_3_remap_hdp_registers(struct
amdgpu_device *adev)
static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
{
- u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+ u32 tmp;
+ /*
+* On SRIOV VF RCC_DEV0_EPF0_STRAP is blocked.
+* So we read rev_id from PCI config space.
+*/
+ if (amdgpu_sriov_vf(adev)) {
+ pci_read_config_dword(adev->pdev, PCI_REVISION_ID, );
+ /* Revision ID is the least significant 8 bits */
+ tmp &= 0xFF;
+ return tmp;
+ }
+
+ tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
--
2.17.1
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