Re: [PATCH] drm/amdgpu: add HDP flush dummy for UVD 6/7

2018-05-11 Thread Christian König 

Just did so.

Sorry for the delay yesterday was a holiday here and well you know how 
long it takes to catch up on mails :)


Christian.

Am 11.05.2018 um 16:09 schrieb Alex Deucher:

Are you going to push this or should I?

Alex

On Tue, May 8, 2018 at 11:46 AM, Deucher, Alexander
 wrote:

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Christian
König 
Sent: Tuesday, May 8, 2018 6:30:06 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: add HDP flush dummy for UVD 6/7

The UVD firmware doesn't seem to like the HDP flush here.

This worked for years without HDP flush, so just skip it.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 16 ++--
  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 -
  2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 6d3359889c0b..8041b26a7a21 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -963,6 +963,16 @@ static void uvd_v6_0_enc_ring_emit_fence(struct
amdgpu_ring *ring, u64 addr,
  amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
  }

+/**
+ * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing
+ *
+ * @ring: amdgpu_ring pointer
+ */
+static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+   /* The firmware doesn't seem to like touching registers at this
point. */
+}
+
  /**
   * uvd_v6_0_ring_test_ring - register write test
   *
@@ -1528,12 +1538,13 @@ static const struct amdgpu_ring_funcs
uvd_v6_0_ring_phys_funcs = {
  .set_wptr = uvd_v6_0_ring_set_wptr,
  .parse_cs = amdgpu_uvd_ring_parse_cs,
  .emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
  10 + /* uvd_v6_0_ring_emit_pipeline_sync */
  14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
  .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
  .emit_ib = uvd_v6_0_ring_emit_ib,
  .emit_fence = uvd_v6_0_ring_emit_fence,
+   .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
  .test_ring = uvd_v6_0_ring_test_ring,
  .test_ib = amdgpu_uvd_ring_test_ib,
  .insert_nop = amdgpu_ring_insert_nop,
@@ -1552,7 +1563,7 @@ static const struct amdgpu_ring_funcs
uvd_v6_0_ring_vm_funcs = {
  .get_wptr = uvd_v6_0_ring_get_wptr,
  .set_wptr = uvd_v6_0_ring_set_wptr,
  .emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
  10 + /* uvd_v6_0_ring_emit_pipeline_sync */
  VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /*
uvd_v6_0_ring_emit_vm_flush */
  14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
@@ -1561,6 +1572,7 @@ static const struct amdgpu_ring_funcs
uvd_v6_0_ring_vm_funcs = {
  .emit_fence = uvd_v6_0_ring_emit_fence,
  .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
  .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
+   .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
  .test_ring = uvd_v6_0_ring_test_ring,
  .test_ib = amdgpu_uvd_ring_test_ib,
  .insert_nop = amdgpu_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 2251db4048f5..b0de1e04093b 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1135,6 +1135,16 @@ static void uvd_v7_0_enc_ring_emit_fence(struct
amdgpu_ring *ring, u64 addr,
  amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
  }

+/**
+ * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
+ *
+ * @ring: amdgpu_ring pointer
+ */
+static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+   /* The firmware doesn't seem to like touching registers at this
point. */
+}
+
  /**
   * uvd_v7_0_ring_test_ring - register write test
   *
@@ -1654,7 +1664,7 @@ static const struct amdgpu_ring_funcs
uvd_v7_0_ring_vm_funcs = {
  .get_wptr = uvd_v7_0_ring_get_wptr,
  .set_wptr = uvd_v7_0_ring_set_wptr,
  .emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
  SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
  SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
  8 + /* uvd_v7_0_ring_emit_vm_flush */
@@ -1663,6 +1673,7 @@ static const struct amdgpu_ring_funcs
uvd_v7_0_ring_vm_funcs = {
  .emit_ib = uvd_v7_0_ring_emit_ib,
  .emit_fence = uvd_v7_0_ring_emit_fence,
  .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
+   .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
  .test_ring = uvd_v7_0_ring_test_ring,
  .test_ib = amdgpu_uvd_ring_test_ib,
  .insert_nop = uvd_v7_0_ring_insert_nop,
--
2.14.1

___

Re: [PATCH] drm/amdgpu: add HDP flush dummy for UVD 6/7

2018-05-11 Thread Alex Deucher 
Are you going to push this or should I?

Alex

On Tue, May 8, 2018 at 11:46 AM, Deucher, Alexander
 wrote:
> Acked-by: Alex Deucher 
>
> 
> From: amd-gfx  on behalf of Christian
> König 
> Sent: Tuesday, May 8, 2018 6:30:06 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: add HDP flush dummy for UVD 6/7
>
> The UVD firmware doesn't seem to like the HDP flush here.
>
> This worked for years without HDP flush, so just skip it.
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 16 ++--
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 -
>  2 files changed, 26 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 6d3359889c0b..8041b26a7a21 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -963,6 +963,16 @@ static void uvd_v6_0_enc_ring_emit_fence(struct
> amdgpu_ring *ring, u64 addr,
>  amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
>  }
>
> +/**
> + * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing
> + *
> + * @ring: amdgpu_ring pointer
> + */
> +static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> +{
> +   /* The firmware doesn't seem to like touching registers at this
> point. */
> +}
> +
>  /**
>   * uvd_v6_0_ring_test_ring - register write test
>   *
> @@ -1528,12 +1538,13 @@ static const struct amdgpu_ring_funcs
> uvd_v6_0_ring_phys_funcs = {
>  .set_wptr = uvd_v6_0_ring_set_wptr,
>  .parse_cs = amdgpu_uvd_ring_parse_cs,
>  .emit_frame_size =
> -   6 + 6 + /* hdp flush / invalidate */
> +   6 + /* hdp invalidate */
>  10 + /* uvd_v6_0_ring_emit_pipeline_sync */
>  14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
>  .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
>  .emit_ib = uvd_v6_0_ring_emit_ib,
>  .emit_fence = uvd_v6_0_ring_emit_fence,
> +   .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
>  .test_ring = uvd_v6_0_ring_test_ring,
>  .test_ib = amdgpu_uvd_ring_test_ib,
>  .insert_nop = amdgpu_ring_insert_nop,
> @@ -1552,7 +1563,7 @@ static const struct amdgpu_ring_funcs
> uvd_v6_0_ring_vm_funcs = {
>  .get_wptr = uvd_v6_0_ring_get_wptr,
>  .set_wptr = uvd_v6_0_ring_set_wptr,
>  .emit_frame_size =
> -   6 + 6 + /* hdp flush / invalidate */
> +   6 + /* hdp invalidate */
>  10 + /* uvd_v6_0_ring_emit_pipeline_sync */
>  VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /*
> uvd_v6_0_ring_emit_vm_flush */
>  14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
> @@ -1561,6 +1572,7 @@ static const struct amdgpu_ring_funcs
> uvd_v6_0_ring_vm_funcs = {
>  .emit_fence = uvd_v6_0_ring_emit_fence,
>  .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
>  .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
> +   .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
>  .test_ring = uvd_v6_0_ring_test_ring,
>  .test_ib = amdgpu_uvd_ring_test_ib,
>  .insert_nop = amdgpu_ring_insert_nop,
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 2251db4048f5..b0de1e04093b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1135,6 +1135,16 @@ static void uvd_v7_0_enc_ring_emit_fence(struct
> amdgpu_ring *ring, u64 addr,
>  amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
>  }
>
> +/**
> + * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
> + *
> + * @ring: amdgpu_ring pointer
> + */
> +static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> +{
> +   /* The firmware doesn't seem to like touching registers at this
> point. */
> +}
> +
>  /**
>   * uvd_v7_0_ring_test_ring - register write test
>   *
> @@ -1654,7 +1664,7 @@ static const struct amdgpu_ring_funcs
> uvd_v7_0_ring_vm_funcs = {
>  .get_wptr = uvd_v7_0_ring_get_wptr,
>  .set_wptr = uvd_v7_0_ring_set_wptr,
>  .emit_frame_size =
> -   6 + 6 + /* hdp flush / invalidate */
> +   6 + /* hdp invalidate */
>  SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
>  SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
>  8 + /* uvd_v7_0_ring_emit_vm_flush */
> @@ -1663,6 +1673,7 @@ static const struct amdgpu_ring_funcs
> uvd_v7_0_ring_vm_funcs = {
>  .emit_ib = uvd_v7_0_ring_emit_ib,
>  .emit_f

Re: [PATCH] drm/amdgpu: add HDP flush dummy for UVD 6/7

2018-05-08 Thread Deucher, Alexander 
Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Christian 
König 
Sent: Tuesday, May 8, 2018 6:30:06 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: add HDP flush dummy for UVD 6/7

The UVD firmware doesn't seem to like the HDP flush here.

This worked for years without HDP flush, so just skip it.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 16 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 -
 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 6d3359889c0b..8041b26a7a21 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -963,6 +963,16 @@ static void uvd_v6_0_enc_ring_emit_fence(struct 
amdgpu_ring *ring, u64 addr,
 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 }

+/**
+ * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing
+ *
+ * @ring: amdgpu_ring pointer
+ */
+static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+   /* The firmware doesn't seem to like touching registers at this point. 
*/
+}
+
 /**
  * uvd_v6_0_ring_test_ring - register write test
  *
@@ -1528,12 +1538,13 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_ring_phys_funcs = {
 .set_wptr = uvd_v6_0_ring_set_wptr,
 .parse_cs = amdgpu_uvd_ring_parse_cs,
 .emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
 .emit_ib = uvd_v6_0_ring_emit_ib,
 .emit_fence = uvd_v6_0_ring_emit_fence,
+   .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
 .test_ring = uvd_v6_0_ring_test_ring,
 .test_ib = amdgpu_uvd_ring_test_ib,
 .insert_nop = amdgpu_ring_insert_nop,
@@ -1552,7 +1563,7 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_ring_vm_funcs = {
 .get_wptr = uvd_v6_0_ring_get_wptr,
 .set_wptr = uvd_v6_0_ring_set_wptr,
 .emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
 VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* 
uvd_v6_0_ring_emit_vm_flush */
 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
@@ -1561,6 +1572,7 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_ring_vm_funcs = {
 .emit_fence = uvd_v6_0_ring_emit_fence,
 .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
 .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
+   .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
 .test_ring = uvd_v6_0_ring_test_ring,
 .test_ib = amdgpu_uvd_ring_test_ib,
 .insert_nop = amdgpu_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 2251db4048f5..b0de1e04093b 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1135,6 +1135,16 @@ static void uvd_v7_0_enc_ring_emit_fence(struct 
amdgpu_ring *ring, u64 addr,
 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 }

+/**
+ * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
+ *
+ * @ring: amdgpu_ring pointer
+ */
+static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+   /* The firmware doesn't seem to like touching registers at this point. 
*/
+}
+
 /**
  * uvd_v7_0_ring_test_ring - register write test
  *
@@ -1654,7 +1664,7 @@ static const struct amdgpu_ring_funcs 
uvd_v7_0_ring_vm_funcs = {
 .get_wptr = uvd_v7_0_ring_get_wptr,
 .set_wptr = uvd_v7_0_ring_set_wptr,
 .emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
 8 + /* uvd_v7_0_ring_emit_vm_flush */
@@ -1663,6 +1673,7 @@ static const struct amdgpu_ring_funcs 
uvd_v7_0_ring_vm_funcs = {
 .emit_ib = uvd_v7_0_ring_emit_ib,
 .emit_fence = uvd_v7_0_ring_emit_fence,
 .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
+   .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
 .test_ring = uvd_v7_0_ring_test_ring,
 .test_ib = amdgpu_uvd_ring_test_ib,
 .insert_nop = uvd_v7_0_ring_insert_nop,
--
2.14.1

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[PATCH] drm/amdgpu: add HDP flush dummy for UVD 6/7

2018-05-08 Thread Christian König 
The UVD firmware doesn't seem to like the HDP flush here.

This worked for years without HDP flush, so just skip it.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 16 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 -
 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 6d3359889c0b..8041b26a7a21 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -963,6 +963,16 @@ static void uvd_v6_0_enc_ring_emit_fence(struct 
amdgpu_ring *ring, u64 addr,
amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 }
 
+/**
+ * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing
+ *
+ * @ring: amdgpu_ring pointer
+ */
+static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+   /* The firmware doesn't seem to like touching registers at this point. 
*/
+}
+
 /**
  * uvd_v6_0_ring_test_ring - register write test
  *
@@ -1528,12 +1538,13 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_ring_phys_funcs = {
.set_wptr = uvd_v6_0_ring_set_wptr,
.parse_cs = amdgpu_uvd_ring_parse_cs,
.emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
10 + /* uvd_v6_0_ring_emit_pipeline_sync */
14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
.emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
.emit_ib = uvd_v6_0_ring_emit_ib,
.emit_fence = uvd_v6_0_ring_emit_fence,
+   .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
.test_ring = uvd_v6_0_ring_test_ring,
.test_ib = amdgpu_uvd_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
@@ -1552,7 +1563,7 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_ring_vm_funcs = {
.get_wptr = uvd_v6_0_ring_get_wptr,
.set_wptr = uvd_v6_0_ring_set_wptr,
.emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
10 + /* uvd_v6_0_ring_emit_pipeline_sync */
VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* 
uvd_v6_0_ring_emit_vm_flush */
14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
@@ -1561,6 +1572,7 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_ring_vm_funcs = {
.emit_fence = uvd_v6_0_ring_emit_fence,
.emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
.emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
+   .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
.test_ring = uvd_v6_0_ring_test_ring,
.test_ib = amdgpu_uvd_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 2251db4048f5..b0de1e04093b 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1135,6 +1135,16 @@ static void uvd_v7_0_enc_ring_emit_fence(struct 
amdgpu_ring *ring, u64 addr,
amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 }
 
+/**
+ * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
+ *
+ * @ring: amdgpu_ring pointer
+ */
+static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+   /* The firmware doesn't seem to like touching registers at this point. 
*/
+}
+
 /**
  * uvd_v7_0_ring_test_ring - register write test
  *
@@ -1654,7 +1664,7 @@ static const struct amdgpu_ring_funcs 
uvd_v7_0_ring_vm_funcs = {
.get_wptr = uvd_v7_0_ring_get_wptr,
.set_wptr = uvd_v7_0_ring_set_wptr,
.emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
8 + /* uvd_v7_0_ring_emit_vm_flush */
@@ -1663,6 +1673,7 @@ static const struct amdgpu_ring_funcs 
uvd_v7_0_ring_vm_funcs = {
.emit_ib = uvd_v7_0_ring_emit_ib,
.emit_fence = uvd_v7_0_ring_emit_fence,
.emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
+   .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
.test_ring = uvd_v7_0_ring_test_ring,
.test_ib = amdgpu_uvd_ring_test_ib,
.insert_nop = uvd_v7_0_ring_insert_nop,
-- 
2.14.1

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