Re: [PATCH] drm/amdgpu: add SPM golden settings for Navi10(v2)

2020-04-06 Thread Yin, Tianci (Rico) 
[AMD Official Use Only - Internal Distribution Only]

Thanks very much Alex!

From: Alex Deucher 
Sent: Monday, April 6, 2020 22:29
To: Yin, Tianci (Rico) 
Cc: amd-gfx list ; Deucher, Alexander 
; Xu, Feifei ; Zhang, Hawking 
; Hesik, Christopher 
Subject: Re: [PATCH] drm/amdgpu: add SPM golden settings for Navi10(v2)

On Mon, Apr 6, 2020 at 10:26 AM Tianci Yin  wrote:
>
> From: "Tianci.Yin" 
>
> Add RLC_SPM golden settings
>
> Change-Id: I616e127171293d915cb3a05dee02f51cec8d8f6f
> Signed-off-by: Tianci.Yin 

Reviewed-by: Alex Deucher 
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Re: [PATCH] drm/amdgpu: add SPM golden settings for Navi10(v2)

2020-04-06 Thread Alex Deucher 
On Mon, Apr 6, 2020 at 10:26 AM Tianci Yin  wrote:
>
> From: "Tianci.Yin" 
>
> Add RLC_SPM golden settings
>
> Change-Id: I616e127171293d915cb3a05dee02f51cec8d8f6f
> Signed-off-by: Tianci.Yin 

Reviewed-by: Alex Deucher 
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[PATCH] drm/amdgpu: add SPM golden settings for Navi10(v2)

2020-04-06 Thread Tianci Yin 
From: "Tianci.Yin" 

Add RLC_SPM golden settings

Change-Id: I616e127171293d915cb3a05dee02f51cec8d8f6f
Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1059 
 1 file changed, 1059 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 70edbbf84338..19d9bdba0453 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -138,6 +138,1062 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_0_nv10[] =
/* Pending on emulation bring up */
 };
 
+static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
+{
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe000, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 
0x, 0x28),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 
0x, 0x9),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 
0x, 0x8),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 
0x, 0x1b),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x1),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 
0x, 0x8),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x1),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 
0x, 0x1b),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 
0x, 0x20),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 
0x, 0xe),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 
0x, 0xc8),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 
0x, 0xf),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 
0x, 0xcc),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 
0x, 0xf),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 
0x, 0xd0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 
0x, 0xf),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 
0x, 0xd4),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 
0x, 0xf),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 
0x, 0x24),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 
0x, 0xf),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 
0x, 0x24),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 
0x, 0xf),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 
0x, 0x4),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 
0x, 0x11),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 
0x, 0x8),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 
0x, 0xf),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 
0x, 0x0),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0),
+

Re: [PATCH] drm/amdgpu: add SPM golden settings for Navi10

2020-04-03 Thread Alex Deucher 
On Fri, Apr 3, 2020 at 1:30 AM Tianci Yin  wrote:
>
> From: "Tianci.Yin" 
>
> Add RLC_SPM golden settings
>
> Change-Id: I616e127171293d915cb3a05dee02f51cec8d8f6f
> Signed-off-by: Tianci.Yin 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c|9 +
>  .../gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h | 1058 +
>  2 files changed, 1067 insertions(+)
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 70edbbf84338..7c96a894ad37 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -48,6 +48,7 @@
>  #include "v10_structs.h"
>  #include "gfx_v10_0.h"
>  #include "nbio_v2_3.h"
> +#include "golden_gc_spm_10_1_0.h"

Can we just include the table directly in this file instead of a
separate header?  One more comment below.

>
>  /**
>   * Navi10 has two graphic rings to share each graphic pipe.
> @@ -138,6 +139,11 @@ static const struct soc15_reg_golden 
> golden_settings_gc_10_0_nv10[] =
> /* Pending on emulation bring up */
>  };
>
> +static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
> +{
> +   GOLDEN_GC_SPM_10_1_0
> +};
> +
>  static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
>  {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x, 
> 0x003c0014),
> @@ -388,6 +394,9 @@ static void gfx_v10_0_init_golden_registers(struct 
> amdgpu_device *adev)
> soc15_program_register_sequence(adev,
> golden_settings_gc_10_0_nv10,
> (const 
> u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
> +   soc15_program_register_sequence(adev,
> +   
> golden_settings_gc_rlc_spm_10_0_nv10,
> +   (const 
> u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
> break;
> case CHIP_NAVI14:
> soc15_program_register_sequence(adev,
> diff --git a/drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h 
> b/drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h
> new file mode 100644
> index ..e65af4a6fcdd
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h

This file is missing a license.

Alex
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RE: [PATCH] drm/amdgpu: add SPM golden settings for Navi10

2020-04-03 Thread Xu, Feifei 
[AMD Official Use Only - Internal Distribution Only]



Reviewed-by: Feifei Xu 

-Original Message-
From: Tianci Yin  
Sent: 2020年4月3日 13:30
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Hesik, Christopher 
; Zhang, Hawking ; Xu, Feifei 
; Yin, Tianci (Rico) 
Subject: [PATCH] drm/amdgpu: add SPM golden settings for Navi10

From: "Tianci.Yin" 

Add RLC_SPM golden settings

Change-Id: I616e127171293d915cb3a05dee02f51cec8d8f6f
Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c|9 +
 .../gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h | 1058 +
 2 files changed, 1067 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 70edbbf84338..7c96a894ad37 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -48,6 +48,7 @@
 #include "v10_structs.h"
 #include "gfx_v10_0.h"
 #include "nbio_v2_3.h"
+#include "golden_gc_spm_10_1_0.h"
 
 /**
  * Navi10 has two graphic rings to share each graphic pipe.
@@ -138,6 +139,11 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_0_nv10[] =
/* Pending on emulation bring up */
 };
 
+static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
+{
+   GOLDEN_GC_SPM_10_1_0
+};
+
 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
 {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x, 
0x003c0014),
@@ -388,6 +394,9 @@ static void gfx_v10_0_init_golden_registers(struct 
amdgpu_device *adev)
soc15_program_register_sequence(adev,
golden_settings_gc_10_0_nv10,
(const 
u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
+   soc15_program_register_sequence(adev,
+   
golden_settings_gc_rlc_spm_10_0_nv10,
+   (const 
u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
break;
case CHIP_NAVI14:
soc15_program_register_sequence(adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h 
b/drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h
new file mode 100644
index ..e65af4a6fcdd
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h
@@ -0,0 +1,1058 @@
+#ifndef __GOLDEN_GC_SPM_10_1_0_H__
+#define __GOLDEN_GC_SPM_10_1_0_H__
+
+#define GOLDEN_GC_SPM_10_1_0 \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe000, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0x, 
0x28), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0x, 
0x9), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0x, 
0x8), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0x, 
0x1b), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x1), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0x, 
0x8), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x1), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0x, 
0x1b), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0x, 
0x20), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0x, 
0xe), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0x, 
0xc8), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0x, 
0xf), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0x, 
0xcc), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0x, 
0xf), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0x, 
0xd0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0x, 
0xf), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmR

[PATCH] drm/amdgpu: add SPM golden settings for Navi10

2020-04-02 Thread Tianci Yin 
From: "Tianci.Yin" 

Add RLC_SPM golden settings

Change-Id: I616e127171293d915cb3a05dee02f51cec8d8f6f
Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c|9 +
 .../gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h | 1058 +
 2 files changed, 1067 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 70edbbf84338..7c96a894ad37 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -48,6 +48,7 @@
 #include "v10_structs.h"
 #include "gfx_v10_0.h"
 #include "nbio_v2_3.h"
+#include "golden_gc_spm_10_1_0.h"
 
 /**
  * Navi10 has two graphic rings to share each graphic pipe.
@@ -138,6 +139,11 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_0_nv10[] =
/* Pending on emulation bring up */
 };
 
+static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
+{
+   GOLDEN_GC_SPM_10_1_0
+};
+
 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
 {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x, 
0x003c0014),
@@ -388,6 +394,9 @@ static void gfx_v10_0_init_golden_registers(struct 
amdgpu_device *adev)
soc15_program_register_sequence(adev,
golden_settings_gc_10_0_nv10,
(const 
u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
+   soc15_program_register_sequence(adev,
+   
golden_settings_gc_rlc_spm_10_0_nv10,
+   (const 
u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
break;
case CHIP_NAVI14:
soc15_program_register_sequence(adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h 
b/drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h
new file mode 100644
index ..e65af4a6fcdd
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/golden_gc_spm_10_1_0.h
@@ -0,0 +1,1058 @@
+#ifndef __GOLDEN_GC_SPM_10_1_0_H__
+#define __GOLDEN_GC_SPM_10_1_0_H__
+
+#define GOLDEN_GC_SPM_10_1_0 \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe000, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0x, 
0x28), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0x, 
0x9), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0x, 
0x8), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0x, 
0x1b), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x1), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0x, 
0x8), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x1), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0x, 
0x1b), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0x, 
0x20), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0x, 
0xe), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0x, 
0xc8), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0x, 
0xf), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0x, 
0xcc), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0x, 
0xf), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0x, 
0xd0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0x, 
0xf), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0x, 
0xd4), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0x, 
0xf), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xff, 0x0), \
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0x, 
0x24), \
+SOC15_REG_GOLDEN_VALUE(GC, 0,