Re: [PATCH] drm/amdgpu: fix CPDMA hang in PRT mode for VEGA20
On 1/9/19 10:23 AM, Zhou1, Tao wrote: -Original Message- From: amd-gfx On Behalf Of Zhang, Jerry(Junwei) Sent: 2019年1月9日 9:39 To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org Cc: Li, Yukun1 Subject: Re: [PATCH] drm/amdgpu: fix CPDMA hang in PRT mode for VEGA20 On 1/8/19 6:55 PM, Tao Zhou wrote: Fix CPDMA hang in PRT mode for both of VEGA10 and VEGA20 Change-Id: I0e5e089d2192063c4a04fa6dbd534f25eb0177be Signed-off-by: Tao Zhou Tested-by: Yukun.Li --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 968b127c6c8f..fbca0494f871 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -113,7 +113,10 @@ static const struct soc15_reg_golden golden_settings_gc_9_0[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0x, 0x4a2c0e68), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0x, 0xb5d3f197), SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x1920), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x0fff, 0x03ff) + SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x0fff, 0x03ff), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x, 0x0800), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x, 0x0800), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x, 0x8000) IIRC, the CP_DEBUG is the key to fix the CPDMA hang, do we need other settings? or just to align the settings with latest status? Jerry Set CPF_INT_DMA in reg CP_MECx_F32_INT_DIS for Compute and set DISABLE_GFX_HALT_ON_UTCL1_ERROR in CP_DEBUG for GFX. All the settings are needed. Thanks for confirmation. Almost forgot compute. That's fine. BTW, not sure PRT is used for compute as well. Jerry Tao }; static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = @@ -135,10 +138,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x0003, 0x0002), SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x000f, 0x01000107), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x1800, 0x0800), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x0800, 0x0880), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x, 0x0800), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x, 0x0800), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x, 0x8000) + SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x0800, +0x0880) }; static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: fix CPDMA hang in PRT mode for VEGA20
> -Original Message- > From: amd-gfx On Behalf Of > Zhang, Jerry(Junwei) > Sent: 2019年1月9日 9:39 > To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org > Cc: Li, Yukun1 > Subject: Re: [PATCH] drm/amdgpu: fix CPDMA hang in PRT mode for VEGA20 > > On 1/8/19 6:55 PM, Tao Zhou wrote: > > Fix CPDMA hang in PRT mode for both of VEGA10 and VEGA20 > > > > Change-Id: I0e5e089d2192063c4a04fa6dbd534f25eb0177be > > Signed-off-by: Tao Zhou > > Tested-by: Yukun.Li > > --- > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +- > > 1 file changed, 5 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > index 968b127c6c8f..fbca0494f871 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > @@ -113,7 +113,10 @@ static const struct soc15_reg_golden > golden_settings_gc_9_0[] = > > SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, > 0x, 0x4a2c0e68), > > SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, > 0x, 0xb5d3f197), > > SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, > 0x3fff3af3, 0x1920), > > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, > 0x0fff, 0x03ff) > > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, > 0x0fff, 0x03ff), > > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, > 0x, 0x0800), > > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, > 0x, 0x0800), > > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x, > 0x8000) > IIRC, the CP_DEBUG is the key to fix the CPDMA hang, do we need other > settings? > or just to align the settings with latest status? > > Jerry > Set CPF_INT_DMA in reg CP_MECx_F32_INT_DIS for Compute and set DISABLE_GFX_HALT_ON_UTCL1_ERROR in CP_DEBUG for GFX. All the settings are needed. Tao > > }; > > > > static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = > > @@ -135,10 +138,7 @@ static const struct soc15_reg_golden > golden_settings_gc_9_0_vg10[] = > > SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, > 0x0003, 0x0002), > > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, > 0x000f, 0x01000107), > > SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x1800, > 0x0800), > > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, > 0x0800, 0x0880), > > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, > 0x, 0x0800), > > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, > 0x, 0x0800), > > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x, > 0x8000) > > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, > 0x0800, > > +0x0880) > > }; > > > > static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: fix CPDMA hang in PRT mode for VEGA20
On 1/8/19 6:55 PM, Tao Zhou wrote: Fix CPDMA hang in PRT mode for both of VEGA10 and VEGA20 Change-Id: I0e5e089d2192063c4a04fa6dbd534f25eb0177be Signed-off-by: Tao Zhou Tested-by: Yukun.Li --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 968b127c6c8f..fbca0494f871 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -113,7 +113,10 @@ static const struct soc15_reg_golden golden_settings_gc_9_0[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0x, 0x4a2c0e68), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0x, 0xb5d3f197), SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x1920), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x0fff, 0x03ff) + SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x0fff, 0x03ff), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x, 0x0800), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x, 0x0800), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x, 0x8000) IIRC, the CP_DEBUG is the key to fix the CPDMA hang, do we need other settings? or just to align the settings with latest status? Jerry }; static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = @@ -135,10 +138,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x0003, 0x0002), SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x000f, 0x01000107), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x1800, 0x0800), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x0800, 0x0880), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x, 0x0800), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x, 0x0800), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x, 0x8000) + SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x0800, 0x0880) }; static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: fix CPDMA hang in PRT mode for VEGA20
On Tue, Jan 8, 2019 at 5:55 AM Tao Zhou wrote: > > Fix CPDMA hang in PRT mode for both of VEGA10 and VEGA20 > > Change-Id: I0e5e089d2192063c4a04fa6dbd534f25eb0177be > Signed-off-by: Tao Zhou > Tested-by: Yukun.Li Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 968b127c6c8f..fbca0494f871 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -113,7 +113,10 @@ static const struct soc15_reg_golden > golden_settings_gc_9_0[] = > SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0x, > 0x4a2c0e68), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0x, > 0xb5d3f197), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, > 0x1920), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x0fff, > 0x03ff) > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x0fff, > 0x03ff), > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x, > 0x0800), > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x, > 0x0800), > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x, 0x8000) > }; > > static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = > @@ -135,10 +138,7 @@ static const struct soc15_reg_golden > golden_settings_gc_9_0_vg10[] = > SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x0003, > 0x0002), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x000f, > 0x01000107), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x1800, 0x0800), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x0800, > 0x0880), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x, > 0x0800), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x, > 0x0800), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x, 0x8000) > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x0800, 0x0880) > }; > > static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix CPDMA hang in PRT mode for VEGA20
Fix CPDMA hang in PRT mode for both of VEGA10 and VEGA20 Change-Id: I0e5e089d2192063c4a04fa6dbd534f25eb0177be Signed-off-by: Tao Zhou Tested-by: Yukun.Li --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 968b127c6c8f..fbca0494f871 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -113,7 +113,10 @@ static const struct soc15_reg_golden golden_settings_gc_9_0[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0x, 0x4a2c0e68), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0x, 0xb5d3f197), SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x1920), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x0fff, 0x03ff) + SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x0fff, 0x03ff), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x, 0x0800), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x, 0x0800), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x, 0x8000) }; static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = @@ -135,10 +138,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x0003, 0x0002), SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x000f, 0x01000107), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x1800, 0x0800), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x0800, 0x0880), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x, 0x0800), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x, 0x0800), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x, 0x8000) + SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x0800, 0x0880) }; static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx