Re: [PATCH] drm/amdgpu: fix no full coverage issue for gprs initialization
Hi Dennis,
Should we check in the compute shader source codes? I only saw the shader
binaries. This will be helpful if people want to modify those shaders/fix
issues. The source code can be in a comment section above the binary.
Regards,
Oak
On 2021-04-27, 11:31 AM, "amd-gfx on behalf of Christian König"
wrote:
Ok in this case looks good to me.
Christian.
Am 27.04.21 um 17:26 schrieb Zhang, Hawking:
> [AMD Public Use]
>
> This need to be done during reset as well.
>
> Regards,
> Hawking
>
> -Original Message-
> From: Christian König
> Sent: Tuesday, April 27, 2021 23:17
> To: Zhang, Hawking ; Li, Dennis
; amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Kuehling, Felix ; Koenig,
Christian
> Subject: Re: [PATCH] drm/amdgpu: fix no full coverage issue for gprs
initialization
>
> This is only done during bootup, isn't it?
>
> Wouldn't it be better to use the normal IB pool instead of the direct
one? Or do we also need to do this during GPU reset?
>
> Regards,
> Christian.
>
> Am 27.04.21 um 16:55 schrieb Zhang, Hawking:
>> [AMD Public Use]
>>
>> Please split the following into another patch when you commit the one.
>> Other than that, the patch is
>>
>> Reviewed-by: Hawking Zhang
>>
>> Regards,
>> Hawking
>>
>> @@ -479,8 +710,6 @@ void gfx_v9_4_2_init_golden_registers(struct
amdgpu_device *adev,
>> die_id);
>> break;
>> }
>> -
>> -return;
>>}
>>
>> -Original Message-
>> From: Dennis Li
>> Sent: Tuesday, April 27, 2021 22:38
>> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
>> ; Kuehling, Felix ;
>> Zhang, Hawking ; Koenig, Christian
>>
>> Cc: Li, Dennis
>> Subject: [PATCH] drm/amdgpu: fix no full coverage issue for gprs
>> initialization
>>
>> The number of waves is changed to 8, so it is impossible to use old
solution to cover all sgprs.
>>
>> Signed-off-by: Dennis Li
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> index a2fe2dac32c1..2e6789a7dc46 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> @@ -328,7 +328,7 @@ int amdgpu_ib_pool_init(struct amdgpu_device
>> *adev)
>>
>> for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
>> if (i == AMDGPU_IB_POOL_DIRECT)
>> -size = PAGE_SIZE * 2;
>> +size = PAGE_SIZE * 6;
>> else
>> size = AMDGPU_IB_POOL_SIZE;
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
>> index d17e57dea178..77948c033c45 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
>> @@ -32,6 +32,11 @@
>>#include "amdgpu_ras.h"
>>#include "amdgpu_gfx.h"
>>
>> +#define SE_ID_MAX 8
>> +#define CU_ID_MAX 16
>> +#define SIMD_ID_MAX 4
>> +#define WAVE_ID_MAX 10
>> +
>>enum gfx_v9_4_2_utc_type {
>> VML2_MEM,
>> VML2_WALKER_MEM,
>> @@ -81,100 +86,100 @@ static const struct soc15_reg_golden
>> golden_settings_gc_9_4_2_alde[] = { };
>>
>>static const u32 vgpr_init_compute_shader_aldebaran[] = {
>> -0xb8840904, 0xb8851a04, 0xb8861344, 0x9207c006, 0x92088405,
0x81070807,
>> -0x81070407, 0x8e078207, 0xbe88008f, 0xc0410200, 0x0007,
0xd3d94000,
>> -0x1880, 0xd3d94001, 0x1880, 0xd3d94002, 0x1880,
0xd3d94003,
>> -0x1880, 0xd3d94004, 0x1880, 0xd3d94005, 0x1880,
0xd3d94006,
>> -0x1880, 0xd3d94007, 0x1880, 0xd3d94008, 0x1880,
0xd3d94009,
>> -0x1880, 0xd3d9400a, 0x1880, 0xd3d9400b, 0x1880,
0xd3d9400c,
>> -0x1880, 0xd3d9400d, 0x1880, 0xd3d9400e, 0x1880,
0xd3d9400f,
>> -0x1880, 0xd3d94010, 0x1880, 0xd3d94011, 0x1880,
0xd3d94012,
>> -0x1880, 0xd3d94013, 0x1880, 0xd3d94014, 0x1880,
0xd3d94015,
>&g
Re: [PATCH] drm/amdgpu: fix no full coverage issue for gprs initialization
Ok in this case looks good to me.
Christian.
Am 27.04.21 um 17:26 schrieb Zhang, Hawking:
[AMD Public Use]
This need to be done during reset as well.
Regards,
Hawking
-Original Message-
From: Christian König
Sent: Tuesday, April 27, 2021 23:17
To: Zhang, Hawking ; Li, Dennis ;
amd-gfx@lists.freedesktop.org; Deucher, Alexander ; Kuehling, Felix
; Koenig, Christian
Subject: Re: [PATCH] drm/amdgpu: fix no full coverage issue for gprs
initialization
This is only done during bootup, isn't it?
Wouldn't it be better to use the normal IB pool instead of the direct one? Or
do we also need to do this during GPU reset?
Regards,
Christian.
Am 27.04.21 um 16:55 schrieb Zhang, Hawking:
[AMD Public Use]
Please split the following into another patch when you commit the one.
Other than that, the patch is
Reviewed-by: Hawking Zhang
Regards,
Hawking
@@ -479,8 +710,6 @@ void gfx_v9_4_2_init_golden_registers(struct amdgpu_device
*adev,
die_id);
break;
}
-
- return;
}
-Original Message-
From: Dennis Li
Sent: Tuesday, April 27, 2021 22:38
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Kuehling, Felix ;
Zhang, Hawking ; Koenig, Christian
Cc: Li, Dennis
Subject: [PATCH] drm/amdgpu: fix no full coverage issue for gprs
initialization
The number of waves is changed to 8, so it is impossible to use old solution to
cover all sgprs.
Signed-off-by: Dennis Li
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index a2fe2dac32c1..2e6789a7dc46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -328,7 +328,7 @@ int amdgpu_ib_pool_init(struct amdgpu_device
*adev)
for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
if (i == AMDGPU_IB_POOL_DIRECT)
- size = PAGE_SIZE * 2;
+ size = PAGE_SIZE * 6;
else
size = AMDGPU_IB_POOL_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
index d17e57dea178..77948c033c45 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
@@ -32,6 +32,11 @@
#include "amdgpu_ras.h"
#include "amdgpu_gfx.h"
+#define SE_ID_MAX 8
+#define CU_ID_MAX 16
+#define SIMD_ID_MAX 4
+#define WAVE_ID_MAX 10
+
enum gfx_v9_4_2_utc_type {
VML2_MEM,
VML2_WALKER_MEM,
@@ -81,100 +86,100 @@ static const struct soc15_reg_golden
golden_settings_gc_9_4_2_alde[] = { };
static const u32 vgpr_init_compute_shader_aldebaran[] = {
- 0xb8840904, 0xb8851a04, 0xb8861344, 0x9207c006, 0x92088405, 0x81070807,
- 0x81070407, 0x8e078207, 0xbe88008f, 0xc0410200, 0x0007, 0xd3d94000,
- 0x1880, 0xd3d94001, 0x1880, 0xd3d94002, 0x1880, 0xd3d94003,
- 0x1880, 0xd3d94004, 0x1880, 0xd3d94005, 0x1880, 0xd3d94006,
- 0x1880, 0xd3d94007, 0x1880, 0xd3d94008, 0x1880, 0xd3d94009,
- 0x1880, 0xd3d9400a, 0x1880, 0xd3d9400b, 0x1880, 0xd3d9400c,
- 0x1880, 0xd3d9400d, 0x1880, 0xd3d9400e, 0x1880, 0xd3d9400f,
- 0x1880, 0xd3d94010, 0x1880, 0xd3d94011, 0x1880, 0xd3d94012,
- 0x1880, 0xd3d94013, 0x1880, 0xd3d94014, 0x1880, 0xd3d94015,
- 0x1880, 0xd3d94016, 0x1880, 0xd3d94017, 0x1880, 0xd3d94018,
- 0x1880, 0xd3d94019, 0x1880, 0xd3d9401a, 0x1880, 0xd3d9401b,
- 0x1880, 0xd3d9401c, 0x1880, 0xd3d9401d, 0x1880, 0xd3d9401e,
- 0x1880, 0xd3d9401f, 0x1880, 0xd3d94020, 0x1880, 0xd3d94021,
- 0x1880, 0xd3d94022, 0x1880, 0xd3d94023, 0x1880, 0xd3d94024,
- 0x1880, 0xd3d94025, 0x1880, 0xd3d94026, 0x1880, 0xd3d94027,
- 0x1880, 0xd3d94028, 0x1880, 0xd3d94029, 0x1880, 0xd3d9402a,
- 0x1880, 0xd3d9402b, 0x1880, 0xd3d9402c, 0x1880, 0xd3d9402d,
- 0x1880, 0xd3d9402e, 0x1880, 0xd3d9402f, 0x1880, 0xd3d94030,
- 0x1880, 0xd3d94031, 0x1880, 0xd3d94032, 0x1880, 0xd3d94033,
- 0x1880, 0xd3d94034, 0x1880, 0xd3d94035, 0x1880, 0xd3d94036,
- 0x1880, 0xd3d94037, 0x1880, 0xd3d94038, 0x1880, 0xd3d94039,
- 0x1880, 0xd3d9403a, 0x1880, 0xd3d9403b, 0x1880, 0xd3d9403c,
- 0x1880, 0xd3d9403d, 0x1880, 0xd3d9403e, 0x1880, 0xd3d9403f,
- 0x1880, 0xd3d94040, 0x1880, 0xd3d94041, 0x1880, 0xd3d94042,
- 0x1880, 0xd3d94043, 0x1880, 0xd3d94044, 0x1880, 0xd3d94045,
- 0x1880, 0xd3d94046, 0x1880, 0xd3d94047, 0x1880, 0xd3d94048,
- 0x1880, 0xd3d94049, 0x1880, 0xd3d9404a, 0x1880, 0xd3d9404b,
- 0x1880, 0xd3d9404c, 0x1880, 0xd3d9404d, 0x1880, 0xd3d9404e,
- 0x1880, 0xd3d9404f, 0x1880, 0
RE: [PATCH] drm/amdgpu: fix no full coverage issue for gprs initialization
[AMD Public Use]
This need to be done during reset as well.
Regards,
Hawking
-Original Message-
From: Christian König
Sent: Tuesday, April 27, 2021 23:17
To: Zhang, Hawking ; Li, Dennis ;
amd-gfx@lists.freedesktop.org; Deucher, Alexander ;
Kuehling, Felix ; Koenig, Christian
Subject: Re: [PATCH] drm/amdgpu: fix no full coverage issue for gprs
initialization
This is only done during bootup, isn't it?
Wouldn't it be better to use the normal IB pool instead of the direct one? Or
do we also need to do this during GPU reset?
Regards,
Christian.
Am 27.04.21 um 16:55 schrieb Zhang, Hawking:
> [AMD Public Use]
>
> Please split the following into another patch when you commit the one.
> Other than that, the patch is
>
> Reviewed-by: Hawking Zhang
>
> Regards,
> Hawking
>
> @@ -479,8 +710,6 @@ void gfx_v9_4_2_init_golden_registers(struct
> amdgpu_device *adev,
>die_id);
> break;
> }
> -
> - return;
> }
>
> -Original Message-
> From: Dennis Li
> Sent: Tuesday, April 27, 2021 22:38
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> ; Kuehling, Felix ;
> Zhang, Hawking ; Koenig, Christian
>
> Cc: Li, Dennis
> Subject: [PATCH] drm/amdgpu: fix no full coverage issue for gprs
> initialization
>
> The number of waves is changed to 8, so it is impossible to use old solution
> to cover all sgprs.
>
> Signed-off-by: Dennis Li
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index a2fe2dac32c1..2e6789a7dc46 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -328,7 +328,7 @@ int amdgpu_ib_pool_init(struct amdgpu_device
> *adev)
>
> for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
> if (i == AMDGPU_IB_POOL_DIRECT)
> - size = PAGE_SIZE * 2;
> + size = PAGE_SIZE * 6;
> else
> size = AMDGPU_IB_POOL_SIZE;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
> index d17e57dea178..77948c033c45 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
> @@ -32,6 +32,11 @@
> #include "amdgpu_ras.h"
> #include "amdgpu_gfx.h"
>
> +#define SE_ID_MAX 8
> +#define CU_ID_MAX 16
> +#define SIMD_ID_MAX 4
> +#define WAVE_ID_MAX 10
> +
> enum gfx_v9_4_2_utc_type {
> VML2_MEM,
> VML2_WALKER_MEM,
> @@ -81,100 +86,100 @@ static const struct soc15_reg_golden
> golden_settings_gc_9_4_2_alde[] = { };
>
> static const u32 vgpr_init_compute_shader_aldebaran[] = {
> - 0xb8840904, 0xb8851a04, 0xb8861344, 0x9207c006, 0x92088405, 0x81070807,
> - 0x81070407, 0x8e078207, 0xbe88008f, 0xc0410200, 0x0007, 0xd3d94000,
> - 0x1880, 0xd3d94001, 0x1880, 0xd3d94002, 0x1880, 0xd3d94003,
> - 0x1880, 0xd3d94004, 0x1880, 0xd3d94005, 0x1880, 0xd3d94006,
> - 0x1880, 0xd3d94007, 0x1880, 0xd3d94008, 0x1880, 0xd3d94009,
> - 0x1880, 0xd3d9400a, 0x1880, 0xd3d9400b, 0x1880, 0xd3d9400c,
> - 0x1880, 0xd3d9400d, 0x1880, 0xd3d9400e, 0x1880, 0xd3d9400f,
> - 0x1880, 0xd3d94010, 0x1880, 0xd3d94011, 0x1880, 0xd3d94012,
> - 0x1880, 0xd3d94013, 0x1880, 0xd3d94014, 0x1880, 0xd3d94015,
> - 0x1880, 0xd3d94016, 0x1880, 0xd3d94017, 0x1880, 0xd3d94018,
> - 0x1880, 0xd3d94019, 0x1880, 0xd3d9401a, 0x1880, 0xd3d9401b,
> - 0x1880, 0xd3d9401c, 0x1880, 0xd3d9401d, 0x1880, 0xd3d9401e,
> - 0x1880, 0xd3d9401f, 0x1880, 0xd3d94020, 0x1880, 0xd3d94021,
> - 0x1880, 0xd3d94022, 0x1880, 0xd3d94023, 0x1880, 0xd3d94024,
> - 0x1880, 0xd3d94025, 0x1880, 0xd3d94026, 0x1880, 0xd3d94027,
> - 0x1880, 0xd3d94028, 0x1880, 0xd3d94029, 0x1880, 0xd3d9402a,
> - 0x1880, 0xd3d9402b, 0x1880, 0xd3d9402c, 0x1880, 0xd3d9402d,
> - 0x1880, 0xd3d9402e, 0x1880, 0xd3d9402f, 0x1880, 0xd3d94030,
> - 0x1880, 0xd3d94031, 0x1880, 0xd3d94032, 0x1880, 0xd3d94033,
> - 0x1880, 0xd3d94034, 0x1880, 0xd3d94035, 0x1880, 0xd3d94036,
> - 0x1880, 0xd3d94037, 0x1880, 0xd3d94038, 0x1880, 0xd3d94039,
> - 0x1880, 0xd3d9403a, 0x1880, 0xd3d9403b, 0x1880, 0xd3d9403c,
> - 0x1880, 0xd3d9403d, 0x1880, 0xd3d9403e, 0x1880, 0xd3d9403f,
> - 0x1880, 0xd3d94040, 0x1880, 0xd3d94041, 0x1880, 0xd3d94042,
> - 0x1880, 0xd3d94043, 0x1880, 0xd3d94044, 0x188
Re: [PATCH] drm/amdgpu: fix no full coverage issue for gprs initialization
This is only done during bootup, isn't it?
Wouldn't it be better to use the normal IB pool instead of the direct
one? Or do we also need to do this during GPU reset?
Regards,
Christian.
Am 27.04.21 um 16:55 schrieb Zhang, Hawking:
[AMD Public Use]
Please split the following into another patch when you commit the one. Other
than that, the patch is
Reviewed-by: Hawking Zhang
Regards,
Hawking
@@ -479,8 +710,6 @@ void gfx_v9_4_2_init_golden_registers(struct amdgpu_device
*adev,
die_id);
break;
}
-
- return;
}
-Original Message-
From: Dennis Li
Sent: Tuesday, April 27, 2021 22:38
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander ; Kuehling,
Felix ; Zhang, Hawking ; Koenig, Christian
Cc: Li, Dennis
Subject: [PATCH] drm/amdgpu: fix no full coverage issue for gprs initialization
The number of waves is changed to 8, so it is impossible to use old solution to
cover all sgprs.
Signed-off-by: Dennis Li
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index a2fe2dac32c1..2e6789a7dc46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -328,7 +328,7 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev)
for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
if (i == AMDGPU_IB_POOL_DIRECT)
- size = PAGE_SIZE * 2;
+ size = PAGE_SIZE * 6;
else
size = AMDGPU_IB_POOL_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
index d17e57dea178..77948c033c45 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
@@ -32,6 +32,11 @@
#include "amdgpu_ras.h"
#include "amdgpu_gfx.h"
+#define SE_ID_MAX 8
+#define CU_ID_MAX 16
+#define SIMD_ID_MAX 4
+#define WAVE_ID_MAX 10
+
enum gfx_v9_4_2_utc_type {
VML2_MEM,
VML2_WALKER_MEM,
@@ -81,100 +86,100 @@ static const struct soc15_reg_golden
golden_settings_gc_9_4_2_alde[] = { };
static const u32 vgpr_init_compute_shader_aldebaran[] = {
- 0xb8840904, 0xb8851a04, 0xb8861344, 0x9207c006, 0x92088405, 0x81070807,
- 0x81070407, 0x8e078207, 0xbe88008f, 0xc0410200, 0x0007, 0xd3d94000,
- 0x1880, 0xd3d94001, 0x1880, 0xd3d94002, 0x1880, 0xd3d94003,
- 0x1880, 0xd3d94004, 0x1880, 0xd3d94005, 0x1880, 0xd3d94006,
- 0x1880, 0xd3d94007, 0x1880, 0xd3d94008, 0x1880, 0xd3d94009,
- 0x1880, 0xd3d9400a, 0x1880, 0xd3d9400b, 0x1880, 0xd3d9400c,
- 0x1880, 0xd3d9400d, 0x1880, 0xd3d9400e, 0x1880, 0xd3d9400f,
- 0x1880, 0xd3d94010, 0x1880, 0xd3d94011, 0x1880, 0xd3d94012,
- 0x1880, 0xd3d94013, 0x1880, 0xd3d94014, 0x1880, 0xd3d94015,
- 0x1880, 0xd3d94016, 0x1880, 0xd3d94017, 0x1880, 0xd3d94018,
- 0x1880, 0xd3d94019, 0x1880, 0xd3d9401a, 0x1880, 0xd3d9401b,
- 0x1880, 0xd3d9401c, 0x1880, 0xd3d9401d, 0x1880, 0xd3d9401e,
- 0x1880, 0xd3d9401f, 0x1880, 0xd3d94020, 0x1880, 0xd3d94021,
- 0x1880, 0xd3d94022, 0x1880, 0xd3d94023, 0x1880, 0xd3d94024,
- 0x1880, 0xd3d94025, 0x1880, 0xd3d94026, 0x1880, 0xd3d94027,
- 0x1880, 0xd3d94028, 0x1880, 0xd3d94029, 0x1880, 0xd3d9402a,
- 0x1880, 0xd3d9402b, 0x1880, 0xd3d9402c, 0x1880, 0xd3d9402d,
- 0x1880, 0xd3d9402e, 0x1880, 0xd3d9402f, 0x1880, 0xd3d94030,
- 0x1880, 0xd3d94031, 0x1880, 0xd3d94032, 0x1880, 0xd3d94033,
- 0x1880, 0xd3d94034, 0x1880, 0xd3d94035, 0x1880, 0xd3d94036,
- 0x1880, 0xd3d94037, 0x1880, 0xd3d94038, 0x1880, 0xd3d94039,
- 0x1880, 0xd3d9403a, 0x1880, 0xd3d9403b, 0x1880, 0xd3d9403c,
- 0x1880, 0xd3d9403d, 0x1880, 0xd3d9403e, 0x1880, 0xd3d9403f,
- 0x1880, 0xd3d94040, 0x1880, 0xd3d94041, 0x1880, 0xd3d94042,
- 0x1880, 0xd3d94043, 0x1880, 0xd3d94044, 0x1880, 0xd3d94045,
- 0x1880, 0xd3d94046, 0x1880, 0xd3d94047, 0x1880, 0xd3d94048,
- 0x1880, 0xd3d94049, 0x1880, 0xd3d9404a, 0x1880, 0xd3d9404b,
- 0x1880, 0xd3d9404c, 0x1880, 0xd3d9404d, 0x1880, 0xd3d9404e,
- 0x1880, 0xd3d9404f, 0x1880, 0xd3d94050, 0x1880, 0xd3d94051,
- 0x1880, 0xd3d94052, 0x1880, 0xd3d94053, 0x1880, 0xd3d94054,
- 0x1880, 0xd3d94055, 0x1880, 0xd3d94056, 0x1880, 0xd3d94057,
- 0x1880, 0xd3d94058, 0x1880, 0xd3d94059, 0x1880, 0xd3d9405a,
- 0x1880, 0xd3d9405b, 0x1880, 0xd3d9405c, 0x1880, 0xd3d9405d,
- 0x1880, 0xd3d9405e, 0x1880, 0xd3d9405f, 0x1880, 0xd3d94060,
- 0x1880, 0xd3d94061, 0x1880, 0
RE: [PATCH] drm/amdgpu: fix no full coverage issue for gprs initialization
[AMD Public Use]
BTW, please explicitly call out aldebaran in either commit description or
subject since it is really aldebaran specific algorithm.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Tuesday, April 27, 2021 22:56
To: Li, Dennis ; amd-gfx@lists.freedesktop.org; Deucher,
Alexander ; Kuehling, Felix
; Koenig, Christian
Cc: Li, Dennis
Subject: RE: [PATCH] drm/amdgpu: fix no full coverage issue for gprs
initialization
[AMD Public Use]
Please split the following into another patch when you commit the one. Other
than that, the patch is
Reviewed-by: Hawking Zhang
Regards,
Hawking
@@ -479,8 +710,6 @@ void gfx_v9_4_2_init_golden_registers(struct amdgpu_device
*adev,
die_id);
break;
}
-
- return;
}
-Original Message-
From: Dennis Li
Sent: Tuesday, April 27, 2021 22:38
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Kuehling, Felix ; Zhang,
Hawking ; Koenig, Christian
Cc: Li, Dennis
Subject: [PATCH] drm/amdgpu: fix no full coverage issue for gprs initialization
The number of waves is changed to 8, so it is impossible to use old solution to
cover all sgprs.
Signed-off-by: Dennis Li
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index a2fe2dac32c1..2e6789a7dc46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -328,7 +328,7 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev)
for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
if (i == AMDGPU_IB_POOL_DIRECT)
- size = PAGE_SIZE * 2;
+ size = PAGE_SIZE * 6;
else
size = AMDGPU_IB_POOL_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
index d17e57dea178..77948c033c45 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
@@ -32,6 +32,11 @@
#include "amdgpu_ras.h"
#include "amdgpu_gfx.h"
+#define SE_ID_MAX 8
+#define CU_ID_MAX 16
+#define SIMD_ID_MAX 4
+#define WAVE_ID_MAX 10
+
enum gfx_v9_4_2_utc_type {
VML2_MEM,
VML2_WALKER_MEM,
@@ -81,100 +86,100 @@ static const struct soc15_reg_golden
golden_settings_gc_9_4_2_alde[] = { };
static const u32 vgpr_init_compute_shader_aldebaran[] = {
- 0xb8840904, 0xb8851a04, 0xb8861344, 0x9207c006, 0x92088405, 0x81070807,
- 0x81070407, 0x8e078207, 0xbe88008f, 0xc0410200, 0x0007, 0xd3d94000,
- 0x1880, 0xd3d94001, 0x1880, 0xd3d94002, 0x1880, 0xd3d94003,
- 0x1880, 0xd3d94004, 0x1880, 0xd3d94005, 0x1880, 0xd3d94006,
- 0x1880, 0xd3d94007, 0x1880, 0xd3d94008, 0x1880, 0xd3d94009,
- 0x1880, 0xd3d9400a, 0x1880, 0xd3d9400b, 0x1880, 0xd3d9400c,
- 0x1880, 0xd3d9400d, 0x1880, 0xd3d9400e, 0x1880, 0xd3d9400f,
- 0x1880, 0xd3d94010, 0x1880, 0xd3d94011, 0x1880, 0xd3d94012,
- 0x1880, 0xd3d94013, 0x1880, 0xd3d94014, 0x1880, 0xd3d94015,
- 0x1880, 0xd3d94016, 0x1880, 0xd3d94017, 0x1880, 0xd3d94018,
- 0x1880, 0xd3d94019, 0x1880, 0xd3d9401a, 0x1880, 0xd3d9401b,
- 0x1880, 0xd3d9401c, 0x1880, 0xd3d9401d, 0x1880, 0xd3d9401e,
- 0x1880, 0xd3d9401f, 0x1880, 0xd3d94020, 0x1880, 0xd3d94021,
- 0x1880, 0xd3d94022, 0x1880, 0xd3d94023, 0x1880, 0xd3d94024,
- 0x1880, 0xd3d94025, 0x1880, 0xd3d94026, 0x1880, 0xd3d94027,
- 0x1880, 0xd3d94028, 0x1880, 0xd3d94029, 0x1880, 0xd3d9402a,
- 0x1880, 0xd3d9402b, 0x1880, 0xd3d9402c, 0x1880, 0xd3d9402d,
- 0x1880, 0xd3d9402e, 0x1880, 0xd3d9402f, 0x1880, 0xd3d94030,
- 0x1880, 0xd3d94031, 0x1880, 0xd3d94032, 0x1880, 0xd3d94033,
- 0x1880, 0xd3d94034, 0x1880, 0xd3d94035, 0x1880, 0xd3d94036,
- 0x1880, 0xd3d94037, 0x1880, 0xd3d94038, 0x1880, 0xd3d94039,
- 0x1880, 0xd3d9403a, 0x1880, 0xd3d9403b, 0x1880, 0xd3d9403c,
- 0x1880, 0xd3d9403d, 0x1880, 0xd3d9403e, 0x1880, 0xd3d9403f,
- 0x1880, 0xd3d94040, 0x1880, 0xd3d94041, 0x1880, 0xd3d94042,
- 0x1880, 0xd3d94043, 0x1880, 0xd3d94044, 0x1880, 0xd3d94045,
- 0x1880, 0xd3d94046, 0x1880, 0xd3d94047, 0x1880, 0xd3d94048,
- 0x1880, 0xd3d94049, 0x1880, 0xd3d9404a, 0x1880, 0xd3d9404b,
- 0x1880, 0xd3d9404c, 0x1880, 0xd3d9404d, 0x1880, 0xd3d9404e,
- 0x1880, 0xd3d9404f, 0x1880, 0xd3d94050, 0x1880, 0xd3d94051,
- 0x1880, 0xd3d94052, 0x1880, 0xd3d94053, 0x1880, 0xd3d94054,
- 0x1880, 0xd3d94055, 0x1880, 0xd3d94056, 0x1880, 0xd3d94057,
- 0x1880, 0xd3d94058, 0x1880, 0xd3d94059,
RE: [PATCH] drm/amdgpu: fix no full coverage issue for gprs initialization
[AMD Public Use]
Please split the following into another patch when you commit the one. Other
than that, the patch is
Reviewed-by: Hawking Zhang
Regards,
Hawking
@@ -479,8 +710,6 @@ void gfx_v9_4_2_init_golden_registers(struct amdgpu_device
*adev,
die_id);
break;
}
-
- return;
}
-Original Message-
From: Dennis Li
Sent: Tuesday, April 27, 2021 22:38
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Kuehling, Felix ; Zhang,
Hawking ; Koenig, Christian
Cc: Li, Dennis
Subject: [PATCH] drm/amdgpu: fix no full coverage issue for gprs initialization
The number of waves is changed to 8, so it is impossible to use old solution to
cover all sgprs.
Signed-off-by: Dennis Li
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index a2fe2dac32c1..2e6789a7dc46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -328,7 +328,7 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev)
for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
if (i == AMDGPU_IB_POOL_DIRECT)
- size = PAGE_SIZE * 2;
+ size = PAGE_SIZE * 6;
else
size = AMDGPU_IB_POOL_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
index d17e57dea178..77948c033c45 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
@@ -32,6 +32,11 @@
#include "amdgpu_ras.h"
#include "amdgpu_gfx.h"
+#define SE_ID_MAX 8
+#define CU_ID_MAX 16
+#define SIMD_ID_MAX 4
+#define WAVE_ID_MAX 10
+
enum gfx_v9_4_2_utc_type {
VML2_MEM,
VML2_WALKER_MEM,
@@ -81,100 +86,100 @@ static const struct soc15_reg_golden
golden_settings_gc_9_4_2_alde[] = { };
static const u32 vgpr_init_compute_shader_aldebaran[] = {
- 0xb8840904, 0xb8851a04, 0xb8861344, 0x9207c006, 0x92088405, 0x81070807,
- 0x81070407, 0x8e078207, 0xbe88008f, 0xc0410200, 0x0007, 0xd3d94000,
- 0x1880, 0xd3d94001, 0x1880, 0xd3d94002, 0x1880, 0xd3d94003,
- 0x1880, 0xd3d94004, 0x1880, 0xd3d94005, 0x1880, 0xd3d94006,
- 0x1880, 0xd3d94007, 0x1880, 0xd3d94008, 0x1880, 0xd3d94009,
- 0x1880, 0xd3d9400a, 0x1880, 0xd3d9400b, 0x1880, 0xd3d9400c,
- 0x1880, 0xd3d9400d, 0x1880, 0xd3d9400e, 0x1880, 0xd3d9400f,
- 0x1880, 0xd3d94010, 0x1880, 0xd3d94011, 0x1880, 0xd3d94012,
- 0x1880, 0xd3d94013, 0x1880, 0xd3d94014, 0x1880, 0xd3d94015,
- 0x1880, 0xd3d94016, 0x1880, 0xd3d94017, 0x1880, 0xd3d94018,
- 0x1880, 0xd3d94019, 0x1880, 0xd3d9401a, 0x1880, 0xd3d9401b,
- 0x1880, 0xd3d9401c, 0x1880, 0xd3d9401d, 0x1880, 0xd3d9401e,
- 0x1880, 0xd3d9401f, 0x1880, 0xd3d94020, 0x1880, 0xd3d94021,
- 0x1880, 0xd3d94022, 0x1880, 0xd3d94023, 0x1880, 0xd3d94024,
- 0x1880, 0xd3d94025, 0x1880, 0xd3d94026, 0x1880, 0xd3d94027,
- 0x1880, 0xd3d94028, 0x1880, 0xd3d94029, 0x1880, 0xd3d9402a,
- 0x1880, 0xd3d9402b, 0x1880, 0xd3d9402c, 0x1880, 0xd3d9402d,
- 0x1880, 0xd3d9402e, 0x1880, 0xd3d9402f, 0x1880, 0xd3d94030,
- 0x1880, 0xd3d94031, 0x1880, 0xd3d94032, 0x1880, 0xd3d94033,
- 0x1880, 0xd3d94034, 0x1880, 0xd3d94035, 0x1880, 0xd3d94036,
- 0x1880, 0xd3d94037, 0x1880, 0xd3d94038, 0x1880, 0xd3d94039,
- 0x1880, 0xd3d9403a, 0x1880, 0xd3d9403b, 0x1880, 0xd3d9403c,
- 0x1880, 0xd3d9403d, 0x1880, 0xd3d9403e, 0x1880, 0xd3d9403f,
- 0x1880, 0xd3d94040, 0x1880, 0xd3d94041, 0x1880, 0xd3d94042,
- 0x1880, 0xd3d94043, 0x1880, 0xd3d94044, 0x1880, 0xd3d94045,
- 0x1880, 0xd3d94046, 0x1880, 0xd3d94047, 0x1880, 0xd3d94048,
- 0x1880, 0xd3d94049, 0x1880, 0xd3d9404a, 0x1880, 0xd3d9404b,
- 0x1880, 0xd3d9404c, 0x1880, 0xd3d9404d, 0x1880, 0xd3d9404e,
- 0x1880, 0xd3d9404f, 0x1880, 0xd3d94050, 0x1880, 0xd3d94051,
- 0x1880, 0xd3d94052, 0x1880, 0xd3d94053, 0x1880, 0xd3d94054,
- 0x1880, 0xd3d94055, 0x1880, 0xd3d94056, 0x1880, 0xd3d94057,
- 0x1880, 0xd3d94058, 0x1880, 0xd3d94059, 0x1880, 0xd3d9405a,
- 0x1880, 0xd3d9405b, 0x1880, 0xd3d9405c, 0x1880, 0xd3d9405d,
- 0x1880, 0xd3d9405e, 0x1880, 0xd3d9405f, 0x1880, 0xd3d94060,
- 0x1880, 0xd3d94061, 0x1880, 0xd3d94062, 0x1880, 0xd3d94063,
- 0x1880, 0xd3d94064, 0x1880, 0xd3d94065, 0x1880, 0xd3d94066,
- 0x1880, 0xd3d94067, 0x1880, 0xd3d94068, 0x1880, 0xd3d94069,
- 0x1880, 0xd3d9406a, 0x1880, 0xd3d9406b,
[PATCH] drm/amdgpu: fix no full coverage issue for gprs initialization
The number of waves is changed to 8, so it is impossible to use old
solution to cover all sgprs.
Signed-off-by: Dennis Li
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index a2fe2dac32c1..2e6789a7dc46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -328,7 +328,7 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev)
for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
if (i == AMDGPU_IB_POOL_DIRECT)
- size = PAGE_SIZE * 2;
+ size = PAGE_SIZE * 6;
else
size = AMDGPU_IB_POOL_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
index d17e57dea178..77948c033c45 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
@@ -32,6 +32,11 @@
#include "amdgpu_ras.h"
#include "amdgpu_gfx.h"
+#define SE_ID_MAX 8
+#define CU_ID_MAX 16
+#define SIMD_ID_MAX 4
+#define WAVE_ID_MAX 10
+
enum gfx_v9_4_2_utc_type {
VML2_MEM,
VML2_WALKER_MEM,
@@ -81,100 +86,100 @@ static const struct soc15_reg_golden
golden_settings_gc_9_4_2_alde[] = {
};
static const u32 vgpr_init_compute_shader_aldebaran[] = {
- 0xb8840904, 0xb8851a04, 0xb8861344, 0x9207c006, 0x92088405, 0x81070807,
- 0x81070407, 0x8e078207, 0xbe88008f, 0xc0410200, 0x0007, 0xd3d94000,
- 0x1880, 0xd3d94001, 0x1880, 0xd3d94002, 0x1880, 0xd3d94003,
- 0x1880, 0xd3d94004, 0x1880, 0xd3d94005, 0x1880, 0xd3d94006,
- 0x1880, 0xd3d94007, 0x1880, 0xd3d94008, 0x1880, 0xd3d94009,
- 0x1880, 0xd3d9400a, 0x1880, 0xd3d9400b, 0x1880, 0xd3d9400c,
- 0x1880, 0xd3d9400d, 0x1880, 0xd3d9400e, 0x1880, 0xd3d9400f,
- 0x1880, 0xd3d94010, 0x1880, 0xd3d94011, 0x1880, 0xd3d94012,
- 0x1880, 0xd3d94013, 0x1880, 0xd3d94014, 0x1880, 0xd3d94015,
- 0x1880, 0xd3d94016, 0x1880, 0xd3d94017, 0x1880, 0xd3d94018,
- 0x1880, 0xd3d94019, 0x1880, 0xd3d9401a, 0x1880, 0xd3d9401b,
- 0x1880, 0xd3d9401c, 0x1880, 0xd3d9401d, 0x1880, 0xd3d9401e,
- 0x1880, 0xd3d9401f, 0x1880, 0xd3d94020, 0x1880, 0xd3d94021,
- 0x1880, 0xd3d94022, 0x1880, 0xd3d94023, 0x1880, 0xd3d94024,
- 0x1880, 0xd3d94025, 0x1880, 0xd3d94026, 0x1880, 0xd3d94027,
- 0x1880, 0xd3d94028, 0x1880, 0xd3d94029, 0x1880, 0xd3d9402a,
- 0x1880, 0xd3d9402b, 0x1880, 0xd3d9402c, 0x1880, 0xd3d9402d,
- 0x1880, 0xd3d9402e, 0x1880, 0xd3d9402f, 0x1880, 0xd3d94030,
- 0x1880, 0xd3d94031, 0x1880, 0xd3d94032, 0x1880, 0xd3d94033,
- 0x1880, 0xd3d94034, 0x1880, 0xd3d94035, 0x1880, 0xd3d94036,
- 0x1880, 0xd3d94037, 0x1880, 0xd3d94038, 0x1880, 0xd3d94039,
- 0x1880, 0xd3d9403a, 0x1880, 0xd3d9403b, 0x1880, 0xd3d9403c,
- 0x1880, 0xd3d9403d, 0x1880, 0xd3d9403e, 0x1880, 0xd3d9403f,
- 0x1880, 0xd3d94040, 0x1880, 0xd3d94041, 0x1880, 0xd3d94042,
- 0x1880, 0xd3d94043, 0x1880, 0xd3d94044, 0x1880, 0xd3d94045,
- 0x1880, 0xd3d94046, 0x1880, 0xd3d94047, 0x1880, 0xd3d94048,
- 0x1880, 0xd3d94049, 0x1880, 0xd3d9404a, 0x1880, 0xd3d9404b,
- 0x1880, 0xd3d9404c, 0x1880, 0xd3d9404d, 0x1880, 0xd3d9404e,
- 0x1880, 0xd3d9404f, 0x1880, 0xd3d94050, 0x1880, 0xd3d94051,
- 0x1880, 0xd3d94052, 0x1880, 0xd3d94053, 0x1880, 0xd3d94054,
- 0x1880, 0xd3d94055, 0x1880, 0xd3d94056, 0x1880, 0xd3d94057,
- 0x1880, 0xd3d94058, 0x1880, 0xd3d94059, 0x1880, 0xd3d9405a,
- 0x1880, 0xd3d9405b, 0x1880, 0xd3d9405c, 0x1880, 0xd3d9405d,
- 0x1880, 0xd3d9405e, 0x1880, 0xd3d9405f, 0x1880, 0xd3d94060,
- 0x1880, 0xd3d94061, 0x1880, 0xd3d94062, 0x1880, 0xd3d94063,
- 0x1880, 0xd3d94064, 0x1880, 0xd3d94065, 0x1880, 0xd3d94066,
- 0x1880, 0xd3d94067, 0x1880, 0xd3d94068, 0x1880, 0xd3d94069,
- 0x1880, 0xd3d9406a, 0x1880, 0xd3d9406b, 0x1880, 0xd3d9406c,
- 0x1880, 0xd3d9406d, 0x1880, 0xd3d9406e, 0x1880, 0xd3d9406f,
- 0x1880, 0xd3d94070, 0x1880, 0xd3d94071, 0x1880, 0xd3d94072,
- 0x1880, 0xd3d94073, 0x1880, 0xd3d94074, 0x1880, 0xd3d94075,
- 0x1880, 0xd3d94076, 0x1880, 0xd3d94077, 0x1880, 0xd3d94078,
- 0x1880, 0xd3d94079, 0x1880, 0xd3d9407a, 0x1880, 0xd3d9407b,
- 0x1880, 0xd3d9407c, 0x1880, 0xd3d9407d, 0x1880, 0xd3d9407e,
- 0x1880, 0xd3d9407f, 0x1880, 0xd3d94080, 0x1880, 0xd3d94081,
- 0x1880, 0xd3d94082, 0x1880, 0xd3d94083, 0x1880, 0xd3d94084,
-
