RE: [PATCH] drm/amdgpu: refine uvd gate logic for CI.

2016-08-24 Thread Deucher, Alexander
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, August 24, 2016 7:56 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH] drm/amdgpu: refine uvd gate logic for CI.
> 
> uvd dpm will be controlled by uvd.
> dpm just disable uvd dpm in case of suspend when play video.
> due to the new logic of uvd_begin_use/end_use,
> if disable uvd dpm in late init, will have no chance to
> enable uvd dpm after resume until play video again.
> 
> Change-Id: I14792383ed50c0465699cdda7f1bad2ea144b861
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 6 ++
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> index a0d63a2..1d8c375 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> @@ -5396,7 +5396,7 @@ static void ci_dpm_disable(struct amdgpu_device
> *adev)
>   amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
>  AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
> 
> - ci_dpm_powergate_uvd(adev, false);
> + ci_dpm_powergate_uvd(adev, true);
> 
>   if (!amdgpu_ci_is_smc_running(adev))
>   return;
> @@ -6036,7 +6036,7 @@ static int ci_dpm_init(struct amdgpu_device *adev)
> 
>   pi->caps_dynamic_ac_timing = true;
> 
> - pi->uvd_power_gated = false;
> + pi->uvd_power_gated = true;
> 
>   /* make sure dc limits are valid */
>   if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0)
> ||
> @@ -6179,8 +6179,6 @@ static int ci_dpm_late_init(void *handle)
>   if (ret)
>   return ret;
> 
> - ci_dpm_powergate_uvd(adev, true);
> -
>   return 0;
>  }
> 
> --
> 1.9.1
> 
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


[PATCH] drm/amdgpu: refine uvd gate logic for CI.

2016-08-24 Thread Rex Zhu
uvd dpm will be controlled by uvd.
dpm just disable uvd dpm in case of suspend when play video.
due to the new logic of uvd_begin_use/end_use,
if disable uvd dpm in late init, will have no chance to
enable uvd dpm after resume until play video again.

Change-Id: I14792383ed50c0465699cdda7f1bad2ea144b861
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index a0d63a2..1d8c375 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -5396,7 +5396,7 @@ static void ci_dpm_disable(struct amdgpu_device *adev)
amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
   AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
 
-   ci_dpm_powergate_uvd(adev, false);
+   ci_dpm_powergate_uvd(adev, true);
 
if (!amdgpu_ci_is_smc_running(adev))
return;
@@ -6036,7 +6036,7 @@ static int ci_dpm_init(struct amdgpu_device *adev)
 
pi->caps_dynamic_ac_timing = true;
 
-   pi->uvd_power_gated = false;
+   pi->uvd_power_gated = true;
 
/* make sure dc limits are valid */
if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
@@ -6179,8 +6179,6 @@ static int ci_dpm_late_init(void *handle)
if (ret)
return ret;
 
-   ci_dpm_powergate_uvd(adev, true);
-
return 0;
 }
 
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx