subject:"\[PATCH\] drm\/amdgpu\: update IP count INFO query"

Re: [PATCH] drm/amdgpu: update IP count INFO query

2023-09-15 Thread Deucher, Alexander

[AMD Official Use Only - General]

For jpeg, if the rings actually represent independent JPEG engines, we probably 
want to expose adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings.

Alex

From: Sundararaju, Sathishkumar 
Sent: Thursday, September 14, 2023 12:00 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Koenig, Christian 
; Liu, Leo ; Sundararaju, 
Sathishkumar 
Subject: [PATCH] drm/amdgpu: update IP count INFO query

update the query to return the number of functional
instances where there is more than an instance of the requested
type and for others continue to return one.

Signed-off-by: Sathishkumar S 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 90 +
 1 file changed, 61 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 3a48bec10aea..9521fa7a1bf9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -200,6 +200,44 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, 
unsigned long flags)
 return r;
 }

+static enum amd_ip_block_type amdgpu_ip_get_block_type(
+   struct amdgpu_device *adev, uint32_t ip)
+{
+   enum amd_ip_block_type type;
+
+   switch (ip) {
+   case AMDGPU_HW_IP_GFX:
+   type = AMD_IP_BLOCK_TYPE_GFX;
+   break;
+   case AMDGPU_HW_IP_COMPUTE:
+   type = AMD_IP_BLOCK_TYPE_GFX;
+   break;
+   case AMDGPU_HW_IP_DMA:
+   type = AMD_IP_BLOCK_TYPE_SDMA;
+   break;
+   case AMDGPU_HW_IP_UVD:
+   case AMDGPU_HW_IP_UVD_ENC:
+   type = AMD_IP_BLOCK_TYPE_UVD;
+   break;
+   case AMDGPU_HW_IP_VCE:
+   type = AMD_IP_BLOCK_TYPE_VCE;
+   break;
+   case AMDGPU_HW_IP_VCN_DEC:
+   case AMDGPU_HW_IP_VCN_ENC:
+   type = AMD_IP_BLOCK_TYPE_VCN;
+   break;
+   case AMDGPU_HW_IP_VCN_JPEG:
+   type = (amdgpu_device_ip_get_ip_block(adev, 
AMD_IP_BLOCK_TYPE_JPEG)) ?
+  AMD_IP_BLOCK_TYPE_JPEG : 
AMD_IP_BLOCK_TYPE_VCN;
+   break;
+   default:
+   type = AMD_IP_BLOCK_TYPE_NUM;
+   break;
+   }
+
+   return type;
+}
+
 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 struct drm_amdgpu_query_fw *query_fw,
 struct amdgpu_device *adev)
@@ -592,45 +630,39 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
 }
 case AMDGPU_INFO_HW_IP_COUNT: {
 enum amd_ip_block_type type;
+   struct amdgpu_ip_block *ip_block = NULL;
 uint32_t count = 0;

-   switch (info->query_hw_ip.type) {
-   case AMDGPU_HW_IP_GFX:
-   type = AMD_IP_BLOCK_TYPE_GFX;
-   break;
-   case AMDGPU_HW_IP_COMPUTE:
-   type = AMD_IP_BLOCK_TYPE_GFX;
-   break;
-   case AMDGPU_HW_IP_DMA:
-   type = AMD_IP_BLOCK_TYPE_SDMA;
-   break;
-   case AMDGPU_HW_IP_UVD:
-   type = AMD_IP_BLOCK_TYPE_UVD;
+   type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type);
+   ip_block = amdgpu_device_ip_get_ip_block(adev, type);
+   if (!ip_block || !ip_block->status.valid)
+   return -EINVAL;
+
+   switch (type) {
+   case AMD_IP_BLOCK_TYPE_GFX:
+   case AMD_IP_BLOCK_TYPE_VCE:
+   count = 1;
 break;
-   case AMDGPU_HW_IP_VCE:
-   type = AMD_IP_BLOCK_TYPE_VCE;
+   case AMD_IP_BLOCK_TYPE_SDMA:
+   count = adev->sdma.num_instances;
 break;
-   case AMDGPU_HW_IP_UVD_ENC:
-   type = AMD_IP_BLOCK_TYPE_UVD;
+   case AMD_IP_BLOCK_TYPE_JPEG:
+   count = adev->jpeg.num_jpeg_inst;
 break;
-   case AMDGPU_HW_IP_VCN_DEC:
-   case AMDGPU_HW_IP_VCN_ENC:
-   type = AMD_IP_BLOCK_TYPE_VCN;
+   case AMD_IP_BLOCK_TYPE_VCN:
+   count = adev->vcn.num_vcn_inst;
 break;
-   case AMDGPU_HW_IP_VCN_JPEG:
-   type = (amdgpu_device_ip_get_ip_block(adev, 
AMD_IP_BLOCK_TYPE_JPEG)) ?
-   AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
+   case AMD_IP_BLOCK_TYPE_UVD:
+   count = adev->uvd.num_uvd_inst;
 break;
+   /* For all other IP block types not list

RE: [PATCH] drm/amdgpu: update IP count INFO query

2023-09-15 Thread Liu, Leo

[AMD Official Use Only - General]

Reviewed-by: Leo Liu 

-Original Message-
From: Sundararaju, Sathishkumar 
Sent: Thursday, September 14, 2023 12:01 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian 
; Liu, Leo ; Sundararaju, 
Sathishkumar 
Subject: [PATCH] drm/amdgpu: update IP count INFO query

update the query to return the number of functional instances where there is 
more than an instance of the requested type and for others continue to return 
one.

Signed-off-by: Sathishkumar S 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 90 +
 1 file changed, 61 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 3a48bec10aea..9521fa7a1bf9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -200,6 +200,44 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, 
unsigned long flags)
return r;
 }

+static enum amd_ip_block_type amdgpu_ip_get_block_type(
+   struct amdgpu_device *adev, uint32_t ip) {
+   enum amd_ip_block_type type;
+
+   switch (ip) {
+   case AMDGPU_HW_IP_GFX:
+   type = AMD_IP_BLOCK_TYPE_GFX;
+   break;
+   case AMDGPU_HW_IP_COMPUTE:
+   type = AMD_IP_BLOCK_TYPE_GFX;
+   break;
+   case AMDGPU_HW_IP_DMA:
+   type = AMD_IP_BLOCK_TYPE_SDMA;
+   break;
+   case AMDGPU_HW_IP_UVD:
+   case AMDGPU_HW_IP_UVD_ENC:
+   type = AMD_IP_BLOCK_TYPE_UVD;
+   break;
+   case AMDGPU_HW_IP_VCE:
+   type = AMD_IP_BLOCK_TYPE_VCE;
+   break;
+   case AMDGPU_HW_IP_VCN_DEC:
+   case AMDGPU_HW_IP_VCN_ENC:
+   type = AMD_IP_BLOCK_TYPE_VCN;
+   break;
+   case AMDGPU_HW_IP_VCN_JPEG:
+   type = (amdgpu_device_ip_get_ip_block(adev, 
AMD_IP_BLOCK_TYPE_JPEG)) ?
+  AMD_IP_BLOCK_TYPE_JPEG : 
AMD_IP_BLOCK_TYPE_VCN;
+   break;
+   default:
+   type = AMD_IP_BLOCK_TYPE_NUM;
+   break;
+   }
+
+   return type;
+}
+
 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
struct drm_amdgpu_query_fw *query_fw,
struct amdgpu_device *adev)
@@ -592,45 +630,39 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
}
case AMDGPU_INFO_HW_IP_COUNT: {
enum amd_ip_block_type type;
+   struct amdgpu_ip_block *ip_block = NULL;
uint32_t count = 0;

-   switch (info->query_hw_ip.type) {
-   case AMDGPU_HW_IP_GFX:
-   type = AMD_IP_BLOCK_TYPE_GFX;
-   break;
-   case AMDGPU_HW_IP_COMPUTE:
-   type = AMD_IP_BLOCK_TYPE_GFX;
-   break;
-   case AMDGPU_HW_IP_DMA:
-   type = AMD_IP_BLOCK_TYPE_SDMA;
-   break;
-   case AMDGPU_HW_IP_UVD:
-   type = AMD_IP_BLOCK_TYPE_UVD;
+   type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type);
+   ip_block = amdgpu_device_ip_get_ip_block(adev, type);
+   if (!ip_block || !ip_block->status.valid)
+   return -EINVAL;
+
+   switch (type) {
+   case AMD_IP_BLOCK_TYPE_GFX:
+   case AMD_IP_BLOCK_TYPE_VCE:
+   count = 1;
break;
-   case AMDGPU_HW_IP_VCE:
-   type = AMD_IP_BLOCK_TYPE_VCE;
+   case AMD_IP_BLOCK_TYPE_SDMA:
+   count = adev->sdma.num_instances;
break;
-   case AMDGPU_HW_IP_UVD_ENC:
-   type = AMD_IP_BLOCK_TYPE_UVD;
+   case AMD_IP_BLOCK_TYPE_JPEG:
+   count = adev->jpeg.num_jpeg_inst;
break;
-   case AMDGPU_HW_IP_VCN_DEC:
-   case AMDGPU_HW_IP_VCN_ENC:
-   type = AMD_IP_BLOCK_TYPE_VCN;
+   case AMD_IP_BLOCK_TYPE_VCN:
+   count = adev->vcn.num_vcn_inst;
break;
-   case AMDGPU_HW_IP_VCN_JPEG:
-   type = (amdgpu_device_ip_get_ip_block(adev, 
AMD_IP_BLOCK_TYPE_JPEG)) ?
-   AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
+   case AMD_IP_BLOCK_TYPE_UVD:
+   count = adev->uvd.num_uvd_inst;
break;
+   /* For all other IP block types not listed in the switch 
statement
+* the ip status is valid here and the instance count is one.
+*/
default:
-

[PATCH] drm/amdgpu: update IP count INFO query

2023-09-14 Thread Sathishkumar S

update the query to return the number of functional
instances where there is more than an instance of the requested
type and for others continue to return one.

Signed-off-by: Sathishkumar S 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 90 +
 1 file changed, 61 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 3a48bec10aea..9521fa7a1bf9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -200,6 +200,44 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, 
unsigned long flags)
return r;
 }
 
+static enum amd_ip_block_type amdgpu_ip_get_block_type(
+   struct amdgpu_device *adev, uint32_t ip)
+{
+   enum amd_ip_block_type type;
+
+   switch (ip) {
+   case AMDGPU_HW_IP_GFX:
+   type = AMD_IP_BLOCK_TYPE_GFX;
+   break;
+   case AMDGPU_HW_IP_COMPUTE:
+   type = AMD_IP_BLOCK_TYPE_GFX;
+   break;
+   case AMDGPU_HW_IP_DMA:
+   type = AMD_IP_BLOCK_TYPE_SDMA;
+   break;
+   case AMDGPU_HW_IP_UVD:
+   case AMDGPU_HW_IP_UVD_ENC:
+   type = AMD_IP_BLOCK_TYPE_UVD;
+   break;
+   case AMDGPU_HW_IP_VCE:
+   type = AMD_IP_BLOCK_TYPE_VCE;
+   break;
+   case AMDGPU_HW_IP_VCN_DEC:
+   case AMDGPU_HW_IP_VCN_ENC:
+   type = AMD_IP_BLOCK_TYPE_VCN;
+   break;
+   case AMDGPU_HW_IP_VCN_JPEG:
+   type = (amdgpu_device_ip_get_ip_block(adev, 
AMD_IP_BLOCK_TYPE_JPEG)) ?
+  AMD_IP_BLOCK_TYPE_JPEG : 
AMD_IP_BLOCK_TYPE_VCN;
+   break;
+   default:
+   type = AMD_IP_BLOCK_TYPE_NUM;
+   break;
+   }
+
+   return type;
+}
+
 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
struct drm_amdgpu_query_fw *query_fw,
struct amdgpu_device *adev)
@@ -592,45 +630,39 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
}
case AMDGPU_INFO_HW_IP_COUNT: {
enum amd_ip_block_type type;
+   struct amdgpu_ip_block *ip_block = NULL;
uint32_t count = 0;
 
-   switch (info->query_hw_ip.type) {
-   case AMDGPU_HW_IP_GFX:
-   type = AMD_IP_BLOCK_TYPE_GFX;
-   break;
-   case AMDGPU_HW_IP_COMPUTE:
-   type = AMD_IP_BLOCK_TYPE_GFX;
-   break;
-   case AMDGPU_HW_IP_DMA:
-   type = AMD_IP_BLOCK_TYPE_SDMA;
-   break;
-   case AMDGPU_HW_IP_UVD:
-   type = AMD_IP_BLOCK_TYPE_UVD;
+   type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type);
+   ip_block = amdgpu_device_ip_get_ip_block(adev, type);
+   if (!ip_block || !ip_block->status.valid)
+   return -EINVAL;
+
+   switch (type) {
+   case AMD_IP_BLOCK_TYPE_GFX:
+   case AMD_IP_BLOCK_TYPE_VCE:
+   count = 1;
break;
-   case AMDGPU_HW_IP_VCE:
-   type = AMD_IP_BLOCK_TYPE_VCE;
+   case AMD_IP_BLOCK_TYPE_SDMA:
+   count = adev->sdma.num_instances;
break;
-   case AMDGPU_HW_IP_UVD_ENC:
-   type = AMD_IP_BLOCK_TYPE_UVD;
+   case AMD_IP_BLOCK_TYPE_JPEG:
+   count = adev->jpeg.num_jpeg_inst;
break;
-   case AMDGPU_HW_IP_VCN_DEC:
-   case AMDGPU_HW_IP_VCN_ENC:
-   type = AMD_IP_BLOCK_TYPE_VCN;
+   case AMD_IP_BLOCK_TYPE_VCN:
+   count = adev->vcn.num_vcn_inst;
break;
-   case AMDGPU_HW_IP_VCN_JPEG:
-   type = (amdgpu_device_ip_get_ip_block(adev, 
AMD_IP_BLOCK_TYPE_JPEG)) ?
-   AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
+   case AMD_IP_BLOCK_TYPE_UVD:
+   count = adev->uvd.num_uvd_inst;
break;
+   /* For all other IP block types not listed in the switch 
statement
+* the ip status is valid here and the instance count is one.
+*/
default:
-   return -EINVAL;
+   count = 1;
+   break;
}
 
-   for (i = 0; i < adev->num_ip_blocks; i++)
-   if (adev->ip_blocks[i].version->type == type &&
-   adev->ip_blocks[i].status.valid &&
-   count < AMDGPU_HW_IP_INSTANCE_

Re: [PATCH] drm/amdgpu: update IP count INFO query

RE: [PATCH] drm/amdgpu: update IP count INFO query

[PATCH] drm/amdgpu: update IP count INFO query

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