subject:"\[PATCH\] drm\/amdkfd\: correct the cache info for gfx1036"

Re: [PATCH] drm/amdkfd: correct the cache info for gfx1036

2022-10-21 Thread Alex Deucher

It looks like this patch never landed.

Alex

On Tue, Oct 11, 2022 at 9:48 PM Zhang, Yifan  wrote:
>
> [Public]
>
>
>
> This patch is
>
>
>
> Reviewed-by: Yifan Zhang 
>
>
>
> From: Zhang, Jesse(Jie) 
> Sent: Tuesday, October 11, 2022 1:23 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan 
> ; Kuehling, Felix 
> Subject: RE: [PATCH] drm/amdkfd: correct the cache info for gfx1036
>
>
>
> [AMD Official Use Only - General]
>
>
>
>
>
>correct the cache information for gfx1036
>
>
>
> Signed-off-by: Yifan Zhang yifan1.zh...@amd.com
>
>
>
> Signed-off-by: jie1zhan jesse.zh...@amd.com
>
> Change-Id: I60e754737057c144e69a6511ba6ddfca472ca7a1
>
>
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
>
> index 477a30981c1b..d25ac9cbe5b2 100644
>
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
>
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
>
> @@ -795,6 +795,54 @@ static struct kfd_gpu_cache_info 
> yellow_carp_cache_info[] = {
>
> },
>
> };
>
>
>
> +static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = {
>
> +   {
>
> +   /* TCP L1 Cache per CU */
>
> +   .cache_size = 16,
>
> +   .cache_level = 1,
>
> +   .flags = (CRAT_CACHE_FLAGS_ENABLED |
>
> +   CRAT_CACHE_FLAGS_DATA_CACHE |
>
> +   CRAT_CACHE_FLAGS_SIMD_CACHE),
>
> +   .num_cu_shared = 1,
>
> +   },
>
> +   {
>
> +   /* Scalar L1 Instruction Cache per SQC */
>
> +   .cache_size = 32,
>
> +   .cache_level = 1,
>
> +   .flags = (CRAT_CACHE_FLAGS_ENABLED |
>
> +   CRAT_CACHE_FLAGS_INST_CACHE |
>
> +   CRAT_CACHE_FLAGS_SIMD_CACHE),
>
> +   .num_cu_shared = 2,
>
> +   },
>
> +   {
>
> +   /* Scalar L1 Data Cache per SQC */
>
> +   .cache_size = 16,
>
> +   .cache_level = 1,
>
> +   .flags = (CRAT_CACHE_FLAGS_ENABLED |
>
> +   CRAT_CACHE_FLAGS_DATA_CACHE |
>
> +   CRAT_CACHE_FLAGS_SIMD_CACHE),
>
> +   .num_cu_shared = 2,
>
> +   },
>
> +   {
>
> +   /* GL1 Data Cache per SA */
>
> +   .cache_size = 128,
>
> +   .cache_level = 1,
>
> +   .flags = (CRAT_CACHE_FLAGS_ENABLED |
>
> +   CRAT_CACHE_FLAGS_DATA_CACHE |
>
> +   CRAT_CACHE_FLAGS_SIMD_CACHE),
>
> +   .num_cu_shared = 2,
>
> +   },
>
> +   {
>
> +   /* L2 Data Cache per GPU (Total Tex Cache) */
>
> +   .cache_size = 256,
>
> +   .cache_level = 2,
>
> +   .flags = (CRAT_CACHE_FLAGS_ENABLED |
>
> +   CRAT_CACHE_FLAGS_DATA_CACHE |
>
> +   CRAT_CACHE_FLAGS_SIMD_CACHE),
>
> +   .num_cu_shared = 2,
>
> +   },
>
> +};
>
> +
>
> static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
>
> struct crat_subtype_computeunit *cu)
>
> {
>
> @@ -1514,11 +1562,14 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev 
> *kdev,
>
> num_of_cache_types = 
> ARRAY_SIZE(beige_goby_cache_info);
>
> break;
>
> case IP_VERSION(10, 3, 3):
>
> -   case IP_VERSION(10, 3, 6): /* TODO: Double check these on 
> production silicon */
>
> case IP_VERSION(10, 3, 7): /* TODO: Double check these on 
> production silicon */
>
> pcache_info = yellow_carp_cache_info;
>
> num_of_cache_types = 
> ARRAY_SIZE(yellow_carp_cache_info);
>
> break;
>
> +   case IP_VERSION(10, 3, 6):
>
> +   pcache_info = gc_10_3_6_cache_info;
>
> +   num_of_cache_types = ARRAY_SIZE(gc_10_3_6_cache_info);
>
> +   break;
>
> case IP_VERSION(11, 0, 0):

RE: [PATCH] drm/amdkfd: correct the cache info for gfx1036

2022-10-11 Thread Zhang, Yifan

[Public]

This patch is

Reviewed-by: Yifan Zhang 

From: Zhang, Jesse(Jie) 
Sent: Tuesday, October 11, 2022 1:23 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan 
; Kuehling, Felix 
Subject: RE: [PATCH] drm/amdkfd: correct the cache info for gfx1036


[AMD Official Use Only - General]



   correct the cache information for gfx1036



Signed-off-by: Yifan Zhang yifan1.zh...@amd.com<mailto:yifan1.zh...@amd.com>



Signed-off-by: jie1zhan jesse.zh...@amd.com<mailto:jesse.zh...@amd.com>

Change-Id: I60e754737057c144e69a6511ba6ddfca472ca7a1



diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c

index 477a30981c1b..d25ac9cbe5b2 100644

--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c

+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c

@@ -795,6 +795,54 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] 
= {

},

};



+static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = {

+   {

+   /* TCP L1 Cache per CU */

+   .cache_size = 16,

+   .cache_level = 1,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_DATA_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 1,

+   },

+   {

+   /* Scalar L1 Instruction Cache per SQC */

+   .cache_size = 32,

+   .cache_level = 1,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_INST_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 2,

+   },

+   {

+   /* Scalar L1 Data Cache per SQC */

+   .cache_size = 16,

+   .cache_level = 1,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_DATA_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 2,

+   },

+   {

+   /* GL1 Data Cache per SA */

+   .cache_size = 128,

+   .cache_level = 1,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_DATA_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 2,

+   },

+   {

+   /* L2 Data Cache per GPU (Total Tex Cache) */

+   .cache_size = 256,

+   .cache_level = 2,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_DATA_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 2,

+   },

+};

+

static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,

struct crat_subtype_computeunit *cu)

{

@@ -1514,11 +1562,14 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,

num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);

break;

case IP_VERSION(10, 3, 3):

-   case IP_VERSION(10, 3, 6): /* TODO: Double check these on 
production silicon */

case IP_VERSION(10, 3, 7): /* TODO: Double check these on 
production silicon */

pcache_info = yellow_carp_cache_info;

num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);

break;

+   case IP_VERSION(10, 3, 6):

+   pcache_info = gc_10_3_6_cache_info;

+   num_of_cache_types = ARRAY_SIZE(gc_10_3_6_cache_info);

+   break;

case IP_VERSION(11, 0, 0):

Re: [PATCH] drm/amdkfd: correct the cache info for gfx1036

2022-10-11 Thread Deucher, Alexander

[Public]

Acked-by: Alex Deucher 

From: Zhang, Jesse(Jie) 
Sent: Tuesday, October 11, 2022 1:23 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Zhang, Yifan 
; Kuehling, Felix 
Subject: RE: [PATCH] drm/amdkfd: correct the cache info for gfx1036


[AMD Official Use Only - General]





   correct the cache information for gfx1036



Signed-off-by: Yifan Zhang yifan1.zh...@amd.com<mailto:yifan1.zh...@amd.com>



Signed-off-by: jie1zhan jesse.zh...@amd.com<mailto:jesse.zh...@amd.com>

Change-Id: I60e754737057c144e69a6511ba6ddfca472ca7a1



diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c

index 477a30981c1b..d25ac9cbe5b2 100644

--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c

+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c

@@ -795,6 +795,54 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] 
= {

},

};



+static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = {

+   {

+   /* TCP L1 Cache per CU */

+   .cache_size = 16,

+   .cache_level = 1,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_DATA_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 1,

+   },

+   {

+   /* Scalar L1 Instruction Cache per SQC */

+   .cache_size = 32,

+   .cache_level = 1,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_INST_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 2,

+   },

+   {

+   /* Scalar L1 Data Cache per SQC */

+   .cache_size = 16,

+   .cache_level = 1,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_DATA_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 2,

+   },

+   {

+   /* GL1 Data Cache per SA */

+   .cache_size = 128,

+   .cache_level = 1,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_DATA_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 2,

+   },

+   {

+   /* L2 Data Cache per GPU (Total Tex Cache) */

+   .cache_size = 256,

+   .cache_level = 2,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_DATA_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 2,

+   },

+};

+

static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,

struct crat_subtype_computeunit *cu)

{

@@ -1514,11 +1562,14 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,

num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);

break;

case IP_VERSION(10, 3, 3):

-   case IP_VERSION(10, 3, 6): /* TODO: Double check these on 
production silicon */

case IP_VERSION(10, 3, 7): /* TODO: Double check these on 
production silicon */

pcache_info = yellow_carp_cache_info;

num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);

break;

+   case IP_VERSION(10, 3, 6):

+   pcache_info = gc_10_3_6_cache_info;

+   num_of_cache_types = ARRAY_SIZE(gc_10_3_6_cache_info);

+   break;

case IP_VERSION(11, 0, 0):

RE: [PATCH] drm/amdkfd: correct the cache info for gfx1036

2022-10-10 Thread Zhang, Jesse(Jie)

[AMD Official Use Only - General]



   correct the cache information for gfx1036



Signed-off-by: Yifan Zhang yifan1.zh...@amd.com



Signed-off-by: jie1zhan jesse.zh...@amd.com

Change-Id: I60e754737057c144e69a6511ba6ddfca472ca7a1



diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c

index 477a30981c1b..d25ac9cbe5b2 100644

--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c

+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c

@@ -795,6 +795,54 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] 
= {

},

};



+static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = {

+   {

+   /* TCP L1 Cache per CU */

+   .cache_size = 16,

+   .cache_level = 1,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_DATA_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 1,

+   },

+   {

+   /* Scalar L1 Instruction Cache per SQC */

+   .cache_size = 32,

+   .cache_level = 1,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_INST_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 2,

+   },

+   {

+   /* Scalar L1 Data Cache per SQC */

+   .cache_size = 16,

+   .cache_level = 1,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_DATA_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 2,

+   },

+   {

+   /* GL1 Data Cache per SA */

+   .cache_size = 128,

+   .cache_level = 1,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_DATA_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 2,

+   },

+   {

+   /* L2 Data Cache per GPU (Total Tex Cache) */

+   .cache_size = 256,

+   .cache_level = 2,

+   .flags = (CRAT_CACHE_FLAGS_ENABLED |

+   CRAT_CACHE_FLAGS_DATA_CACHE |

+   CRAT_CACHE_FLAGS_SIMD_CACHE),

+   .num_cu_shared = 2,

+   },

+};

+

static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,

struct crat_subtype_computeunit *cu)

{

@@ -1514,11 +1562,14 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,

num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);

break;

case IP_VERSION(10, 3, 3):

-   case IP_VERSION(10, 3, 6): /* TODO: Double check these on 
production silicon */

case IP_VERSION(10, 3, 7): /* TODO: Double check these on 
production silicon */

pcache_info = yellow_carp_cache_info;

num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);

break;

+   case IP_VERSION(10, 3, 6):

+   pcache_info = gc_10_3_6_cache_info;

+   num_of_cache_types = ARRAY_SIZE(gc_10_3_6_cache_info);

+   break;

case IP_VERSION(11, 0, 0):

Re: [PATCH] drm/amdkfd: correct the cache info for gfx1036

RE: [PATCH] drm/amdkfd: correct the cache info for gfx1036

Re: [PATCH] drm/amdkfd: correct the cache info for gfx1036

RE: [PATCH] drm/amdkfd: correct the cache info for gfx1036

4 matches

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