From: Charlene Liu <charlene....@amd.com>

[why]
fix NULL pointer in irq_service_dcn201

[how]
initialize proper num of irq source for linu

Reviewed-by: Sung joon Kim <USER DID NOT SET AN EMAIL>
Acked-by: Solomon Chiu <solomon.c...@amd.com>
Signed-off-by: Charlene Liu <charlene....@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h            |  1 +
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h |  9 +++++----
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h   |  1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c  | 17 ++++++++++-------
 4 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 8cc9626fc111..c5a091d0bbfc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -899,6 +899,7 @@ union surface_update_flags {
                uint32_t bandwidth_change:1;
                uint32_t clock_change:1;
                uint32_t stereo_format_change:1;
+               uint32_t lut_3d:1;
                uint32_t full_update:1;
        } bits;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 296b2f80a1ec..307369b52b42 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -663,14 +663,15 @@ struct dce_hwseq_registers {
        uint32_t MC_VM_XGMI_LFB_CNTL;
        uint32_t AZALIA_AUDIO_DTO;
        uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
+       /* MMHUB VM */
+       uint32_t MC_VM_FB_LOCATION_BASE;
+       uint32_t MC_VM_FB_LOCATION_TOP;
+       uint32_t MC_VM_FB_OFFSET;
+       uint32_t MMHUBBUB_MEM_PWR_CNTL;
        uint32_t HPO_TOP_CLOCK_CONTROL;
        uint32_t ODM_MEM_PWR_CTRL3;
        uint32_t DMU_MEM_PWR_CNTL;
-       uint32_t MMHUBBUB_MEM_PWR_CNTL;
        uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
-       uint32_t MC_VM_FB_LOCATION_BASE;
-       uint32_t MC_VM_FB_LOCATION_TOP;
-       uint32_t MC_VM_FB_OFFSET;
 };
  /* set field name */
 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
index bf1ffc3629c7..3d9be87aae45 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
@@ -111,6 +111,7 @@ enum dce110_opp_reg_type {
        OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
        OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
        OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
+       OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
        OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
        OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
        OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index fb0dec4ed3a6..0f273ac0c83f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -256,16 +256,19 @@ struct abm *dmub_abm_create(
        const struct dce_abm_shift *abm_shift,
        const struct dce_abm_mask *abm_mask)
 {
-       struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
+       if (!ctx->dc->config.disable_dmcu) {
+               struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
 
-       if (abm_dce == NULL) {
-               BREAK_TO_DEBUGGER();
-               return NULL;
-       }
+               if (abm_dce == NULL) {
+                       BREAK_TO_DEBUGGER();
+                       return NULL;
+               }
 
-       dmub_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask);
+               dmub_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask);
 
-       return &abm_dce->base;
+               return &abm_dce->base;
+       }
+       return NULL;
 }
 
 void dmub_abm_destroy(struct abm **abm)
-- 
2.25.1

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