From: Aric Cyr <aric....@amd.com>
This reverts commit bea6beb76a9f19a9a86d24d304f27b3cff5f1791
as it causes crash on driver load in some scenarios.
Signed-off-by: Aric Cyr <aric....@amd.com>
Reviewed-by: Martin Leung <martin.le...@amd.com>
Acked-by: Solomon Chiu <solomon.c...@amd.com>
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 48 +------------------
drivers/gpu/drm/amd/display/dc/dc.h | 2 -
2 files changed, 2 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 3946d12e9fb1..01b1853b7750 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -761,43 +761,6 @@ static struct wm_table ddr4_wm_table_rn = {
}
};
-static struct wm_table ddr4_1R_wm_table_rn = {
- .entries = {
- {
- .wm_inst = WM_A,
- .wm_type = WM_TYPE_PSTATE_CHG,
- .pstate_latency_us = 11.72,
- .sr_exit_time_us = 13.90,
- .sr_enter_plus_exit_time_us = 14.80,
- .valid = true,
- },
- {
- .wm_inst = WM_B,
- .wm_type = WM_TYPE_PSTATE_CHG,
- .pstate_latency_us = 11.72,
- .sr_exit_time_us = 13.90,
- .sr_enter_plus_exit_time_us = 14.80,
- .valid = true,
- },
- {
- .wm_inst = WM_C,
- .wm_type = WM_TYPE_PSTATE_CHG,
- .pstate_latency_us = 11.72,
- .sr_exit_time_us = 13.90,
- .sr_enter_plus_exit_time_us = 14.80,
- .valid = true,
- },
- {
- .wm_inst = WM_D,
- .wm_type = WM_TYPE_PSTATE_CHG,
- .pstate_latency_us = 11.72,
- .sr_exit_time_us = 13.90,
- .sr_enter_plus_exit_time_us = 14.80,
- .valid = true,
- },
- }
-};
-
static struct wm_table lpddr4_wm_table_rn = {
.entries = {
{
@@ -969,12 +932,8 @@ void rn_clk_mgr_construct(
} else {
if (is_green_sardine)
rn_bw_params.wm_table = ddr4_wm_table_gs;
- else {
- if (ctx->dc->config.is_single_rank_dimm)
- rn_bw_params.wm_table =
ddr4_1R_wm_table_rn;
- else
- rn_bw_params.wm_table =
ddr4_wm_table_rn;
- }
+ else
+ rn_bw_params.wm_table = ddr4_wm_table_rn;
}
/* Saved clocks configured at boot for debug purposes */
rn_dump_clk_registers(&clk_mgr->base.boot_snapshot,
&clk_mgr->base, &log_info);
@@ -992,9 +951,6 @@ void rn_clk_mgr_construct(
if (status == PP_SMU_RESULT_OK &&
ctx->dc_bios && ctx->dc_bios->integrated_info) {
rn_clk_mgr_helper_populate_bw_params
(clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
- /* treat memory config as single channel if memory is
asymmetrics. */
- if (ctx->dc->config.is_asymmetric_memory)
- clk_mgr->base.bw_params->num_channels = 1;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 153093abafbd..2088508dac1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -307,8 +307,6 @@ struct dc_config {
#endif
uint64_t vblank_alignment_dto_params;
uint8_t vblank_alignment_max_frame_time_diff;
- bool is_asymmetric_memory;
- bool is_single_rank_dimm;
};
enum visual_confirm {
--
2.29.0
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