Re: [PATCH 06/13] drm/amd/powerplay: revise clock level setup
On Tue, Jun 19, 2018 at 3:38 AM, Evan Quan wrote:
> Make sure the clock level set only on dpm enabled. Also uvd/vce/soc
> clock also changed correspondingly.
>
> Change-Id: I1db2e2ac355fd5aea1c0a25c2b140d039a590089
> Signed-off-by: Evan Quan
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 318
> ++---
> 1 file changed, 211 insertions(+), 107 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index ea530af..a124b81 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -958,76 +958,172 @@ static uint32_t vega12_find_lowest_dpm_level(
> break;
> }
>
> + if (i >= table->count) {
> + i = 0;
> + table->dpm_levels[i].enabled = true;
> + }
> +
> return i;
> }
>
> static uint32_t vega12_find_highest_dpm_level(
> struct vega12_single_dpm_table *table)
> {
> - uint32_t i = 0;
> + int32_t i = 0;
> + PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
> + "[FindHighestDPMLevel] DPM Table has too many
> entries!",
> + return MAX_REGULAR_DPM_NUMBER - 1);
>
> - if (table->count <= MAX_REGULAR_DPM_NUMBER) {
> - for (i = table->count; i > 0; i--) {
> - if (table->dpm_levels[i - 1].enabled)
> - return i - 1;
> - }
> - } else {
> - pr_info("DPM Table Has Too Many Entries!");
> - return MAX_REGULAR_DPM_NUMBER - 1;
> + for (i = table->count - 1; i >= 0; i--) {
> + if (table->dpm_levels[i].enabled)
> + break;
> }
>
> - return i;
> + if (i < 0) {
> + i = 0;
> + table->dpm_levels[i].enabled = true;
> + }
> +
> + return (uint32_t)i;
> }
>
> static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
> {
> struct vega12_hwmgr *data = hwmgr->backend;
> - if (data->smc_state_table.gfx_boot_level !=
> - data->dpm_table.gfx_table.dpm_state.soft_min_level) {
> - smum_send_msg_to_smc_with_parameter(hwmgr,
> - PPSMC_MSG_SetSoftMinByFreq,
> - PPCLK_GFXCLK<<16 |
> data->dpm_table.gfx_table.dpm_levels[data->smc_state_table.gfx_boot_level].value);
> - data->dpm_table.gfx_table.dpm_state.soft_min_level =
> - data->smc_state_table.gfx_boot_level;
> + uint32_t min_freq;
> + int ret = 0;
> +
> + if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
> + min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
> + PP_ASSERT_WITH_CODE(!(ret =
> smum_send_msg_to_smc_with_parameter(
> + hwmgr, PPSMC_MSG_SetSoftMinByFreq,
> + (PPCLK_GFXCLK << 16) | (min_freq &
> 0x))),
> + "Failed to set soft min gfxclk !",
> + return ret);
> }
>
> - if (data->smc_state_table.mem_boot_level !=
> - data->dpm_table.mem_table.dpm_state.soft_min_level) {
> - smum_send_msg_to_smc_with_parameter(hwmgr,
> - PPSMC_MSG_SetSoftMinByFreq,
> - PPCLK_UCLK<<16 |
> data->dpm_table.mem_table.dpm_levels[data->smc_state_table.mem_boot_level].value);
> - data->dpm_table.mem_table.dpm_state.soft_min_level =
> - data->smc_state_table.mem_boot_level;
> + if (data->smu_features[GNLD_DPM_UCLK].enabled) {
> + min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
> + PP_ASSERT_WITH_CODE(!(ret =
> smum_send_msg_to_smc_with_parameter(
> + hwmgr, PPSMC_MSG_SetSoftMinByFreq,
> + (PPCLK_UCLK << 16) | (min_freq &
> 0x))),
> + "Failed to set soft min memclk !",
> + return ret);
> +
> + min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
> + PP_ASSERT_WITH_CODE(!(ret =
> smum_send_msg_to_smc_with_parameter(
> + hwmgr, PPSMC_MSG_SetHardMinByFreq,
> + (PPCLK_UCLK << 16) | (min_freq &
> 0x))),
> + "Failed to set hard min memclk !",
> + return ret);
> }
>
> - return 0;
> + if (data->smu_features[GNLD_DPM_UVD].enabled) {
> + min_freq =
> data->dpm_table.vclk_table.dpm_state.soft_min_level;
> +
> +
[PATCH 06/13] drm/amd/powerplay: revise clock level setup
Make sure the clock level set only on dpm enabled. Also uvd/vce/soc
clock also changed correspondingly.
Change-Id: I1db2e2ac355fd5aea1c0a25c2b140d039a590089
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 318 ++---
1 file changed, 211 insertions(+), 107 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index ea530af..a124b81 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -958,76 +958,172 @@ static uint32_t vega12_find_lowest_dpm_level(
break;
}
+ if (i >= table->count) {
+ i = 0;
+ table->dpm_levels[i].enabled = true;
+ }
+
return i;
}
static uint32_t vega12_find_highest_dpm_level(
struct vega12_single_dpm_table *table)
{
- uint32_t i = 0;
+ int32_t i = 0;
+ PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
+ "[FindHighestDPMLevel] DPM Table has too many entries!",
+ return MAX_REGULAR_DPM_NUMBER - 1);
- if (table->count <= MAX_REGULAR_DPM_NUMBER) {
- for (i = table->count; i > 0; i--) {
- if (table->dpm_levels[i - 1].enabled)
- return i - 1;
- }
- } else {
- pr_info("DPM Table Has Too Many Entries!");
- return MAX_REGULAR_DPM_NUMBER - 1;
+ for (i = table->count - 1; i >= 0; i--) {
+ if (table->dpm_levels[i].enabled)
+ break;
}
- return i;
+ if (i < 0) {
+ i = 0;
+ table->dpm_levels[i].enabled = true;
+ }
+
+ return (uint32_t)i;
}
static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
{
struct vega12_hwmgr *data = hwmgr->backend;
- if (data->smc_state_table.gfx_boot_level !=
- data->dpm_table.gfx_table.dpm_state.soft_min_level) {
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_SetSoftMinByFreq,
- PPCLK_GFXCLK<<16 |
data->dpm_table.gfx_table.dpm_levels[data->smc_state_table.gfx_boot_level].value);
- data->dpm_table.gfx_table.dpm_state.soft_min_level =
- data->smc_state_table.gfx_boot_level;
+ uint32_t min_freq;
+ int ret = 0;
+
+ if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
+ min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+ hwmgr, PPSMC_MSG_SetSoftMinByFreq,
+ (PPCLK_GFXCLK << 16) | (min_freq &
0x))),
+ "Failed to set soft min gfxclk !",
+ return ret);
}
- if (data->smc_state_table.mem_boot_level !=
- data->dpm_table.mem_table.dpm_state.soft_min_level) {
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_SetSoftMinByFreq,
- PPCLK_UCLK<<16 |
data->dpm_table.mem_table.dpm_levels[data->smc_state_table.mem_boot_level].value);
- data->dpm_table.mem_table.dpm_state.soft_min_level =
- data->smc_state_table.mem_boot_level;
+ if (data->smu_features[GNLD_DPM_UCLK].enabled) {
+ min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+ hwmgr, PPSMC_MSG_SetSoftMinByFreq,
+ (PPCLK_UCLK << 16) | (min_freq &
0x))),
+ "Failed to set soft min memclk !",
+ return ret);
+
+ min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+ hwmgr, PPSMC_MSG_SetHardMinByFreq,
+ (PPCLK_UCLK << 16) | (min_freq &
0x))),
+ "Failed to set hard min memclk !",
+ return ret);
}
- return 0;
+ if (data->smu_features[GNLD_DPM_UVD].enabled) {
+ min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
+
+ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+ hwmgr, PPSMC_MSG_SetSoftMinByFreq,
+ (PPCLK_VCLK << 16) | (min_freq &
0x))),
+ "Failed to set soft min v
