From: Monk Liu <monk....@amd.com>
Required for SR-IOV.
Signed-off-by: Monk Liu <monk....@amd.com>
Signed-off-by: Xiangliang Yu <xiangliang...@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index bb93b0a..4704524 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1501,7 +1501,7 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device
*adev)
struct amdgpu_ring *ring;
u32 tmp;
u32 rb_bufsz;
- u64 rb_addr, rptr_addr;
+ u64 rb_addr, rptr_addr, wptr_gpu_addr;
/* Set the write pointer delay */
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY), 0);
@@ -1529,6 +1529,10 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device
*adev)
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR),
lower_32_bits(rptr_addr));
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI),
upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
+ wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
lower_32_bits(wptr_gpu_addr));
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI),
upper_32_bits(wptr_gpu_addr));
+
mdelay(1);
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp);
--
2.5.5
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