Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Thursday, November 14, 2019 12:23 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH 1/2] drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK
>
> So that the setting reflects what the hw supports. This will be used in a
> subsequent patch so needs to be correct.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 7 +++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 57459a65eb44..ad39db49a29d 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -719,6 +719,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
>
> switch (adev->asic_type) {
> case CHIP_VEGA20:
> + adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> vega20_set_ppt_funcs(smu);
> break;
> case CHIP_NAVI10:
> @@ -727,6 +728,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
> navi10_set_ppt_funcs(smu);
> break;
> case CHIP_ARCTURUS:
> + adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> arcturus_set_ppt_funcs(smu);
> /* OD is not supported on Arcturus */
> smu->od_enabled =false;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index a24beaa4fb01..443625c83ec9 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -81,6 +81,8 @@ static void hwmgr_init_workload_prority(struct
> pp_hwmgr *hwmgr)
>
> int hwmgr_early_init(struct pp_hwmgr *hwmgr) {
> + struct amdgpu_device *adev = hwmgr->adev;
> +
> if (!hwmgr)
> return -EINVAL;
>
> @@ -96,6 +98,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>
> switch (hwmgr->chip_family) {
> case AMDGPU_FAMILY_CI:
> + adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> hwmgr->smumgr_funcs = _smu_funcs;
> ci_set_asic_special_caps(hwmgr);
> hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
> @@ -106,12 +109,14 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
> smu7_init_function_pointers(hwmgr);
> break;
> case AMDGPU_FAMILY_CZ:
> + adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> hwmgr->od_enabled = false;
> hwmgr->smumgr_funcs = _smu_funcs;
> hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
> smu8_init_function_pointers(hwmgr);
> break;
> case AMDGPU_FAMILY_VI:
> + adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
> switch (hwmgr->chip_id) {
> case CHIP_TOPAZ:
> @@ -153,6 +158,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
> case AMDGPU_FAMILY_AI:
> switch (hwmgr->chip_id) {
> case CHIP_VEGA10:
> + adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
> hwmgr->smumgr_funcs = _smu_funcs;
> vega10_hwmgr_init(hwmgr);
> @@ -162,6 +168,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
> vega12_hwmgr_init(hwmgr);
> break;
> case CHIP_VEGA20:
> + adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
> hwmgr->smumgr_funcs = _smu_funcs;
> vega20_hwmgr_init(hwmgr);
> --
> 2.23.0
>
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