Re: [PATCH 1/2] drm/amdgpu/psp: keep TMR in visible vram region for SRIOV

2019-08-28 Thread Yin, Tianci (Rico) 
Hi Christian,

Thank you very much for your suggestions!

A little more improvement have made about the patch1, please review again.

BTW, any suggestion about the patch2?

Rico

From: Christian König 
Sent: Wednesday, August 28, 2019 21:09
To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org 

Cc: Xu, Feifei ; Ma, Le ; Xiao, Jack 
; Zhang, Hawking 
Subject: Re: [PATCH 1/2] drm/amdgpu/psp: keep TMR in visible vram region for 
SRIOV

Am 28.08.19 um 13:40 schrieb Tianci Yin:
> From: "Tianci.Yin" 
>
> Fix compute ring test failure in sriov scenario.
>
> Change-Id: I141d3d094e2cba9bcf2f6c96f4d8c4ef43c421c3
> Signed-off-by: Tianci.Yin 

Reviewed-by: Christian König  for both patches.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 15 +++
>   1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 9f7cc5b..43fa8b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -239,6 +239,7 @@ static int psp_tmr_init(struct psp_context *psp)
>   {
>int ret;
>int tmr_size;
> + void *tmr_buf;
>
>/*
> * According to HW engineer, they prefer the TMR address be "naturally
> @@ -261,9 +262,14 @@ static int psp_tmr_init(struct psp_context *psp)
>}
>}
>
> - ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
> -   AMDGPU_GEM_DOMAIN_VRAM,
> -   >tmr_bo, >tmr_mc_addr, NULL);
> + if (!amdgpu_sriov_vf(psp->adev))
> + ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
> +   AMDGPU_GEM_DOMAIN_VRAM,
> +   >tmr_bo, >tmr_mc_addr, 
> NULL);
> + else
> + ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
> +   AMDGPU_GEM_DOMAIN_VRAM,
> +   >tmr_bo, >tmr_mc_addr, 
> _buf);
>
>return ret;
>   }
> @@ -1206,6 +1212,7 @@ static int psp_hw_fini(void *handle)
>   {
>struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>struct psp_context *psp = >psp;
> + void *tmr_buf;
>
>if (adev->gmc.xgmi.num_physical_nodes > 1 &&
>psp->xgmi_context.initialized == 1)
> @@ -1216,7 +1223,7 @@ static int psp_hw_fini(void *handle)
>
>psp_ring_destroy(psp, PSP_RING_TYPE__KM);
>
> - amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, NULL);
> + amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, _buf);
>amdgpu_bo_free_kernel(>fw_pri_bo,
>  >fw_pri_mc_addr, >fw_pri_buf);
>amdgpu_bo_free_kernel(>fence_buf_bo,

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[PATCH 1/2] drm/amdgpu/psp: keep TMR in visible vram region for SRIOV

2019-08-28 Thread Tianci Yin 
From: "Tianci.Yin" 

Fix compute ring test failure in sriov scenario.

Change-Id: I141d3d094e2cba9bcf2f6c96f4d8c4ef43c421c3
Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 9f7cc5b..d11ce86 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -239,6 +239,8 @@ static int psp_tmr_init(struct psp_context *psp)
 {
int ret;
int tmr_size;
+   void *tmr_buf;
+   void **pptr = amdgpu_sriov_vf(psp->adev) ? _buf : NULL;
 
/*
 * According to HW engineer, they prefer the TMR address be "naturally
@@ -263,7 +265,7 @@ static int psp_tmr_init(struct psp_context *psp)
 
ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
  AMDGPU_GEM_DOMAIN_VRAM,
- >tmr_bo, >tmr_mc_addr, NULL);
+ >tmr_bo, >tmr_mc_addr, pptr);
 
return ret;
 }
@@ -1206,6 +1208,8 @@ static int psp_hw_fini(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = >psp;
+   void *tmr_buf;
+   void **pptr = amdgpu_sriov_vf(psp->adev) ? _buf : NULL;
 
if (adev->gmc.xgmi.num_physical_nodes > 1 &&
psp->xgmi_context.initialized == 1)
@@ -1216,7 +1220,7 @@ static int psp_hw_fini(void *handle)
 
psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 
-   amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, NULL);
+   amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, pptr);
amdgpu_bo_free_kernel(>fw_pri_bo,
  >fw_pri_mc_addr, >fw_pri_buf);
amdgpu_bo_free_kernel(>fence_buf_bo,
-- 
2.7.4

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Re: [PATCH 1/2] drm/amdgpu/psp: keep TMR in visible vram region for SRIOV

2019-08-28 Thread Christian König 

Am 28.08.19 um 13:40 schrieb Tianci Yin:

From: "Tianci.Yin" 

Fix compute ring test failure in sriov scenario.

Change-Id: I141d3d094e2cba9bcf2f6c96f4d8c4ef43c421c3
Signed-off-by: Tianci.Yin 


Reviewed-by: Christian König  for both patches.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 15 +++
  1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 9f7cc5b..43fa8b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -239,6 +239,7 @@ static int psp_tmr_init(struct psp_context *psp)
  {
int ret;
int tmr_size;
+   void *tmr_buf;
  
  	/*

 * According to HW engineer, they prefer the TMR address be "naturally
@@ -261,9 +262,14 @@ static int psp_tmr_init(struct psp_context *psp)
}
}
  
-	ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,

- AMDGPU_GEM_DOMAIN_VRAM,
- >tmr_bo, >tmr_mc_addr, NULL);
+   if (!amdgpu_sriov_vf(psp->adev))
+   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ >tmr_bo, >tmr_mc_addr, 
NULL);
+   else
+   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ >tmr_bo, >tmr_mc_addr, 
_buf);
  
  	return ret;

  }
@@ -1206,6 +1212,7 @@ static int psp_hw_fini(void *handle)
  {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = >psp;
+   void *tmr_buf;
  
  	if (adev->gmc.xgmi.num_physical_nodes > 1 &&

psp->xgmi_context.initialized == 1)
@@ -1216,7 +1223,7 @@ static int psp_hw_fini(void *handle)
  
  	psp_ring_destroy(psp, PSP_RING_TYPE__KM);
  
-	amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, NULL);

+   amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, _buf);
amdgpu_bo_free_kernel(>fw_pri_bo,
  >fw_pri_mc_addr, >fw_pri_buf);
amdgpu_bo_free_kernel(>fence_buf_bo,


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[PATCH 1/2] drm/amdgpu/psp: keep TMR in visible vram region for SRIOV

2019-08-28 Thread Tianci Yin 
From: "Tianci.Yin" 

Fix compute ring test failure in sriov scenario.

Change-Id: I141d3d094e2cba9bcf2f6c96f4d8c4ef43c421c3
Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 15 +++
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 9f7cc5b..43fa8b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -239,6 +239,7 @@ static int psp_tmr_init(struct psp_context *psp)
 {
int ret;
int tmr_size;
+   void *tmr_buf;
 
/*
 * According to HW engineer, they prefer the TMR address be "naturally
@@ -261,9 +262,14 @@ static int psp_tmr_init(struct psp_context *psp)
}
}
 
-   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM,
- >tmr_bo, >tmr_mc_addr, NULL);
+   if (!amdgpu_sriov_vf(psp->adev))
+   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ >tmr_bo, >tmr_mc_addr, 
NULL);
+   else
+   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ >tmr_bo, >tmr_mc_addr, 
_buf);
 
return ret;
 }
@@ -1206,6 +1212,7 @@ static int psp_hw_fini(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = >psp;
+   void *tmr_buf;
 
if (adev->gmc.xgmi.num_physical_nodes > 1 &&
psp->xgmi_context.initialized == 1)
@@ -1216,7 +1223,7 @@ static int psp_hw_fini(void *handle)
 
psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 
-   amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, NULL);
+   amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, _buf);
amdgpu_bo_free_kernel(>fw_pri_bo,
  >fw_pri_mc_addr, >fw_pri_buf);
amdgpu_bo_free_kernel(>fence_buf_bo,
-- 
2.7.4

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[PATCH 1/2] drm/amdgpu/psp: keep TMR in visible vram region for SRIOV

2019-08-28 Thread Tianci Yin 
From: "Tianci.Yin" 

Fix compute ring test failure in sriov scenario.

Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 14 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h |  1 +
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 9f7cc5b..92c68c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -261,9 +261,15 @@ static int psp_tmr_init(struct psp_context *psp)
}
}
 
-   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM,
- >tmr_bo, >tmr_mc_addr, NULL);
+   psp->tmr_buf = NULL;
+   if (!amdgpu_sriov_vf(psp->adev))
+   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ >tmr_bo, >tmr_mc_addr, 
NULL);
+   else
+   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ >tmr_bo, >tmr_mc_addr, 
>tmr_buf);
 
return ret;
 }
@@ -1216,7 +1222,7 @@ static int psp_hw_fini(void *handle)
 
psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 
-   amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, NULL);
+   amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, >tmr_buf);
amdgpu_bo_free_kernel(>fw_pri_bo,
  >fw_pri_mc_addr, >fw_pri_buf);
amdgpu_bo_free_kernel(>fence_buf_bo,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index bc0947f..b73d4aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -171,6 +171,7 @@ struct psp_context
/* tmr buffer */
struct amdgpu_bo*tmr_bo;
uint64_ttmr_mc_addr;
+   void*tmr_buf;
 
/* asd firmware and buffer */
const struct firmware   *asd_fw;
-- 
2.7.4

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