Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends
Am 19.07.19 um 00:34 schrieb Kuehling, Felix: On 2019-07-18 4:47 a.m., Christian König wrote: [SNIP] There is also a more general issue with direct submission that I found while you were on vacation. There is no locking of the ring buffer. So direct and non-direct submission to the same ring is broken at the moment. Correct. That's why I reserved an extra paging queue for this. Thinking more about it I've found that this is actually quite a killer argument for using a separate scheduler entity, cause for updates outside of the fault handler we actually need to have everything in order here. [SNIP] Yeah, the root PD always exists as long as the VM exists. Everything else can be created/destroyed/moved dynamically. Yeah, exactly. The question is how do we want to keep the root PD in place? We could still add the fence or we could pin it permanently. Right. I was thinking permanent pinning can lead to fragmentation. It would be good if those small root PDs could be moved around to make room for bigger contiguous allocations when needed. Yeah, exactly my fear as well. It's just that adding the user CS to the root PD will definitely make it leak into the memory management. [SNIP] I mean it was your requirement that we have a mix of page fault and pre-filled page tables in the same process. Right. There are a few different requirements: 1. Disable retry faults and instruction replay for a VM completely (better performance for ML shaders) 2. Pre-fill page tables even when retry faults are enabled In case #2 we could deal with page tables being evicted (not fenced). But MM engines that don't support retry faults would throw a wrench in this idea. Yeah, MM-engines still need to add all user CS fences to the BOs for the foreseeable future. So there will be a mix of page fault and fenced handling in the MM anyway, the optional pre-filling doesn't make that any more complicated. The only way around that is to allocate the new page tables with the no_wait_gpu flag set and so avoid having any dependencies on ongoing operations. We discussed this before. I suggested an emergency pool for page tables. That pool can have a limited size. If page tables don't have user fences on them, they can always be evicted, so we can always make room in this emergency pool. You underestimate the problem. For page tables I can make sure rather easily that we can always allocate something, but ALL allocations made during page fault can't depend on user CS. This means we need to use this for pages which are used for HMM based migration and for this you can't have a fixed pool. That is if you do migration in the page fault handler. We could do migration outside of the page fault handler. See below. You can always have the case that a page fault will move back something which was evicted or swapped out. But you do need fences on page tables related to the allocation and migration of page tables themselves. And your page table updates must wait for those fences. Therefore I think the whole approach of direct submission for page table updates is fundamentally broken. For the reasons noted above you can't have any fences related to the allocation and migration on page tables. What can happen later on is that you need to wait for a BO move to finish before we can update the page tables. A page table updated coming from a page fault handler should never have could want to migrate memory to wait for any BO move. The fact that there was a page fault means, someone is trying to access this memory right now. Well essentially with HMM we want to migrate memory to VRAM during the page fault handler, don't we? The page fault handler could inform migration decisions. But the migration itself doesn't need to be in the page fault handler. A migration can be on an application thread (e.g. triggered by an hbind or similar call) or on a worker thread that gets triggered by asynchonous events such as page faults, polling of performance counters, etc. A migration would trigger an MMU notifier that would invalidate the respective page table entries. Updating the page table entries with the new physical addresses would happen likely in a page fault handler after the migration is complete. Well now you are limiting the use case to HMM. As I noted before with both Vega and Navi based hw generations we probably can't always do this because of performance restrictions. To minimize the amount of page faults while the migration is in progress we could also put PTEs in silent retry mode first. After the migration is complete we could update the PTEs with non-silent retry or with the new physical addresses. Way to risky. We can only do this if we can be absolutely sure that the migration is happening. E.g. we can do this if we have a BO which is moving under driver control, but not with an MMU notifier. The handling here is simply not under driver control. But I think that this is a completely
Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends
On 2019-07-18 4:47 a.m., Christian König wrote: [snip] >>> This is a corner case we can handle later on. As long as the VM is >>> still alive just allocating page tables again should be sufficient for >>> this. >> Do you mean, instead of migrating page tables back, throwing them away >> and allocating a new one? > > Yes, exactly that's the idea here. OK, I think that would work. The thing with direct submission and not waiting for fences is, that you only have implicit synchronization with anything else that was also submitted directly to the same SDMA ring. So page table allocation and initialization would work fine. Migration would not, unless you have special cases for migration of page table BOs. There is also a more general issue with direct submission that I found while you were on vacation. There is no locking of the ring buffer. So direct and non-direct submission to the same ring is broken at the moment. > I mean it's perfectly possible that the process is killed while > faults > are still in the pipeline. > >> I think it's possible that a page table gets evicted while a page >> fault >> is pending. Maybe not with graphics, but definitely with compute >> where >> waves can be preempted while waiting for a page fault. In that case >> the >> direct access would break. >> >> Even with graphics I think it's still possible that new page tables >> need >> to be allocated to handle a page fault. When that happens, you >> need to >> wait for fences to let new page tables be validated and initialized. > Yeah, the problem here is that when you wait on fences which in turn > depend on your submission your end up in a deadlock. > I think this implies that you have amdgpu_cs fences attached to page tables. I believe this is the fundamental issue that needs to be fixed. >>> We still need this cause even with page faults the root PD can't be >>> evicted. >>> >>> What we can probably do is to split up the PDs/PTs into the root PD >>> and everything else. >> Yeah, the root PD always exists as long as the VM exists. Everything >> else can be created/destroyed/moved dynamically. > > Yeah, exactly. The question is how do we want to keep the root PD in > place? > > We could still add the fence or we could pin it permanently. Right. I was thinking permanent pinning can lead to fragmentation. It would be good if those small root PDs could be moved around to make room for bigger contiguous allocations when needed. > If you want to manage page tables in page fault interrupt handlers, you can't have command submission fences attached to your page tables. You can allow page tables to be evicted while the command submission is in progress. A page fault will fault it back in if it's needed. If you eliminate command submission fences on the page tables, you remove the potential for deadlocks. >>> No, there is still a huge potential for deadlocks here. >>> >>> Additional to the root PDs you can have a MM submission which needs to >>> wait for a compute submission to be finished. >> I assume by MM you mean "memory manger", not "multi-media". [SNIP] > > Sorry I meant "multi-media", so just snipped your response. > > What I want to say here is that I don't believe we can keep user CS > fences our of memory management. > > See there can be submission from engines which don't support or don't > want to enabled recoverable page faults which depend on submissions > which do use recoverable page faults. > > I mean it was your requirement that we have a mix of page fault and > pre-filled page tables in the same process. Right. There are a few different requirements: 1. Disable retry faults and instruction replay for a VM completely (better performance for ML shaders) 2. Pre-fill page tables even when retry faults are enabled In case #2 we could deal with page tables being evicted (not fenced). But MM engines that don't support retry faults would throw a wrench in this idea. > >>> If you then make your new allocation depend on the MM submission to be >>> finished you have a classical circle dependency and a deadlock at hand. >> I don't see it. Allocate page table, wait for fence associated with that >> page table initialization, update PTEs. At no point do we depend on the >> user CS being stalled by the page fault. There is not user submission on >> the paging ring. Anything that has been scheduled on the paging ring has >> its dependencies satisfied. > > Allocation is the main problem here. We need to make sure that we > never ever depend on user CS when making memory allocation in the page > fault handler. >> We may need separate scheduler entities >> (queues) for regular MM submissions that can depend on user fences and >> VM submissions that must not. > > Yeah, thought about that as well but even then you need a way to note > that you want to use this separate
Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends
Am 17.07.19 um 22:31 schrieb Kuehling, Felix: On 2019-07-17 5:10, Christian König wrote: Am 16.07.19 um 18:40 schrieb Kuehling, Felix: On 2019-07-16 9:36 a.m., Christian König wrote: Am 02.07.19 um 21:35 schrieb Kuehling, Felix: This assumes that page tables are resident when a page fault is handled. Yeah, that is correct. I also haven't completely figured out how we can prevent the VM from being destroyed while handling the fault. There are other cases I had in mind: Page tables can be evicted. For KFD processes which can be preempted with CWSR, it's possible that a wave that caused a page fault is preempted due to a page table eviction. That means, by the time the page fault is handled, the page table is no longer resident. This is a corner case we can handle later on. As long as the VM is still alive just allocating page tables again should be sufficient for this. Do you mean, instead of migrating page tables back, throwing them away and allocating a new one? Yes, exactly that's the idea here. Also, this may be a corner case. But I feel you're limiting yourself to a small range of current use cases. I'm not convinced that the design you're building here will scale to future use cases for HMM updating page tables for random virtual addresses. I'm looking for a general solution that will work for those future use cases. Otherwise we'll end up having to rewrite this page-table-update-in-fault-handler code from scratch in a month or two. Well actually I'm keeping mostly HMM in mind. Filling page tables on demand is just a step in between. I also want to support a use case where per-VM-BOs are swapped in and out on demand, but I think that we will just use that for testing. I mean it's perfectly possible that the process is killed while faults are still in the pipeline. I think it's possible that a page table gets evicted while a page fault is pending. Maybe not with graphics, but definitely with compute where waves can be preempted while waiting for a page fault. In that case the direct access would break. Even with graphics I think it's still possible that new page tables need to be allocated to handle a page fault. When that happens, you need to wait for fences to let new page tables be validated and initialized. Yeah, the problem here is that when you wait on fences which in turn depend on your submission your end up in a deadlock. I think this implies that you have amdgpu_cs fences attached to page tables. I believe this is the fundamental issue that needs to be fixed. We still need this cause even with page faults the root PD can't be evicted. What we can probably do is to split up the PDs/PTs into the root PD and everything else. Yeah, the root PD always exists as long as the VM exists. Everything else can be created/destroyed/moved dynamically. Yeah, exactly. The question is how do we want to keep the root PD in place? We could still add the fence or we could pin it permanently. If you want to manage page tables in page fault interrupt handlers, you can't have command submission fences attached to your page tables. You can allow page tables to be evicted while the command submission is in progress. A page fault will fault it back in if it's needed. If you eliminate command submission fences on the page tables, you remove the potential for deadlocks. No, there is still a huge potential for deadlocks here. Additional to the root PDs you can have a MM submission which needs to wait for a compute submission to be finished. I assume by MM you mean "memory manger", not "multi-media". [SNIP] Sorry I meant "multi-media", so just snipped your response. What I want to say here is that I don't believe we can keep user CS fences our of memory management. See there can be submission from engines which don't support or don't want to enabled recoverable page faults which depend on submissions which do use recoverable page faults. I mean it was your requirement that we have a mix of page fault and pre-filled page tables in the same process. If you then make your new allocation depend on the MM submission to be finished you have a classical circle dependency and a deadlock at hand. I don't see it. Allocate page table, wait for fence associated with that page table initialization, update PTEs. At no point do we depend on the user CS being stalled by the page fault. There is not user submission on the paging ring. Anything that has been scheduled on the paging ring has its dependencies satisfied. Allocation is the main problem here. We need to make sure that we never ever depend on user CS when making memory allocation in the page fault handler. We may need separate scheduler entities (queues) for regular MM submissions that can depend on user fences and VM submissions that must not. Yeah, thought about that as well but even then you need a way to note that you want to use this separate entity. The only way around that is to allocate the new page
Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends
On 2019-07-17 5:10, Christian König wrote: > Am 16.07.19 um 18:40 schrieb Kuehling, Felix: >> On 2019-07-16 9:36 a.m., Christian König wrote: >>> Am 02.07.19 um 21:35 schrieb Kuehling, Felix: This assumes that page tables are resident when a page fault is handled. >>> Yeah, that is correct. I also haven't completely figured out how we >>> can prevent the VM from being destroyed while handling the fault. >> There are other cases I had in mind: Page tables can be evicted. For KFD >> processes which can be preempted with CWSR, it's possible that a wave >> that caused a page fault is preempted due to a page table eviction. That >> means, by the time the page fault is handled, the page table is no >> longer resident. > > This is a corner case we can handle later on. As long as the VM is > still alive just allocating page tables again should be sufficient for > this. Do you mean, instead of migrating page tables back, throwing them away and allocating a new one? Also, this may be a corner case. But I feel you're limiting yourself to a small range of current use cases. I'm not convinced that the design you're building here will scale to future use cases for HMM updating page tables for random virtual addresses. I'm looking for a general solution that will work for those future use cases. Otherwise we'll end up having to rewrite this page-table-update-in-fault-handler code from scratch in a month or two. > >>> I mean it's perfectly possible that the process is killed while faults >>> are still in the pipeline. >>> I think it's possible that a page table gets evicted while a page fault is pending. Maybe not with graphics, but definitely with compute where waves can be preempted while waiting for a page fault. In that case the direct access would break. Even with graphics I think it's still possible that new page tables need to be allocated to handle a page fault. When that happens, you need to wait for fences to let new page tables be validated and initialized. >>> Yeah, the problem here is that when you wait on fences which in turn >>> depend on your submission your end up in a deadlock. >>> >> I think this implies that you have amdgpu_cs fences attached to page >> tables. I believe this is the fundamental issue that needs to be fixed. > > We still need this cause even with page faults the root PD can't be > evicted. > > What we can probably do is to split up the PDs/PTs into the root PD > and everything else. Yeah, the root PD always exists as long as the VM exists. Everything else can be created/destroyed/moved dynamically. > >> If you want to manage page tables in page fault interrupt handlers, you >> can't have command submission fences attached to your page tables. You >> can allow page tables to be evicted while the command submission is in >> progress. A page fault will fault it back in if it's needed. If you >> eliminate command submission fences on the page tables, you remove the >> potential for deadlocks. > > No, there is still a huge potential for deadlocks here. > > Additional to the root PDs you can have a MM submission which needs to > wait for a compute submission to be finished. I assume by MM you mean "memory manger", not "multi-media". What kind of MM submission specifically? It can't be a VM page table update, with my proposal to never add user CS fences to VM page table reservations. Are you talking about buffer moves? They could go on a separate scheduler entity from VM submissions, so they don't hold up VM updates. VM updates only need to wait for MM fences that affect the page table BOs themselves. > > If you then make your new allocation depend on the MM submission to be > finished you have a classical circle dependency and a deadlock at hand. I don't see it. Allocate page table, wait for fence associated with that page table initialization, update PTEs. At no point do we depend on the user CS being stalled by the page fault. There is not user submission on the paging ring. Anything that has been scheduled on the paging ring has its dependencies satisfied. We may need separate scheduler entities (queues) for regular MM submissions that can depend on user fences and VM submissions that must not. > > The only way around that is to allocate the new page tables with the > no_wait_gpu flag set and so avoid having any dependencies on ongoing > operations. We discussed this before. I suggested an emergency pool for page tables. That pool can have a limited size. If page tables don't have user fences on them, they can always be evicted, so we can always make room in this emergency pool. > >> But you do need fences on page tables related to the allocation and >> migration of page tables themselves. And your page table updates must >> wait for those fences. Therefore I think the whole approach of direct >> submission for page table updates is fundamentally broken. > > For the reasons
Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends
Am 16.07.19 um 18:40 schrieb Kuehling, Felix: On 2019-07-16 9:36 a.m., Christian König wrote: Am 02.07.19 um 21:35 schrieb Kuehling, Felix: This assumes that page tables are resident when a page fault is handled. Yeah, that is correct. I also haven't completely figured out how we can prevent the VM from being destroyed while handling the fault. There are other cases I had in mind: Page tables can be evicted. For KFD processes which can be preempted with CWSR, it's possible that a wave that caused a page fault is preempted due to a page table eviction. That means, by the time the page fault is handled, the page table is no longer resident. This is a corner case we can handle later on. As long as the VM is still alive just allocating page tables again should be sufficient for this. I mean it's perfectly possible that the process is killed while faults are still in the pipeline. I think it's possible that a page table gets evicted while a page fault is pending. Maybe not with graphics, but definitely with compute where waves can be preempted while waiting for a page fault. In that case the direct access would break. Even with graphics I think it's still possible that new page tables need to be allocated to handle a page fault. When that happens, you need to wait for fences to let new page tables be validated and initialized. Yeah, the problem here is that when you wait on fences which in turn depend on your submission your end up in a deadlock. I think this implies that you have amdgpu_cs fences attached to page tables. I believe this is the fundamental issue that needs to be fixed. We still need this cause even with page faults the root PD can't be evicted. What we can probably do is to split up the PDs/PTs into the root PD and everything else. If you want to manage page tables in page fault interrupt handlers, you can't have command submission fences attached to your page tables. You can allow page tables to be evicted while the command submission is in progress. A page fault will fault it back in if it's needed. If you eliminate command submission fences on the page tables, you remove the potential for deadlocks. No, there is still a huge potential for deadlocks here. Additional to the root PDs you can have a MM submission which needs to wait for a compute submission to be finished. If you then make your new allocation depend on the MM submission to be finished you have a classical circle dependency and a deadlock at hand. The only way around that is to allocate the new page tables with the no_wait_gpu flag set and so avoid having any dependencies on ongoing operations. But you do need fences on page tables related to the allocation and migration of page tables themselves. And your page table updates must wait for those fences. Therefore I think the whole approach of direct submission for page table updates is fundamentally broken. For the reasons noted above you can't have any fences related to the allocation and migration on page tables. What can happen later on is that you need to wait for a BO move to finish before we can update the page tables. But I think that this is a completely different operation which shouldn't be handled in the fault handler. In those cases the fault handler would just silence the retry fault and continue crunching on other faults. As soon as the BO is moved in place we should update the page tables again using the normal SDMA scheduler entity. Patch #2 deals with updating page directories. That pretty much implies that page tables have moved or been reallocated. Wouldn't that be a counter-indication for using direct page table updates? In other words, if you need to update page directories, a direct page table updates is unsafe by definition. No, page tables are allocated because this is for handling invalid faults. E.g. we get a fault for an address where nothing is mapped and just want to silence it. That's the scenario you have in mind now. But in the future we'll get page faults for addresses that have a valid VMA, and we want to use HMM to map that into the GPU page table. Yeah, but we will still need to use the same infrastructure. Avoiding waiting on ongoing operations is mandatory or otherwise we will immediately run into deadlocks. Regards, Christian. Regards, Felix I will try to implement something to at least avoid accessing a destructed VM. Regards, Christian. Regards, Felix On 2019-06-28 8:18 a.m., Christian König wrote: This allows us to update page tables directly while in a page fault. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 4 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 29 + 3 files changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index
Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends
On 2019-07-16 9:36 a.m., Christian König wrote:
> Am 02.07.19 um 21:35 schrieb Kuehling, Felix:
>> This assumes that page tables are resident when a page fault is handled.
>
> Yeah, that is correct. I also haven't completely figured out how we
> can prevent the VM from being destroyed while handling the fault.
There are other cases I had in mind: Page tables can be evicted. For KFD
processes which can be preempted with CWSR, it's possible that a wave
that caused a page fault is preempted due to a page table eviction. That
means, by the time the page fault is handled, the page table is no
longer resident.
>
> I mean it's perfectly possible that the process is killed while faults
> are still in the pipeline.
>
>> I think it's possible that a page table gets evicted while a page fault
>> is pending. Maybe not with graphics, but definitely with compute where
>> waves can be preempted while waiting for a page fault. In that case the
>> direct access would break.
>>
>> Even with graphics I think it's still possible that new page tables need
>> to be allocated to handle a page fault. When that happens, you need to
>> wait for fences to let new page tables be validated and initialized.
>
> Yeah, the problem here is that when you wait on fences which in turn
> depend on your submission your end up in a deadlock.
>
I think this implies that you have amdgpu_cs fences attached to page
tables. I believe this is the fundamental issue that needs to be fixed.
If you want to manage page tables in page fault interrupt handlers, you
can't have command submission fences attached to your page tables. You
can allow page tables to be evicted while the command submission is in
progress. A page fault will fault it back in if it's needed. If you
eliminate command submission fences on the page tables, you remove the
potential for deadlocks.
But you do need fences on page tables related to the allocation and
migration of page tables themselves. And your page table updates must
wait for those fences. Therefore I think the whole approach of direct
submission for page table updates is fundamentally broken.
>> Patch #2 deals with updating page directories. That pretty much implies
>> that page tables have moved or been reallocated. Wouldn't that be a
>> counter-indication for using direct page table updates? In other words,
>> if you need to update page directories, a direct page table updates is
>> unsafe by definition.
>
> No, page tables are allocated because this is for handling invalid
> faults.
>
> E.g. we get a fault for an address where nothing is mapped and just
> want to silence it.
That's the scenario you have in mind now. But in the future we'll get
page faults for addresses that have a valid VMA, and we want to use HMM
to map that into the GPU page table.
Regards,
Felix
>
> I will try to implement something to at least avoid accessing a
> destructed VM.
>
> Regards,
> Christian.
>
>>
>> Regards,
>> Felix
>>
>> On 2019-06-28 8:18 a.m., Christian König wrote:
>>> This allows us to update page tables directly while in a page fault.
>>>
>>> Signed-off-by: Christian König
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 4 +++
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 29
>>> +
>>> 3 files changed, 27 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>> index 489a162ca620..5941accea061 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>> @@ -197,6 +197,11 @@ struct amdgpu_vm_update_params {
>>> */
>>> struct amdgpu_vm *vm;
>>> + /**
>>> + * @direct: if changes should be made directly
>>> + */
>>> + bool direct;
>>> +
>>> /**
>>> * @pages_addr:
>>> *
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
>>> index 5222d165abfc..f94e4896079c 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
>>> @@ -49,6 +49,10 @@ static int amdgpu_vm_cpu_prepare(struct
>>> amdgpu_vm_update_params *p, void *owner,
>>> {
>>> int r;
>>> + /* Don't wait for anything during page fault */
>>> + if (p->direct)
>>> + return 0;
>>> +
>>> /* Wait for PT BOs to be idle. PTs share the same resv. object
>>> * as the root PD BO
>>> */
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
>>> index ddd181f5ed37..891d597063cb 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
>>> @@ -68,17 +68,17 @@ static int amdgpu_vm_sdma_prepare(struct
>>> amdgpu_vm_update_params *p,
>>> if (r)
>>> return r;
>>> - r =
Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends
Am 02.07.19 um 21:35 schrieb Kuehling, Felix:
This assumes that page tables are resident when a page fault is handled.
Yeah, that is correct. I also haven't completely figured out how we can
prevent the VM from being destroyed while handling the fault.
I mean it's perfectly possible that the process is killed while faults
are still in the pipeline.
I think it's possible that a page table gets evicted while a page fault
is pending. Maybe not with graphics, but definitely with compute where
waves can be preempted while waiting for a page fault. In that case the
direct access would break.
Even with graphics I think it's still possible that new page tables need
to be allocated to handle a page fault. When that happens, you need to
wait for fences to let new page tables be validated and initialized.
Yeah, the problem here is that when you wait on fences which in turn
depend on your submission your end up in a deadlock.
Patch #2 deals with updating page directories. That pretty much implies
that page tables have moved or been reallocated. Wouldn't that be a
counter-indication for using direct page table updates? In other words,
if you need to update page directories, a direct page table updates is
unsafe by definition.
No, page tables are allocated because this is for handling invalid faults.
E.g. we get a fault for an address where nothing is mapped and just want
to silence it.
I will try to implement something to at least avoid accessing a
destructed VM.
Regards,
Christian.
Regards,
Felix
On 2019-06-28 8:18 a.m., Christian König wrote:
This allows us to update page tables directly while in a page fault.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 29 +
3 files changed, 27 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 489a162ca620..5941accea061 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -197,6 +197,11 @@ struct amdgpu_vm_update_params {
*/
struct amdgpu_vm *vm;
+ /**
+* @direct: if changes should be made directly
+*/
+ bool direct;
+
/**
* @pages_addr:
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
index 5222d165abfc..f94e4896079c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
@@ -49,6 +49,10 @@ static int amdgpu_vm_cpu_prepare(struct
amdgpu_vm_update_params *p, void *owner,
{
int r;
+ /* Don't wait for anything during page fault */
+ if (p->direct)
+ return 0;
+
/* Wait for PT BOs to be idle. PTs share the same resv. object
* as the root PD BO
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index ddd181f5ed37..891d597063cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -68,17 +68,17 @@ static int amdgpu_vm_sdma_prepare(struct
amdgpu_vm_update_params *p,
if (r)
return r;
- r = amdgpu_sync_fence(p->adev, >job->sync, exclusive, false);
- if (r)
- return r;
+ p->num_dw_left = ndw;
+
+ if (p->direct)
+ return 0;
- r = amdgpu_sync_resv(p->adev, >job->sync, root->tbo.resv,
-owner, false);
+ r = amdgpu_sync_fence(p->adev, >job->sync, exclusive, false);
if (r)
return r;
- p->num_dw_left = ndw;
- return 0;
+ return amdgpu_sync_resv(p->adev, >job->sync, root->tbo.resv,
+ owner, false);
}
/**
@@ -99,13 +99,21 @@ static int amdgpu_vm_sdma_commit(struct
amdgpu_vm_update_params *p,
struct dma_fence *f;
int r;
- ring = container_of(p->vm->entity.rq->sched, struct amdgpu_ring, sched);
+ if (p->direct)
+ ring = p->adev->vm_manager.page_fault;
+ else
+ ring = container_of(p->vm->entity.rq->sched,
+ struct amdgpu_ring, sched);
WARN_ON(ib->length_dw == 0);
amdgpu_ring_pad_ib(ring, ib);
WARN_ON(ib->length_dw > p->num_dw_left);
- r = amdgpu_job_submit(p->job, >vm->entity,
- AMDGPU_FENCE_OWNER_VM, );
+
+ if (p->direct)
+ r = amdgpu_job_submit_direct(p->job, ring, );
+ else
+ r = amdgpu_job_submit(p->job, >vm->entity,
+ AMDGPU_FENCE_OWNER_VM, );
if (r)
goto error;
@@ -120,7 +128,6 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
return r;
}
Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends
This assumes that page tables are resident when a page fault is handled.
I think it's possible that a page table gets evicted while a page fault
is pending. Maybe not with graphics, but definitely with compute where
waves can be preempted while waiting for a page fault. In that case the
direct access would break.
Even with graphics I think it's still possible that new page tables need
to be allocated to handle a page fault. When that happens, you need to
wait for fences to let new page tables be validated and initialized.
Patch #2 deals with updating page directories. That pretty much implies
that page tables have moved or been reallocated. Wouldn't that be a
counter-indication for using direct page table updates? In other words,
if you need to update page directories, a direct page table updates is
unsafe by definition.
Regards,
Felix
On 2019-06-28 8:18 a.m., Christian König wrote:
> This allows us to update page tables directly while in a page fault.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 4 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 29 +
> 3 files changed, 27 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 489a162ca620..5941accea061 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -197,6 +197,11 @@ struct amdgpu_vm_update_params {
>*/
> struct amdgpu_vm *vm;
>
> + /**
> + * @direct: if changes should be made directly
> + */
> + bool direct;
> +
> /**
>* @pages_addr:
>*
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> index 5222d165abfc..f94e4896079c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> @@ -49,6 +49,10 @@ static int amdgpu_vm_cpu_prepare(struct
> amdgpu_vm_update_params *p, void *owner,
> {
> int r;
>
> + /* Don't wait for anything during page fault */
> + if (p->direct)
> + return 0;
> +
> /* Wait for PT BOs to be idle. PTs share the same resv. object
>* as the root PD BO
>*/
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> index ddd181f5ed37..891d597063cb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> @@ -68,17 +68,17 @@ static int amdgpu_vm_sdma_prepare(struct
> amdgpu_vm_update_params *p,
> if (r)
> return r;
>
> - r = amdgpu_sync_fence(p->adev, >job->sync, exclusive, false);
> - if (r)
> - return r;
> + p->num_dw_left = ndw;
> +
> + if (p->direct)
> + return 0;
>
> - r = amdgpu_sync_resv(p->adev, >job->sync, root->tbo.resv,
> - owner, false);
> + r = amdgpu_sync_fence(p->adev, >job->sync, exclusive, false);
> if (r)
> return r;
>
> - p->num_dw_left = ndw;
> - return 0;
> + return amdgpu_sync_resv(p->adev, >job->sync, root->tbo.resv,
> + owner, false);
> }
>
> /**
> @@ -99,13 +99,21 @@ static int amdgpu_vm_sdma_commit(struct
> amdgpu_vm_update_params *p,
> struct dma_fence *f;
> int r;
>
> - ring = container_of(p->vm->entity.rq->sched, struct amdgpu_ring, sched);
> + if (p->direct)
> + ring = p->adev->vm_manager.page_fault;
> + else
> + ring = container_of(p->vm->entity.rq->sched,
> + struct amdgpu_ring, sched);
>
> WARN_ON(ib->length_dw == 0);
> amdgpu_ring_pad_ib(ring, ib);
> WARN_ON(ib->length_dw > p->num_dw_left);
> - r = amdgpu_job_submit(p->job, >vm->entity,
> - AMDGPU_FENCE_OWNER_VM, );
> +
> + if (p->direct)
> + r = amdgpu_job_submit_direct(p->job, ring, );
> + else
> + r = amdgpu_job_submit(p->job, >vm->entity,
> + AMDGPU_FENCE_OWNER_VM, );
> if (r)
> goto error;
>
> @@ -120,7 +128,6 @@ static int amdgpu_vm_sdma_commit(struct
> amdgpu_vm_update_params *p,
> return r;
> }
>
> -
> /**
>* amdgpu_vm_sdma_copy_ptes - copy the PTEs from mapping
>*
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends
Am 28.06.19 um 16:30 schrieb Chunming Zhou:
在 2019/6/28 20:18, Christian König 写道:
This allows us to update page tables directly while in a page fault.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 29 +
3 files changed, 27 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 489a162ca620..5941accea061 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -197,6 +197,11 @@ struct amdgpu_vm_update_params {
*/
struct amdgpu_vm *vm;
+ /**
+* @direct: if changes should be made directly
+*/
+ bool direct;
+
/**
* @pages_addr:
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
index 5222d165abfc..f94e4896079c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
@@ -49,6 +49,10 @@ static int amdgpu_vm_cpu_prepare(struct
amdgpu_vm_update_params *p, void *owner,
{
int r;
+ /* Don't wait for anything during page fault */
+ if (p->direct)
+ return 0;
+
/* Wait for PT BOs to be idle. PTs share the same resv. object
* as the root PD BO
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index ddd181f5ed37..891d597063cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -68,17 +68,17 @@ static int amdgpu_vm_sdma_prepare(struct
amdgpu_vm_update_params *p,
if (r)
return r;
- r = amdgpu_sync_fence(p->adev, >job->sync, exclusive, false);
- if (r)
- return r;
+ p->num_dw_left = ndw;
+
+ if (p->direct)
+ return 0;
- r = amdgpu_sync_resv(p->adev, >job->sync, root->tbo.resv,
-owner, false);
+ r = amdgpu_sync_fence(p->adev, >job->sync, exclusive, false);
if (r)
return r;
- p->num_dw_left = ndw;
- return 0;
+ return amdgpu_sync_resv(p->adev, >job->sync, root->tbo.resv,
+ owner, false);
}
/**
@@ -99,13 +99,21 @@ static int amdgpu_vm_sdma_commit(struct
amdgpu_vm_update_params *p,
struct dma_fence *f;
int r;
- ring = container_of(p->vm->entity.rq->sched, struct amdgpu_ring, sched);
+ if (p->direct)
+ ring = p->adev->vm_manager.page_fault;
+ else
+ ring = container_of(p->vm->entity.rq->sched,
+ struct amdgpu_ring, sched);
WARN_ON(ib->length_dw == 0);
amdgpu_ring_pad_ib(ring, ib);
WARN_ON(ib->length_dw > p->num_dw_left);
- r = amdgpu_job_submit(p->job, >vm->entity,
- AMDGPU_FENCE_OWNER_VM, );
+
+ if (p->direct)
+ r = amdgpu_job_submit_direct(p->job, ring, );
When we use direct submission after intialization, we need to take care
of ring race condision, don't we? Am I missing anything?
Direct submission can only used by the page fault worker thread. And at
least for now there is exactly one worker thread.
Christian.
-David
+ else
+ r = amdgpu_job_submit(p->job, >vm->entity,
+ AMDGPU_FENCE_OWNER_VM, );
if (r)
goto error;
@@ -120,7 +128,6 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
return r;
}
-
/**
* amdgpu_vm_sdma_copy_ptes - copy the PTEs from mapping
*
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends
在 2019/6/28 20:18, Christian König 写道:
> This allows us to update page tables directly while in a page fault.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 4 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 29 +
> 3 files changed, 27 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 489a162ca620..5941accea061 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -197,6 +197,11 @@ struct amdgpu_vm_update_params {
>*/
> struct amdgpu_vm *vm;
>
> + /**
> + * @direct: if changes should be made directly
> + */
> + bool direct;
> +
> /**
>* @pages_addr:
>*
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> index 5222d165abfc..f94e4896079c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> @@ -49,6 +49,10 @@ static int amdgpu_vm_cpu_prepare(struct
> amdgpu_vm_update_params *p, void *owner,
> {
> int r;
>
> + /* Don't wait for anything during page fault */
> + if (p->direct)
> + return 0;
> +
> /* Wait for PT BOs to be idle. PTs share the same resv. object
>* as the root PD BO
>*/
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> index ddd181f5ed37..891d597063cb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> @@ -68,17 +68,17 @@ static int amdgpu_vm_sdma_prepare(struct
> amdgpu_vm_update_params *p,
> if (r)
> return r;
>
> - r = amdgpu_sync_fence(p->adev, >job->sync, exclusive, false);
> - if (r)
> - return r;
> + p->num_dw_left = ndw;
> +
> + if (p->direct)
> + return 0;
>
> - r = amdgpu_sync_resv(p->adev, >job->sync, root->tbo.resv,
> - owner, false);
> + r = amdgpu_sync_fence(p->adev, >job->sync, exclusive, false);
> if (r)
> return r;
>
> - p->num_dw_left = ndw;
> - return 0;
> + return amdgpu_sync_resv(p->adev, >job->sync, root->tbo.resv,
> + owner, false);
> }
>
> /**
> @@ -99,13 +99,21 @@ static int amdgpu_vm_sdma_commit(struct
> amdgpu_vm_update_params *p,
> struct dma_fence *f;
> int r;
>
> - ring = container_of(p->vm->entity.rq->sched, struct amdgpu_ring, sched);
> + if (p->direct)
> + ring = p->adev->vm_manager.page_fault;
> + else
> + ring = container_of(p->vm->entity.rq->sched,
> + struct amdgpu_ring, sched);
>
> WARN_ON(ib->length_dw == 0);
> amdgpu_ring_pad_ib(ring, ib);
> WARN_ON(ib->length_dw > p->num_dw_left);
> - r = amdgpu_job_submit(p->job, >vm->entity,
> - AMDGPU_FENCE_OWNER_VM, );
> +
> + if (p->direct)
> + r = amdgpu_job_submit_direct(p->job, ring, );
When we use direct submission after intialization, we need to take care
of ring race condision, don't we? Am I missing anything?
-David
> + else
> + r = amdgpu_job_submit(p->job, >vm->entity,
> + AMDGPU_FENCE_OWNER_VM, );
> if (r)
> goto error;
>
> @@ -120,7 +128,6 @@ static int amdgpu_vm_sdma_commit(struct
> amdgpu_vm_update_params *p,
> return r;
> }
>
> -
> /**
>* amdgpu_vm_sdma_copy_ptes - copy the PTEs from mapping
>*
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends
This allows us to update page tables directly while in a page fault.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 29 +
3 files changed, 27 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 489a162ca620..5941accea061 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -197,6 +197,11 @@ struct amdgpu_vm_update_params {
*/
struct amdgpu_vm *vm;
+ /**
+* @direct: if changes should be made directly
+*/
+ bool direct;
+
/**
* @pages_addr:
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
index 5222d165abfc..f94e4896079c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
@@ -49,6 +49,10 @@ static int amdgpu_vm_cpu_prepare(struct
amdgpu_vm_update_params *p, void *owner,
{
int r;
+ /* Don't wait for anything during page fault */
+ if (p->direct)
+ return 0;
+
/* Wait for PT BOs to be idle. PTs share the same resv. object
* as the root PD BO
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index ddd181f5ed37..891d597063cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -68,17 +68,17 @@ static int amdgpu_vm_sdma_prepare(struct
amdgpu_vm_update_params *p,
if (r)
return r;
- r = amdgpu_sync_fence(p->adev, >job->sync, exclusive, false);
- if (r)
- return r;
+ p->num_dw_left = ndw;
+
+ if (p->direct)
+ return 0;
- r = amdgpu_sync_resv(p->adev, >job->sync, root->tbo.resv,
-owner, false);
+ r = amdgpu_sync_fence(p->adev, >job->sync, exclusive, false);
if (r)
return r;
- p->num_dw_left = ndw;
- return 0;
+ return amdgpu_sync_resv(p->adev, >job->sync, root->tbo.resv,
+ owner, false);
}
/**
@@ -99,13 +99,21 @@ static int amdgpu_vm_sdma_commit(struct
amdgpu_vm_update_params *p,
struct dma_fence *f;
int r;
- ring = container_of(p->vm->entity.rq->sched, struct amdgpu_ring, sched);
+ if (p->direct)
+ ring = p->adev->vm_manager.page_fault;
+ else
+ ring = container_of(p->vm->entity.rq->sched,
+ struct amdgpu_ring, sched);
WARN_ON(ib->length_dw == 0);
amdgpu_ring_pad_ib(ring, ib);
WARN_ON(ib->length_dw > p->num_dw_left);
- r = amdgpu_job_submit(p->job, >vm->entity,
- AMDGPU_FENCE_OWNER_VM, );
+
+ if (p->direct)
+ r = amdgpu_job_submit_direct(p->job, ring, );
+ else
+ r = amdgpu_job_submit(p->job, >vm->entity,
+ AMDGPU_FENCE_OWNER_VM, );
if (r)
goto error;
@@ -120,7 +128,6 @@ static int amdgpu_vm_sdma_commit(struct
amdgpu_vm_update_params *p,
return r;
}
-
/**
* amdgpu_vm_sdma_copy_ptes - copy the PTEs from mapping
*
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
