[PATCH 12/21] drm/amd/powerplay: add JPEG power control for Navi1x

2019-11-13 Thread Leo Liu 
By separating the JPEG power feature, and using its
own PowerUp and PowerDown messages

v2: remove PowerUpJpeg message argument

Signed-off-by: Leo Liu 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 32 --
 1 file changed, 30 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index aeb9c1e341c7..dce6f76ecbe5 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -384,8 +384,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 
if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
-   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT)
-   | FEATURE_MASK(FEATURE_JPEG_PG_BIT);
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
+
+   if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 
/* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
if (is_asic_secure(smu)) {
@@ -665,6 +667,31 @@ static int navi10_dpm_set_uvd_enable(struct smu_context 
*smu, bool enable)
return ret;
 }
 
+static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
+{
+   struct smu_power_context *smu_power = >smu_power;
+   struct smu_power_gate *power_gate = _power->power_gate;
+   int ret = 0;
+
+   if (enable) {
+   if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
+   ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg);
+   if (ret)
+   return ret;
+   }
+   power_gate->jpeg_gated = false;
+   } else {
+   if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
+   ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg);
+   if (ret)
+   return ret;
+   }
+   power_gate->jpeg_gated = true;
+   }
+
+   return ret;
+}
+
 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
   enum smu_clk_type clk_type,
   uint32_t *value)
@@ -1996,6 +2023,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.get_allowed_feature_mask = navi10_get_allowed_feature_mask,
.set_default_dpm_table = navi10_set_default_dpm_table,
.dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
+   .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
.get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
.print_clk_levels = navi10_print_clk_levels,
.force_clk_levels = navi10_force_clk_levels,
-- 
2.17.1

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Re: [PATCH 12/21] drm/amd/powerplay: add JPEG power control for Navi1x

2019-11-13 Thread Leo Liu 


On 2019-11-12 10:50 p.m., Quan, Evan wrote:

For Navi10, SMU_MSG_PowerUpJpeg message does not need an argument.


The fixes for this and others will be in v2. Thanks for pointing this out.

Regards,

Leo





-Original Message-
From: amd-gfx  On Behalf Of Leo Liu
Sent: Wednesday, November 13, 2019 2:03 AM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Leo 
Subject: [PATCH 12/21] drm/amd/powerplay: add JPEG power control for
Navi1x

By separating the JPEG power feature, and using its own PowerUp and
PowerDown messages

Signed-off-by: Leo Liu 
---
  drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 32 --
  1 file changed, 30 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index aeb9c1e341c7..760568debe6c 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -384,8 +384,10 @@ navi10_get_allowed_feature_mask(struct
smu_context *smu,
*(uint64_t *)feature_mask |=
FEATURE_MASK(FEATURE_ATHUB_PG_BIT);

if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
-   *(uint64_t *)feature_mask |=
FEATURE_MASK(FEATURE_VCN_PG_BIT)
-   | FEATURE_MASK(FEATURE_JPEG_PG_BIT);
+   *(uint64_t *)feature_mask |=
FEATURE_MASK(FEATURE_VCN_PG_BIT);
+
+   if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
+   *(uint64_t *)feature_mask |=
FEATURE_MASK(FEATURE_JPEG_PG_BIT);

/* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
if (is_asic_secure(smu)) {
@@ -665,6 +667,31 @@ static int navi10_dpm_set_uvd_enable(struct
smu_context *smu, bool enable)
return ret;
  }

+static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool
+enable) {
+   struct smu_power_context *smu_power = >smu_power;
+   struct smu_power_gate *power_gate = _power->power_gate;
+   int ret = 0;
+
+   if (enable) {
+   if (smu_feature_is_enabled(smu,
SMU_FEATURE_JPEG_PG_BIT)) {
+   ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_PowerUpJpeg, 1);
+   if (ret)
+   return ret;
+   }
+   power_gate->jpeg_gated = false;
+   } else {
+   if (smu_feature_is_enabled(smu,
SMU_FEATURE_JPEG_PG_BIT)) {
+   ret = smu_send_smc_msg(smu,
SMU_MSG_PowerDownJpeg);
+   if (ret)
+   return ret;
+   }
+   power_gate->jpeg_gated = true;
+   }
+
+   return ret;
+}
+
  static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
   enum smu_clk_type clk_type,
   uint32_t *value)
@@ -1996,6 +2023,7 @@ static const struct pptable_funcs navi10_ppt_funcs =
{
.get_allowed_feature_mask = navi10_get_allowed_feature_mask,
.set_default_dpm_table = navi10_set_default_dpm_table,
.dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
+   .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
.get_current_clk_freq_by_table =
navi10_get_current_clk_freq_by_table,
.print_clk_levels = navi10_print_clk_levels,
.force_clk_levels = navi10_force_clk_levels,
--
2.17.1

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RE: [PATCH 12/21] drm/amd/powerplay: add JPEG power control for Navi1x

2019-11-12 Thread Quan, Evan 
For Navi10, SMU_MSG_PowerUpJpeg message does not need an argument.

> -Original Message-
> From: amd-gfx  On Behalf Of Leo Liu
> Sent: Wednesday, November 13, 2019 2:03 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Leo 
> Subject: [PATCH 12/21] drm/amd/powerplay: add JPEG power control for
> Navi1x
> 
> By separating the JPEG power feature, and using its own PowerUp and
> PowerDown messages
> 
> Signed-off-by: Leo Liu 
> ---
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 32 --
>  1 file changed, 30 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index aeb9c1e341c7..760568debe6c 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -384,8 +384,10 @@ navi10_get_allowed_feature_mask(struct
> smu_context *smu,
>   *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
> 
>   if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
> - *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_VCN_PG_BIT)
> - | FEATURE_MASK(FEATURE_JPEG_PG_BIT);
> + *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_VCN_PG_BIT);
> +
> + if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
> + *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_JPEG_PG_BIT);
> 
>   /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
>   if (is_asic_secure(smu)) {
> @@ -665,6 +667,31 @@ static int navi10_dpm_set_uvd_enable(struct
> smu_context *smu, bool enable)
>   return ret;
>  }
> 
> +static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool
> +enable) {
> + struct smu_power_context *smu_power = >smu_power;
> + struct smu_power_gate *power_gate = _power->power_gate;
> + int ret = 0;
> +
> + if (enable) {
> + if (smu_feature_is_enabled(smu,
> SMU_FEATURE_JPEG_PG_BIT)) {
> + ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_PowerUpJpeg, 1);
> + if (ret)
> + return ret;
> + }
> + power_gate->jpeg_gated = false;
> + } else {
> + if (smu_feature_is_enabled(smu,
> SMU_FEATURE_JPEG_PG_BIT)) {
> + ret = smu_send_smc_msg(smu,
> SMU_MSG_PowerDownJpeg);
> + if (ret)
> + return ret;
> + }
> + power_gate->jpeg_gated = true;
> + }
> +
> + return ret;
> +}
> +
>  static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
>  enum smu_clk_type clk_type,
>  uint32_t *value)
> @@ -1996,6 +2023,7 @@ static const struct pptable_funcs navi10_ppt_funcs =
> {
>   .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
>   .set_default_dpm_table = navi10_set_default_dpm_table,
>   .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
> + .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
>   .get_current_clk_freq_by_table =
> navi10_get_current_clk_freq_by_table,
>   .print_clk_levels = navi10_print_clk_levels,
>   .force_clk_levels = navi10_force_clk_levels,
> --
> 2.17.1
> 
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[PATCH 12/21] drm/amd/powerplay: add JPEG power control for Navi1x

2019-11-12 Thread Leo Liu 
By separating the JPEG power feature, and using its
own PowerUp and PowerDown messages

Signed-off-by: Leo Liu 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 32 --
 1 file changed, 30 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index aeb9c1e341c7..760568debe6c 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -384,8 +384,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 
if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
-   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT)
-   | FEATURE_MASK(FEATURE_JPEG_PG_BIT);
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
+
+   if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 
/* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
if (is_asic_secure(smu)) {
@@ -665,6 +667,31 @@ static int navi10_dpm_set_uvd_enable(struct smu_context 
*smu, bool enable)
return ret;
 }
 
+static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
+{
+   struct smu_power_context *smu_power = >smu_power;
+   struct smu_power_gate *power_gate = _power->power_gate;
+   int ret = 0;
+
+   if (enable) {
+   if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
+   ret = smu_send_smc_msg_with_param(smu, 
SMU_MSG_PowerUpJpeg, 1);
+   if (ret)
+   return ret;
+   }
+   power_gate->jpeg_gated = false;
+   } else {
+   if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
+   ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg);
+   if (ret)
+   return ret;
+   }
+   power_gate->jpeg_gated = true;
+   }
+
+   return ret;
+}
+
 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
   enum smu_clk_type clk_type,
   uint32_t *value)
@@ -1996,6 +2023,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.get_allowed_feature_mask = navi10_get_allowed_feature_mask,
.set_default_dpm_table = navi10_set_default_dpm_table,
.dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
+   .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
.get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
.print_clk_levels = navi10_print_clk_levels,
.force_clk_levels = navi10_force_clk_levels,
-- 
2.17.1

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