Re: [PATCH 2/2] Revert "drm/amd/display: Do not set drr on pipe commit"

2023-05-23 Thread Pillai, Aurabindo 
[AMD Official Use Only - General]

Yep, we shall, thanks Alex.

--

Regards,
Jay

From: Alex Deucher 
Sent: Tuesday, May 23, 2023 11:47 AM
To: Pillai, Aurabindo ; Mahfooz, Hamza 

Cc: Michel Dänzer ; Deucher, Alexander 
; Chalmers, Wesley ; Li, 
Sun peng (Leo) ; Zhuo, Qingqing (Lillian) 
; Siqueira, Rodrigo ; 
amd-gfx@lists.freedesktop.org ; Wentland, Harry 

Subject: Re: [PATCH 2/2] Revert "drm/amd/display: Do not set drr on pipe commit"

Acked-by: Alex Deucher 
for the series.

Jay, I assume you or Hamza will pick these up?

Thanks,

Alex

On Tue, May 23, 2023 at 11:31 AM Aurabindo Pillai
 wrote:
>
> Reviewed-by: Aurabindo Pillai 
>
> On 5/22/23 09:08, Michel Dänzer wrote:
> > From: Michel Dänzer 
> >
> > This reverts commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be.
> >
> > Caused a regression:
> >
> > Samsung Odyssey Neo G9, running at 5120x1440@240/VRR, connected to Navi
> > 21 via DisplayPort, blanks and the GPU hangs while starting the Steam
> > game Assetto Corsa Competizione (via Proton 7.0).
> >
> > Example dmesg excerpt:
> >
> >  amdgpu :0c:00.0: [drm] ERROR [CRTC:82:crtc-0] flip_done timed out
> >  NMI watchdog: Watchdog detected hard LOCKUP on cpu 6
> >  [...]
> >  RIP: 0010:amdgpu_device_rreg.part.0+0x2f/0xf0 [amdgpu]
> >  Code: 41 54 44 8d 24 b5 00 00 00 00 55 89 f5 53 48 89 fb 4c 3b a7 60 0b 00 
> > 00 73 6a 83 e2 02 74 29 4c 03 a3 68 0b 00 00 45 8b 24 24 <48> 8b 43 08 0f 
> > b7 70 3e 66 90 44 89 e0 5b 5d 41 5c 31 d2 31 c9 31
> >  RSP: :b39a119dfb88 EFLAGS: 0086
> >  RAX: c0eb96a0 RBX: 9e7963dc RCX: 7fff
> >  RDX:  RSI: 4ff6 RDI: 9e7963dc
> >  RBP: 4ff6 R08: b39a119dfc40 R09: 0010
> >  R10: b39a119dfc40 R11: b39a119dfc44 R12: 000e05ae
> >  R13:  R14: 9e7963dc0010 R15: 
> >  FS:  1012f6c0() GS:9e805eb8() 
> > knlGS:7fd4
> >  CS:  0010 DS:  ES:  CR0: 80050033
> >  CR2: 461ca000 CR3: 0002a8a2 CR4: 00350ee0
> >  Call Trace:
> >   
> >   dm_read_reg_func+0x37/0xc0 [amdgpu]
> >   generic_reg_get2+0x22/0x60 [amdgpu]
> >   optc1_get_crtc_scanoutpos+0x6a/0xc0 [amdgpu]
> >   dc_stream_get_scanoutpos+0x74/0x90 [amdgpu]
> >   dm_crtc_get_scanoutpos+0x82/0xf0 [amdgpu]
> >   amdgpu_display_get_crtc_scanoutpos+0x91/0x190 [amdgpu]
> >   ? dm_read_reg_func+0x37/0xc0 [amdgpu]
> >   amdgpu_get_vblank_counter_kms+0xb4/0x1a0 [amdgpu]
> >   dm_pflip_high_irq+0x213/0x2f0 [amdgpu]
> >   amdgpu_dm_irq_handler+0x8a/0x200 [amdgpu]
> >   amdgpu_irq_dispatch+0xd4/0x220 [amdgpu]
> >   amdgpu_ih_process+0x7f/0x110 [amdgpu]
> >   amdgpu_irq_handler+0x1f/0x70 [amdgpu]
> >   __handle_irq_event_percpu+0x46/0x1b0
> >   handle_irq_event+0x34/0x80
> >   handle_edge_irq+0x9f/0x240
> >   __common_interrupt+0x66/0x110
> >   common_interrupt+0x5c/0xd0
> >   asm_common_interrupt+0x22/0x40
> >
> > Signed-off-by: Michel Dänzer 
> > ---
> >  drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 --
> >  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 7 ---
> >  2 files changed, 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
> > b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > index 6ce10fd4bb1a..5403e9399a46 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > @@ -2113,12 +2113,6 @@ void dcn20_optimize_bandwidth(
> >   if (hubbub->funcs->program_compbuf_size)
> >   hubbub->funcs->program_compbuf_size(hubbub, 
> > context->bw_ctx.bw.dcn.compbuf_size_kb, true);
> >
> > - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
> > - dc_dmub_srv_p_state_delegate(dc,
> > - true, context);
> > - context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
> > - }
> > -
> >   dc->clk_mgr->funcs->update_clocks(
> >   dc->clk_mgr,
> >   context,
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
> > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > index 0411867654dd..0e071fbc9154 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > @@ -985,18 +985,11 @@ void dcn30_set_disp_patte

Re: [PATCH 2/2] Revert "drm/amd/display: Do not set drr on pipe commit"

2023-05-23 Thread Alex Deucher 
Acked-by: Alex Deucher 
for the series.

Jay, I assume you or Hamza will pick these up?

Thanks,

Alex

On Tue, May 23, 2023 at 11:31 AM Aurabindo Pillai
 wrote:
>
> Reviewed-by: Aurabindo Pillai 
>
> On 5/22/23 09:08, Michel Dänzer wrote:
> > From: Michel Dänzer 
> >
> > This reverts commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be.
> >
> > Caused a regression:
> >
> > Samsung Odyssey Neo G9, running at 5120x1440@240/VRR, connected to Navi
> > 21 via DisplayPort, blanks and the GPU hangs while starting the Steam
> > game Assetto Corsa Competizione (via Proton 7.0).
> >
> > Example dmesg excerpt:
> >
> >  amdgpu :0c:00.0: [drm] ERROR [CRTC:82:crtc-0] flip_done timed out
> >  NMI watchdog: Watchdog detected hard LOCKUP on cpu 6
> >  [...]
> >  RIP: 0010:amdgpu_device_rreg.part.0+0x2f/0xf0 [amdgpu]
> >  Code: 41 54 44 8d 24 b5 00 00 00 00 55 89 f5 53 48 89 fb 4c 3b a7 60 0b 00 
> > 00 73 6a 83 e2 02 74 29 4c 03 a3 68 0b 00 00 45 8b 24 24 <48> 8b 43 08 0f 
> > b7 70 3e 66 90 44 89 e0 5b 5d 41 5c 31 d2 31 c9 31
> >  RSP: :b39a119dfb88 EFLAGS: 0086
> >  RAX: c0eb96a0 RBX: 9e7963dc RCX: 7fff
> >  RDX:  RSI: 4ff6 RDI: 9e7963dc
> >  RBP: 4ff6 R08: b39a119dfc40 R09: 0010
> >  R10: b39a119dfc40 R11: b39a119dfc44 R12: 000e05ae
> >  R13:  R14: 9e7963dc0010 R15: 
> >  FS:  1012f6c0() GS:9e805eb8() 
> > knlGS:7fd4
> >  CS:  0010 DS:  ES:  CR0: 80050033
> >  CR2: 461ca000 CR3: 0002a8a2 CR4: 00350ee0
> >  Call Trace:
> >   
> >   dm_read_reg_func+0x37/0xc0 [amdgpu]
> >   generic_reg_get2+0x22/0x60 [amdgpu]
> >   optc1_get_crtc_scanoutpos+0x6a/0xc0 [amdgpu]
> >   dc_stream_get_scanoutpos+0x74/0x90 [amdgpu]
> >   dm_crtc_get_scanoutpos+0x82/0xf0 [amdgpu]
> >   amdgpu_display_get_crtc_scanoutpos+0x91/0x190 [amdgpu]
> >   ? dm_read_reg_func+0x37/0xc0 [amdgpu]
> >   amdgpu_get_vblank_counter_kms+0xb4/0x1a0 [amdgpu]
> >   dm_pflip_high_irq+0x213/0x2f0 [amdgpu]
> >   amdgpu_dm_irq_handler+0x8a/0x200 [amdgpu]
> >   amdgpu_irq_dispatch+0xd4/0x220 [amdgpu]
> >   amdgpu_ih_process+0x7f/0x110 [amdgpu]
> >   amdgpu_irq_handler+0x1f/0x70 [amdgpu]
> >   __handle_irq_event_percpu+0x46/0x1b0
> >   handle_irq_event+0x34/0x80
> >   handle_edge_irq+0x9f/0x240
> >   __common_interrupt+0x66/0x110
> >   common_interrupt+0x5c/0xd0
> >   asm_common_interrupt+0x22/0x40
> >
> > Signed-off-by: Michel Dänzer 
> > ---
> >  drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 --
> >  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 7 ---
> >  2 files changed, 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
> > b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > index 6ce10fd4bb1a..5403e9399a46 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > @@ -2113,12 +2113,6 @@ void dcn20_optimize_bandwidth(
> >   if (hubbub->funcs->program_compbuf_size)
> >   hubbub->funcs->program_compbuf_size(hubbub, 
> > context->bw_ctx.bw.dcn.compbuf_size_kb, true);
> >
> > - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
> > - dc_dmub_srv_p_state_delegate(dc,
> > - true, context);
> > - context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
> > - }
> > -
> >   dc->clk_mgr->funcs->update_clocks(
> >   dc->clk_mgr,
> >   context,
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
> > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > index 0411867654dd..0e071fbc9154 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > @@ -985,18 +985,11 @@ void dcn30_set_disp_pattern_generator(const struct dc 
> > *dc,
> >  void dcn30_prepare_bandwidth(struct dc *dc,
> >   struct dc_state *context)
> >  {
> > - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
> > - dc->optimized_required = true;
> > - context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
> > - }
> > -
> >   if (dc->clk_mgr->dc_mode_softmax_enabled)
> >   if (dc->clk_mgr->clks.dramclk_khz <= 
> > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
> >   context->bw_ctx.bw.dcn.clk.dramclk_khz > 
> > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
> >   dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, 
> > dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries
> >  - 1].memclk_mhz);
> >
> >   dcn20_prepare_bandwidth(dc, context);
> > -
> > - dc_dmub_srv_p_state_delegate(dc, false, context);
> >  }
> >

Re: [PATCH 2/2] Revert "drm/amd/display: Do not set drr on pipe commit"

2023-05-23 Thread Aurabindo Pillai 
Reviewed-by: Aurabindo Pillai 

On 5/22/23 09:08, Michel Dänzer wrote:
> From: Michel Dänzer 
> 
> This reverts commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be.
> 
> Caused a regression:
> 
> Samsung Odyssey Neo G9, running at 5120x1440@240/VRR, connected to Navi
> 21 via DisplayPort, blanks and the GPU hangs while starting the Steam
> game Assetto Corsa Competizione (via Proton 7.0).
> 
> Example dmesg excerpt:
> 
>  amdgpu :0c:00.0: [drm] ERROR [CRTC:82:crtc-0] flip_done timed out
>  NMI watchdog: Watchdog detected hard LOCKUP on cpu 6
>  [...]
>  RIP: 0010:amdgpu_device_rreg.part.0+0x2f/0xf0 [amdgpu]
>  Code: 41 54 44 8d 24 b5 00 00 00 00 55 89 f5 53 48 89 fb 4c 3b a7 60 0b 00 
> 00 73 6a 83 e2 02 74 29 4c 03 a3 68 0b 00 00 45 8b 24 24 <48> 8b 43 08 0f b7 
> 70 3e 66 90 44 89 e0 5b 5d 41 5c 31 d2 31 c9 31
>  RSP: :b39a119dfb88 EFLAGS: 0086
>  RAX: c0eb96a0 RBX: 9e7963dc RCX: 7fff
>  RDX:  RSI: 4ff6 RDI: 9e7963dc
>  RBP: 4ff6 R08: b39a119dfc40 R09: 0010
>  R10: b39a119dfc40 R11: b39a119dfc44 R12: 000e05ae
>  R13:  R14: 9e7963dc0010 R15: 
>  FS:  1012f6c0() GS:9e805eb8() knlGS:7fd4
>  CS:  0010 DS:  ES:  CR0: 80050033
>  CR2: 461ca000 CR3: 0002a8a2 CR4: 00350ee0
>  Call Trace:
>   
>   dm_read_reg_func+0x37/0xc0 [amdgpu]
>   generic_reg_get2+0x22/0x60 [amdgpu]
>   optc1_get_crtc_scanoutpos+0x6a/0xc0 [amdgpu]
>   dc_stream_get_scanoutpos+0x74/0x90 [amdgpu]
>   dm_crtc_get_scanoutpos+0x82/0xf0 [amdgpu]
>   amdgpu_display_get_crtc_scanoutpos+0x91/0x190 [amdgpu]
>   ? dm_read_reg_func+0x37/0xc0 [amdgpu]
>   amdgpu_get_vblank_counter_kms+0xb4/0x1a0 [amdgpu]
>   dm_pflip_high_irq+0x213/0x2f0 [amdgpu]
>   amdgpu_dm_irq_handler+0x8a/0x200 [amdgpu]
>   amdgpu_irq_dispatch+0xd4/0x220 [amdgpu]
>   amdgpu_ih_process+0x7f/0x110 [amdgpu]
>   amdgpu_irq_handler+0x1f/0x70 [amdgpu]
>   __handle_irq_event_percpu+0x46/0x1b0
>   handle_irq_event+0x34/0x80
>   handle_edge_irq+0x9f/0x240
>   __common_interrupt+0x66/0x110
>   common_interrupt+0x5c/0xd0
>   asm_common_interrupt+0x22/0x40
> 
> Signed-off-by: Michel Dänzer 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 --
>  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 7 ---
>  2 files changed, 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> index 6ce10fd4bb1a..5403e9399a46 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> @@ -2113,12 +2113,6 @@ void dcn20_optimize_bandwidth(
>   if (hubbub->funcs->program_compbuf_size)
>   hubbub->funcs->program_compbuf_size(hubbub, 
> context->bw_ctx.bw.dcn.compbuf_size_kb, true);
>  
> - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
> - dc_dmub_srv_p_state_delegate(dc,
> - true, context);
> - context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
> - }
> -
>   dc->clk_mgr->funcs->update_clocks(
>   dc->clk_mgr,
>   context,
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index 0411867654dd..0e071fbc9154 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -985,18 +985,11 @@ void dcn30_set_disp_pattern_generator(const struct dc 
> *dc,
>  void dcn30_prepare_bandwidth(struct dc *dc,
>   struct dc_state *context)
>  {
> - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
> - dc->optimized_required = true;
> - context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
> - }
> -
>   if (dc->clk_mgr->dc_mode_softmax_enabled)
>   if (dc->clk_mgr->clks.dramclk_khz <= 
> dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
>   context->bw_ctx.bw.dcn.clk.dramclk_khz > 
> dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
>   dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, 
> dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries
>  - 1].memclk_mhz);
>  
>   dcn20_prepare_bandwidth(dc, context);
> -
> - dc_dmub_srv_p_state_delegate(dc, false, context);
>  }
>

[PATCH 2/2] Revert "drm/amd/display: Do not set drr on pipe commit"

2023-05-22 Thread Michel Dänzer 
From: Michel Dänzer 

This reverts commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be.

Caused a regression:

Samsung Odyssey Neo G9, running at 5120x1440@240/VRR, connected to Navi
21 via DisplayPort, blanks and the GPU hangs while starting the Steam
game Assetto Corsa Competizione (via Proton 7.0).

Example dmesg excerpt:

 amdgpu :0c:00.0: [drm] ERROR [CRTC:82:crtc-0] flip_done timed out
 NMI watchdog: Watchdog detected hard LOCKUP on cpu 6
 [...]
 RIP: 0010:amdgpu_device_rreg.part.0+0x2f/0xf0 [amdgpu]
 Code: 41 54 44 8d 24 b5 00 00 00 00 55 89 f5 53 48 89 fb 4c 3b a7 60 0b 00 00 
73 6a 83 e2 02 74 29 4c 03 a3 68 0b 00 00 45 8b 24 24 <48> 8b 43 08 0f b7 70 3e 
66 90 44 89 e0 5b 5d 41 5c 31 d2 31 c9 31
 RSP: :b39a119dfb88 EFLAGS: 0086
 RAX: c0eb96a0 RBX: 9e7963dc RCX: 7fff
 RDX:  RSI: 4ff6 RDI: 9e7963dc
 RBP: 4ff6 R08: b39a119dfc40 R09: 0010
 R10: b39a119dfc40 R11: b39a119dfc44 R12: 000e05ae
 R13:  R14: 9e7963dc0010 R15: 
 FS:  1012f6c0() GS:9e805eb8() knlGS:7fd4
 CS:  0010 DS:  ES:  CR0: 80050033
 CR2: 461ca000 CR3: 0002a8a2 CR4: 00350ee0
 Call Trace:
  
  dm_read_reg_func+0x37/0xc0 [amdgpu]
  generic_reg_get2+0x22/0x60 [amdgpu]
  optc1_get_crtc_scanoutpos+0x6a/0xc0 [amdgpu]
  dc_stream_get_scanoutpos+0x74/0x90 [amdgpu]
  dm_crtc_get_scanoutpos+0x82/0xf0 [amdgpu]
  amdgpu_display_get_crtc_scanoutpos+0x91/0x190 [amdgpu]
  ? dm_read_reg_func+0x37/0xc0 [amdgpu]
  amdgpu_get_vblank_counter_kms+0xb4/0x1a0 [amdgpu]
  dm_pflip_high_irq+0x213/0x2f0 [amdgpu]
  amdgpu_dm_irq_handler+0x8a/0x200 [amdgpu]
  amdgpu_irq_dispatch+0xd4/0x220 [amdgpu]
  amdgpu_ih_process+0x7f/0x110 [amdgpu]
  amdgpu_irq_handler+0x1f/0x70 [amdgpu]
  __handle_irq_event_percpu+0x46/0x1b0
  handle_irq_event+0x34/0x80
  handle_edge_irq+0x9f/0x240
  __common_interrupt+0x66/0x110
  common_interrupt+0x5c/0xd0
  asm_common_interrupt+0x22/0x40

Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 --
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 7 ---
 2 files changed, 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 6ce10fd4bb1a..5403e9399a46 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2113,12 +2113,6 @@ void dcn20_optimize_bandwidth(
if (hubbub->funcs->program_compbuf_size)
hubbub->funcs->program_compbuf_size(hubbub, 
context->bw_ctx.bw.dcn.compbuf_size_kb, true);
 
-   if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
-   dc_dmub_srv_p_state_delegate(dc,
-   true, context);
-   context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
-   }
-
dc->clk_mgr->funcs->update_clocks(
dc->clk_mgr,
context,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 0411867654dd..0e071fbc9154 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -985,18 +985,11 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
 void dcn30_prepare_bandwidth(struct dc *dc,
struct dc_state *context)
 {
-   if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
-   dc->optimized_required = true;
-   context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
-   }
-
if (dc->clk_mgr->dc_mode_softmax_enabled)
if (dc->clk_mgr->clks.dramclk_khz <= 
dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
context->bw_ctx.bw.dcn.clk.dramclk_khz > 
dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, 
dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries
 - 1].memclk_mhz);
 
dcn20_prepare_bandwidth(dc, context);
-
-   dc_dmub_srv_p_state_delegate(dc, false, context);
 }
 
-- 
2.40.1