Re: [PATCH 2/2] drm/amdkfd: Use better name for sdma queue non HWS path
Okay, I will incorporate Shaoyun's input.
Yong
From: Liu, Shaoyun
Sent: Monday, September 23, 2019 10:27 AM
To: Zhao, Yong ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdkfd: Use better name for sdma queue non HWS path
Probably rename to sdma_rlc to avoid the confusion of rlc used in
other amdgpu driver .
Regards
shaoyun.liu
On 2019-09-22 11:56 p.m., Zhao, Yong wrote:
> The old name is prone to confusion. The register offset is for a RLC queue
> rather than a SDMA engine. The value is not a base address, but a
> register offset.
>
> Change-Id: I55fb835f2105392344b1c17323bb55c03f927836
> Signed-off-by: Yong Zhao
> ---
> .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 85 +-
> .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 90 +--
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 10 +--
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 10 +--
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 86 +-
> 5 files changed, 137 insertions(+), 144 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> index c9ce1516956e..d2c0666c2798 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> @@ -70,11 +70,11 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
>return (struct v9_sdma_mqd *)mqd;
> }
>
> -static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
> +static uint32_t get_rlc_reg_offset(struct amdgpu_device *adev,
>unsigned int engine_id,
>unsigned int queue_id)
> {
> - uint32_t base[8] = {
> + uint32_t sdma_engine_reg_base[8] = {
>SOC15_REG_OFFSET(SDMA0, 0,
> mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
>SOC15_REG_OFFSET(SDMA1, 0,
> @@ -92,12 +92,11 @@ static uint32_t get_sdma_base_addr(struct amdgpu_device
> *adev,
>SOC15_REG_OFFSET(SDMA7, 0,
> mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
>};
> - uint32_t retval;
>
> - retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
> -mmSDMA0_RLC0_RB_CNTL);
> + uint32_t retval = sdma_engine_reg_base[engine_id]
> + + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
>
> - pr_debug("sdma base address: 0x%x\n", retval);
> + pr_debug("RLC register offset: 0x%x\n", retval);
>
>return retval;
> }
> @@ -107,22 +106,22 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void
> *mqd,
> {
>struct amdgpu_device *adev = get_amdgpu_device(kgd);
>struct v9_sdma_mqd *m;
> - uint32_t sdma_base_addr;
> + uint32_t rlc_reg_offset;
>unsigned long end_jiffies;
>uint32_t data;
>uint64_t data64;
>uint64_t __user *wptr64 = (uint64_t __user *)wptr;
>
>m = get_sdma_mqd(mqd);
> - sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
> + rlc_reg_offset = get_rlc_reg_offset(adev, m->sdma_engine_id,
>m->sdma_queue_id);
>
> - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
> + WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
>m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
>
>end_jiffies = msecs_to_jiffies(2000) + jiffies;
>while (true) {
> - data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
> + data = RREG32(rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
>if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
>break;
>if (time_after(jiffies, end_jiffies))
> @@ -130,41 +129,41 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void
> *mqd,
>usleep_range(500, 1000);
>}
>
> - WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
> + WREG32(rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
> m->sdmax_rlcx_doorbell_offset);
>
>data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
> ENABLE, 1);
> - WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
> - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
> - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
> + WREG32(rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
> + WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
> +
Re: [PATCH 2/2] drm/amdkfd: Use better name for sdma queue non HWS path
Probably rename to sdma_rlc to avoid the confusion of rlc used in
other amdgpu driver .
Regards
shaoyun.liu
On 2019-09-22 11:56 p.m., Zhao, Yong wrote:
> The old name is prone to confusion. The register offset is for a RLC queue
> rather than a SDMA engine. The value is not a base address, but a
> register offset.
>
> Change-Id: I55fb835f2105392344b1c17323bb55c03f927836
> Signed-off-by: Yong Zhao
> ---
> .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 85 +-
> .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 90 +--
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 10 +--
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 10 +--
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 86 +-
> 5 files changed, 137 insertions(+), 144 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> index c9ce1516956e..d2c0666c2798 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> @@ -70,11 +70,11 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
> return (struct v9_sdma_mqd *)mqd;
> }
>
> -static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
> +static uint32_t get_rlc_reg_offset(struct amdgpu_device *adev,
> unsigned int engine_id,
> unsigned int queue_id)
> {
> - uint32_t base[8] = {
> + uint32_t sdma_engine_reg_base[8] = {
> SOC15_REG_OFFSET(SDMA0, 0,
>mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
> SOC15_REG_OFFSET(SDMA1, 0,
> @@ -92,12 +92,11 @@ static uint32_t get_sdma_base_addr(struct amdgpu_device
> *adev,
> SOC15_REG_OFFSET(SDMA7, 0,
>mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
> };
> - uint32_t retval;
>
> - retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
> -mmSDMA0_RLC0_RB_CNTL);
> + uint32_t retval = sdma_engine_reg_base[engine_id]
> + + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
>
> - pr_debug("sdma base address: 0x%x\n", retval);
> + pr_debug("RLC register offset: 0x%x\n", retval);
>
> return retval;
> }
> @@ -107,22 +106,22 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void
> *mqd,
> {
> struct amdgpu_device *adev = get_amdgpu_device(kgd);
> struct v9_sdma_mqd *m;
> - uint32_t sdma_base_addr;
> + uint32_t rlc_reg_offset;
> unsigned long end_jiffies;
> uint32_t data;
> uint64_t data64;
> uint64_t __user *wptr64 = (uint64_t __user *)wptr;
>
> m = get_sdma_mqd(mqd);
> - sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
> + rlc_reg_offset = get_rlc_reg_offset(adev, m->sdma_engine_id,
> m->sdma_queue_id);
>
> - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
> + WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
> m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
>
> end_jiffies = msecs_to_jiffies(2000) + jiffies;
> while (true) {
> - data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
> + data = RREG32(rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
> if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
> break;
> if (time_after(jiffies, end_jiffies))
> @@ -130,41 +129,41 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void
> *mqd,
> usleep_range(500, 1000);
> }
>
> - WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
> + WREG32(rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
> m->sdmax_rlcx_doorbell_offset);
>
> data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
>ENABLE, 1);
> - WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
> - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
> - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
> + WREG32(rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
> + WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
> + WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
> m->sdmax_rlcx_rb_rptr_hi);
>
> - WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
> + WREG32(rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
> if (read_user_wptr(mm, wptr64, data64)) {
> - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
> + WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
> lower_32_bits(data64));
> - WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
> + WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
>
Re: [PATCH 2/2] drm/amdkfd: Use better name for sdma queue non HWS path
Series is:
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Zhao, Yong
Sent: Sunday, September 22, 2019 11:56 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhao, Yong
Subject: [PATCH 2/2] drm/amdkfd: Use better name for sdma queue non HWS path
The old name is prone to confusion. The register offset is for a RLC queue
rather than a SDMA engine. The value is not a base address, but a
register offset.
Change-Id: I55fb835f2105392344b1c17323bb55c03f927836
Signed-off-by: Yong Zhao
---
.../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 85 +-
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 90 +--
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 10 +--
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 10 +--
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 86 +-
5 files changed, 137 insertions(+), 144 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
index c9ce1516956e..d2c0666c2798 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
@@ -70,11 +70,11 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
return (struct v9_sdma_mqd *)mqd;
}
-static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
+static uint32_t get_rlc_reg_offset(struct amdgpu_device *adev,
unsigned int engine_id,
unsigned int queue_id)
{
- uint32_t base[8] = {
+ uint32_t sdma_engine_reg_base[8] = {
SOC15_REG_OFFSET(SDMA0, 0,
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
SOC15_REG_OFFSET(SDMA1, 0,
@@ -92,12 +92,11 @@ static uint32_t get_sdma_base_addr(struct amdgpu_device
*adev,
SOC15_REG_OFFSET(SDMA7, 0,
mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
};
- uint32_t retval;
- retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
- mmSDMA0_RLC0_RB_CNTL);
+ uint32_t retval = sdma_engine_reg_base[engine_id]
+ + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
- pr_debug("sdma base address: 0x%x\n", retval);
+ pr_debug("RLC register offset: 0x%x\n", retval);
return retval;
}
@@ -107,22 +106,22 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void
*mqd,
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
struct v9_sdma_mqd *m;
- uint32_t sdma_base_addr;
+ uint32_t rlc_reg_offset;
unsigned long end_jiffies;
uint32_t data;
uint64_t data64;
uint64_t __user *wptr64 = (uint64_t __user *)wptr;
m = get_sdma_mqd(mqd);
- sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+ rlc_reg_offset = get_rlc_reg_offset(adev, m->sdma_engine_id,
m->sdma_queue_id);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
end_jiffies = msecs_to_jiffies(2000) + jiffies;
while (true) {
- data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+ data = RREG32(rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
break;
if (time_after(jiffies, end_jiffies))
@@ -130,41 +129,41 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void
*mqd,
usleep_range(500, 1000);
}
- WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
m->sdmax_rlcx_doorbell_offset);
data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
ENABLE, 1);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
m->sdmax_rlcx_rb_rptr_hi);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
if (read_user_wptr(mm, wptr64, data64)) {
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
lower_32_bits(data64));
- WREG32(sdma_base
[PATCH 2/2] drm/amdkfd: Use better name for sdma queue non HWS path
The old name is prone to confusion. The register offset is for a RLC queue
rather than a SDMA engine. The value is not a base address, but a
register offset.
Change-Id: I55fb835f2105392344b1c17323bb55c03f927836
Signed-off-by: Yong Zhao
---
.../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 85 +-
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 90 +--
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 10 +--
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 10 +--
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 86 +-
5 files changed, 137 insertions(+), 144 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
index c9ce1516956e..d2c0666c2798 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
@@ -70,11 +70,11 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
return (struct v9_sdma_mqd *)mqd;
}
-static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
+static uint32_t get_rlc_reg_offset(struct amdgpu_device *adev,
unsigned int engine_id,
unsigned int queue_id)
{
- uint32_t base[8] = {
+ uint32_t sdma_engine_reg_base[8] = {
SOC15_REG_OFFSET(SDMA0, 0,
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
SOC15_REG_OFFSET(SDMA1, 0,
@@ -92,12 +92,11 @@ static uint32_t get_sdma_base_addr(struct amdgpu_device
*adev,
SOC15_REG_OFFSET(SDMA7, 0,
mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
};
- uint32_t retval;
- retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
- mmSDMA0_RLC0_RB_CNTL);
+ uint32_t retval = sdma_engine_reg_base[engine_id]
+ + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
- pr_debug("sdma base address: 0x%x\n", retval);
+ pr_debug("RLC register offset: 0x%x\n", retval);
return retval;
}
@@ -107,22 +106,22 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void
*mqd,
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
struct v9_sdma_mqd *m;
- uint32_t sdma_base_addr;
+ uint32_t rlc_reg_offset;
unsigned long end_jiffies;
uint32_t data;
uint64_t data64;
uint64_t __user *wptr64 = (uint64_t __user *)wptr;
m = get_sdma_mqd(mqd);
- sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+ rlc_reg_offset = get_rlc_reg_offset(adev, m->sdma_engine_id,
m->sdma_queue_id);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
end_jiffies = msecs_to_jiffies(2000) + jiffies;
while (true) {
- data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+ data = RREG32(rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
break;
if (time_after(jiffies, end_jiffies))
@@ -130,41 +129,41 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void
*mqd,
usleep_range(500, 1000);
}
- WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
m->sdmax_rlcx_doorbell_offset);
data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
ENABLE, 1);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
m->sdmax_rlcx_rb_rptr_hi);
- WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
if (read_user_wptr(mm, wptr64, data64)) {
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
lower_32_bits(data64));
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
upper_32_bits(data64));
} else {
- WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+ WREG32(rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
m->sdmax_rlcx_rb_rptr);
- WREG32(sdma_base_addr
