V2:
Add RLC_RLCS_FED_STATUS_0 and RLC_RLCS_FED_STATUS_1 register
offset and shift masks.
Signed-off-by: YiPeng Chai <yipeng.c...@amd.com>
Reviewed-by: Hawking Zhang <hawking.zh...@amd.com>
Reviewed-by: Tao Zhou <tao.zh...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
---
.../include/asic_reg/gc/gc_11_0_3_offset.h | 8 +++
.../include/asic_reg/gc/gc_11_0_3_sh_mask.h | 50 +++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
index 3b95a59b196c..56e00252bff8 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
@@ -3593,6 +3593,14 @@
#define regGCL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX
1
+// addressBlock: gc_rlcsdec
+// base address: 0x3b980
+#define regRLC_RLCS_FED_STATUS_0
0x4eff
+#define regRLC_RLCS_FED_STATUS_0_BASE_IDX
1
+#define regRLC_RLCS_FED_STATUS_1
0x4f00
+#define regRLC_RLCS_FED_STATUS_1_BASE_IDX
1
+
+
// addressBlock: gc_gcvml2pspdec
// base address: 0x3f900
#define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID
0x5e41
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h
index ae3ef8a9e702..658e88a8e2ac 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h
@@ -37642,6 +37642,56 @@
#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_MASK
0x00000FFCL
#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK
0x00030000L
#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_MASK
0x0FFC0000L
+//RLC_RLCS_FED_STATUS_0
+#define RLC_RLCS_FED_STATUS_0__RLC_FED_ERR__SHIFT
0x0
+#define RLC_RLCS_FED_STATUS_0__UTCL2_FED_ERR__SHIFT
0x1
+#define RLC_RLCS_FED_STATUS_0__GE_FED_ERR__SHIFT
0x2
+#define RLC_RLCS_FED_STATUS_0__CPC_FED_ERR__SHIFT
0x3
+#define RLC_RLCS_FED_STATUS_0__CPF_FED_ERR__SHIFT
0x4
+#define RLC_RLCS_FED_STATUS_0__CPG_FED_ERR__SHIFT
0x5
+#define RLC_RLCS_FED_STATUS_0__SDMA0_FED_ERR__SHIFT
0x6
+#define RLC_RLCS_FED_STATUS_0__SDMA1_FED_ERR__SHIFT
0x7
+#define RLC_RLCS_FED_STATUS_0__RLC_FED_ERR_MASK
0x00000001L
+#define RLC_RLCS_FED_STATUS_0__UTCL2_FED_ERR_MASK
0x00000002L
+#define RLC_RLCS_FED_STATUS_0__GE_FED_ERR_MASK
0x00000004L
+#define RLC_RLCS_FED_STATUS_0__CPC_FED_ERR_MASK
0x00000008L
+#define RLC_RLCS_FED_STATUS_0__CPF_FED_ERR_MASK
0x00000010L
+#define RLC_RLCS_FED_STATUS_0__CPG_FED_ERR_MASK
0x00000020L
+#define RLC_RLCS_FED_STATUS_0__SDMA0_FED_ERR_MASK
0x00000040L
+#define RLC_RLCS_FED_STATUS_0__SDMA1_FED_ERR_MASK
0x00000080L
+//RLC_RLCS_FED_STATUS_1
+#define RLC_RLCS_FED_STATUS_1__GL2C0_FED_ERR__SHIFT
0x0
+#define RLC_RLCS_FED_STATUS_1__GL2C1_FED_ERR__SHIFT
0x1
+#define RLC_RLCS_FED_STATUS_1__GL2C2_FED_ERR__SHIFT
0x2
+#define RLC_RLCS_FED_STATUS_1__GL2C3_FED_ERR__SHIFT
0x3
+#define RLC_RLCS_FED_STATUS_1__GL2C4_FED_ERR__SHIFT
0x4
+#define RLC_RLCS_FED_STATUS_1__GL2C5_FED_ERR__SHIFT
0x5
+#define RLC_RLCS_FED_STATUS_1__GL2C6_FED_ERR__SHIFT
0x6
+#define RLC_RLCS_FED_STATUS_1__GL2C7_FED_ERR__SHIFT
0x7
+#define RLC_RLCS_FED_STATUS_1__GL2C8_FED_ERR__SHIFT
0x8
+#define RLC_RLCS_FED_STATUS_1__GL2C9_FED_ERR__SHIFT
0x9
+#define RLC_RLCS_FED_STATUS_1__GL2C10_FED_ERR__SHIFT
0xa
+#define RLC_RLCS_FED_STATUS_1__GL2C11_FED_ERR__SHIFT
0xb
+#define RLC_RLCS_FED_STATUS_1__GL2C12_FED_ERR__SHIFT
0xc
+#define RLC_RLCS_FED_STATUS_1__GL2C13_FED_ERR__SHIFT
0xd
+#define RLC_RLCS_FED_STATUS_1__GL2C14_FED_ERR__SHIFT
0xe
+#define RLC_RLCS_FED_STATUS_1__GL2C15_FED_ERR__SHIFT
0xf
+#define RLC_RLCS_FED_STATUS_1__GL2C0_FED_ERR_MASK
0x00000001L
+#define RLC_RLCS_FED_STATUS_1__GL2C1_FED_ERR_MASK
0x00000002L
+#define RLC_RLCS_FED_STATUS_1__GL2C2_FED_ERR_MASK
0x00000004L
+#define RLC_RLCS_FED_STATUS_1__GL2C3_FED_ERR_MASK
0x00000008L
+#define RLC_RLCS_FED_STATUS_1__GL2C4_FED_ERR_MASK
0x00000010L
+#define RLC_RLCS_FED_STATUS_1__GL2C5_FED_ERR_MASK
0x00000020L
+#define RLC_RLCS_FED_STATUS_1__GL2C6_FED_ERR_MASK
0x00000040L
+#define RLC_RLCS_FED_STATUS_1__GL2C7_FED_ERR_MASK
0x00000080L
+#define RLC_RLCS_FED_STATUS_1__GL2C8_FED_ERR_MASK
0x00000100L
+#define RLC_RLCS_FED_STATUS_1__GL2C9_FED_ERR_MASK
0x00000200L
+#define RLC_RLCS_FED_STATUS_1__GL2C10_FED_ERR_MASK
0x00000400L
+#define RLC_RLCS_FED_STATUS_1__GL2C11_FED_ERR_MASK
0x00000800L
+#define RLC_RLCS_FED_STATUS_1__GL2C12_FED_ERR_MASK
0x00001000L
+#define RLC_RLCS_FED_STATUS_1__GL2C13_FED_ERR_MASK
0x00002000L
+#define RLC_RLCS_FED_STATUS_1__GL2C14_FED_ERR_MASK
0x00004000L
+#define RLC_RLCS_FED_STATUS_1__GL2C15_FED_ERR_MASK
0x00008000L
//RLC_CGTT_MGCG_OVERRIDE
#define RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE__SHIFT
0x0
#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT
0x1
--
2.25.1
