subject:"\[PATCH 3\/3\] drm\/amd\/display\: add missing dcn link encoder regs"

[PATCH 3/3] drm/amd/display: add missing dcn link encoder regs

2019-12-11 Thread Roman.Li

From: Roman Li 

[Why]
The earlier change: "check phy dpalt lane count config"
uses link encoder registers not defined properly.
That caused regression with mst-enabled display not
lighting up.

[How]
Add missing reg definitions.

Signed-off-by: Roman Li 
---
 .../drm/amd/display/dc/dcn10/dcn10_link_encoder.h  |  20 +++
 .../drm/amd/display/dc/dcn20/dcn20_link_encoder.h  | 180 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c  |   9 +-
 .../drm/amd/display/dc/dcn21/dcn21_link_encoder.h  |  39 +
 .../gpu/drm/amd/display/dc/dcn21/dcn21_resource.c  |  11 +-
 5 files changed, 253 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 7493a63..eb13589 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -124,6 +124,26 @@ struct dcn10_link_enc_registers {
uint32_t RDPCSTX_PHY_CNTL13;
uint32_t RDPCSTX_PHY_CNTL14;
uint32_t RDPCSTX_PHY_CNTL15;
+   uint32_t RDPCSTX_CNTL;
+   uint32_t RDPCSTX_CLOCK_CNTL;
+   uint32_t RDPCSTX_PHY_CNTL0;
+   uint32_t RDPCSTX_PHY_CNTL2;
+   uint32_t RDPCSTX_PLL_UPDATE_DATA;
+   uint32_t RDPCS_TX_CR_ADDR;
+   uint32_t RDPCS_TX_CR_DATA;
+   uint32_t DPCSTX_TX_CLOCK_CNTL;
+   uint32_t DPCSTX_TX_CNTL;
+   uint32_t RDPCSTX_INTERRUPT_CONTROL;
+   uint32_t RDPCSTX_PHY_FUSE0;
+   uint32_t RDPCSTX_PHY_FUSE1;
+   uint32_t RDPCSTX_PHY_FUSE2;
+   uint32_t RDPCSTX_PHY_FUSE3;
+   uint32_t RDPCSTX_PHY_RX_LD_VAL;
+   uint32_t DPCSTX_DEBUG_CONFIG;
+   uint32_t RDPCSTX_DEBUG_CONFIG;
+   uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
+   uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
+   uint32_t DCIO_SOFT_RESET;
/* indirect registers */
uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
index 62dfd34..8cab810 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
@@ -33,7 +33,142 @@
SRI(AUX_DPHY_TX_CONTROL, DP_AUX, id)
 
 #define UNIPHY_MASK_SH_LIST(mask_sh)\
-   LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh)
+   LE_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\
+   LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh),\
+   LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL0_XBAR_SOURCE, mask_sh),\
+   LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL1_XBAR_SOURCE, mask_sh),\
+   LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL2_XBAR_SOURCE, mask_sh),\
+   LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL3_XBAR_SOURCE, mask_sh)
+
+#define DPCS_MASK_SH_LIST(mask_sh)\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, 
mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, 
mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, 
mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, 
mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, 
mask_sh),\
+   LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9

Re: [PATCH 3/3] drm/amd/display: add missing dcn link encoder regs

2019-12-13 Thread Harry Wentland

Series is
Reviewed-by: Harry Wentland 

Harry

On 2019-12-11 10:45 a.m., roman...@amd.com wrote:
> From: Roman Li 
> 
> [Why]
> The earlier change: "check phy dpalt lane count config"
> uses link encoder registers not defined properly.
> That caused regression with mst-enabled display not
> lighting up.
> 
> [How]
> Add missing reg definitions.
> 
> Signed-off-by: Roman Li 
> ---
>  .../drm/amd/display/dc/dcn10/dcn10_link_encoder.h  |  20 +++
>  .../drm/amd/display/dc/dcn20/dcn20_link_encoder.h  | 180 
> -
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c  |   9 +-
>  .../drm/amd/display/dc/dcn21/dcn21_link_encoder.h  |  39 +
>  .../gpu/drm/amd/display/dc/dcn21/dcn21_resource.c  |  11 +-
>  5 files changed, 253 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 
> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
> index 7493a63..eb13589 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
> @@ -124,6 +124,26 @@ struct dcn10_link_enc_registers {
>   uint32_t RDPCSTX_PHY_CNTL13;
>   uint32_t RDPCSTX_PHY_CNTL14;
>   uint32_t RDPCSTX_PHY_CNTL15;
> + uint32_t RDPCSTX_CNTL;
> + uint32_t RDPCSTX_CLOCK_CNTL;
> + uint32_t RDPCSTX_PHY_CNTL0;
> + uint32_t RDPCSTX_PHY_CNTL2;
> + uint32_t RDPCSTX_PLL_UPDATE_DATA;
> + uint32_t RDPCS_TX_CR_ADDR;
> + uint32_t RDPCS_TX_CR_DATA;
> + uint32_t DPCSTX_TX_CLOCK_CNTL;
> + uint32_t DPCSTX_TX_CNTL;
> + uint32_t RDPCSTX_INTERRUPT_CONTROL;
> + uint32_t RDPCSTX_PHY_FUSE0;
> + uint32_t RDPCSTX_PHY_FUSE1;
> + uint32_t RDPCSTX_PHY_FUSE2;
> + uint32_t RDPCSTX_PHY_FUSE3;
> + uint32_t RDPCSTX_PHY_RX_LD_VAL;
> + uint32_t DPCSTX_DEBUG_CONFIG;
> + uint32_t RDPCSTX_DEBUG_CONFIG;
> + uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
> + uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
> + uint32_t DCIO_SOFT_RESET;
>   /* indirect registers */
>   uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
>   uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h 
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
> index 62dfd34..8cab810 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
> @@ -33,7 +33,142 @@
>   SRI(AUX_DPHY_TX_CONTROL, DP_AUX, id)
>  
>  #define UNIPHY_MASK_SH_LIST(mask_sh)\
> - LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh)
> + LE_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\
> + LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh),\
> + LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL0_XBAR_SOURCE, mask_sh),\
> + LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL1_XBAR_SOURCE, mask_sh),\
> + LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL2_XBAR_SOURCE, mask_sh),\
> + LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL3_XBAR_SOURCE, mask_sh)
> +
> +#define DPCS_MASK_SH_LIST(mask_sh)\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, 
> mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, 
> mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, 
> mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PH

[PATCH 3/3] drm/amd/display: add missing dcn link encoder regs

Re: [PATCH 3/3] drm/amd/display: add missing dcn link encoder regs

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