[PATCH 3/3] drm/amd/powerplay: implement stop dpm task for vega10.
Change-Id: I19202f1e54ce6a1b8b54aacbc0d42dbba7605662
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 97 ++
.../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 23 +
.../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h | 1 +
.../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 2 +-
.../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h | 1 +
5 files changed, 123 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 5e3e89b..68eae52 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -2420,6 +2420,26 @@ static int vega10_enable_thermal_protection(struct
pp_hwmgr *hwmgr)
return 0;
}
+static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
+{
+ struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+
+ if (data->smu_features[GNLD_THERMAL].supported) {
+ if (!data->smu_features[GNLD_THERMAL].enabled)
+ pr_info("THERMAL Feature Already disabled!");
+
+ PP_ASSERT_WITH_CODE(
+ !vega10_enable_smc_features(hwmgr->smumgr,
+ false,
+
data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
+ "disable THERMAL Feature Failed!",
+ return -1);
+ data->smu_features[GNLD_THERMAL].enabled = false;
+ }
+
+ return 0;
+}
+
static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data =
@@ -2498,6 +2518,37 @@ static int vega10_enable_deep_sleep_master_switch(struct
pp_hwmgr *hwmgr)
return 0;
}
+static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
+{
+ struct vega10_hwmgr *data =
+ (struct vega10_hwmgr *)(hwmgr->backend);
+ uint32_t i, feature_mask = 0;
+
+
+ if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ true,
data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
+ "Attempt to Enable LED DPM feature Failed!", return -EINVAL);
+ data->smu_features[GNLD_LED_DISPLAY].enabled = true;
+ }
+
+ for (i = 0; i < GNLD_DPM_MAX; i++) {
+ if (data->smu_features[i].smu_feature_bitmap & bitmap) {
+ if (data->smu_features[i].supported) {
+ if (data->smu_features[i].enabled) {
+ feature_mask |= data->smu_features[i].
+ smu_feature_bitmap;
+ data->smu_features[i].enabled = false;
+ }
+ }
+ }
+ }
+
+ vega10_enable_smc_features(hwmgr->smumgr, false, feature_mask);
+
+ return 0;
+}
+
/**
* @brief Tell SMC to enabled the supported DPMs.
*
@@ -4356,11 +4407,55 @@ static int vega10_check_states_equal(struct pp_hwmgr
*hwmgr,
return is_update_required;
}
+static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
+{
+ int tmp_result, result = 0;
+
+ tmp_result = (vega10_is_dpm_running(hwmgr)) ? 0 : -1;
+ PP_ASSERT_WITH_CODE(tmp_result == 0,
+ "DPM is not running right now, no need to disable DPM!",
+ return 0);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ThermalController))
+ vega10_disable_thermal_protection(hwmgr);
+
+ tmp_result = vega10_disable_power_containment(hwmgr);
+ PP_ASSERT_WITH_CODE((tmp_result == 0),
+ "Failed to disable power containment!", result =
tmp_result);
+
+ tmp_result = vega10_avfs_enable(hwmgr, false);
+ PP_ASSERT_WITH_CODE((tmp_result == 0),
+ "Failed to disable AVFS!", result = tmp_result);
+
+ tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES);
+ PP_ASSERT_WITH_CODE((tmp_result == 0),
+ "Failed to stop DPM!", result = tmp_result);
+
+ return result;
+}
+
+static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
+{
+ struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ int result;
+
+ result = vega10_disable_dpm_tasks(hwmgr);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "[disable_dpm_tasks] Failed to disable DPM!",
+ );
+ data->water_marks_bitmap &= ~(WaterMarksLoaded);
+
+ return result;
+}
+
+
static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
.backend_init = vega10_hwmgr_backend_init,
.backend_fini = v
RE: [PATCH 3/3] drm/amd/powerplay: implement stop dpm task for vega10.
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Friday, April 28, 2017 1:20 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 3/3] drm/amd/powerplay: implement stop dpm task for
> vega10.
>
> Change-Id: I19202f1e54ce6a1b8b54aacbc0d42dbba7605662
> Signed-off-by: Rex Zhu
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 97
> ++
> .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 23 +
> .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h | 1 +
> .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 2 +-
> .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h | 1 +
> 5 files changed, 123 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 5e3e89b..68eae52 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -2420,6 +2420,26 @@ static int
> vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> +static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
> +{
> + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr-
> >backend);
> +
> + if (data->smu_features[GNLD_THERMAL].supported) {
> + if (!data->smu_features[GNLD_THERMAL].enabled)
> + pr_info("THERMAL Feature Already disabled!");
> +
> + PP_ASSERT_WITH_CODE(
> + !vega10_enable_smc_features(hwmgr-
> >smumgr,
> + false,
> + data-
> >smu_features[GNLD_THERMAL].smu_feature_bitmap),
> + "disable THERMAL Feature Failed!",
> + return -1);
> + data->smu_features[GNLD_THERMAL].enabled = false;
> + }
> +
> + return 0;
> +}
> +
> static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
> {
> struct vega10_hwmgr *data =
> @@ -2498,6 +2518,37 @@ static int
> vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> +static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
> +{
> + struct vega10_hwmgr *data =
> + (struct vega10_hwmgr *)(hwmgr->backend);
> + uint32_t i, feature_mask = 0;
> +
> +
> + if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
> +
> PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr-
> >smumgr,
> + true, data-
> >smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
> + "Attempt to Enable LED DPM feature Failed!", return -
> EINVAL);
> + data->smu_features[GNLD_LED_DISPLAY].enabled = true;
> + }
> +
> + for (i = 0; i < GNLD_DPM_MAX; i++) {
> + if (data->smu_features[i].smu_feature_bitmap & bitmap) {
> + if (data->smu_features[i].supported) {
> + if (data->smu_features[i].enabled) {
> + feature_mask |= data-
> >smu_features[i].
> +
> smu_feature_bitmap;
> + data->smu_features[i].enabled =
> false;
> + }
> + }
> + }
> + }
> +
> + vega10_enable_smc_features(hwmgr->smumgr, false,
> feature_mask);
> +
> + return 0;
> +}
> +
> /**
> * @brief Tell SMC to enabled the supported DPMs.
> *
> @@ -4356,11 +4407,55 @@ static int vega10_check_states_equal(struct
> pp_hwmgr *hwmgr,
> return is_update_required;
> }
>
> +static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
> +{
> + int tmp_result, result = 0;
> +
> + tmp_result = (vega10_is_dpm_running(hwmgr)) ? 0 : -1;
> + PP_ASSERT_WITH_CODE(tmp_result == 0,
> + "DPM is not running right now, no need to disable
> DPM!",
> + return 0);
> +
> + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> + PHM_PlatformCaps_ThermalController))
> + vega10_disable_thermal_protection(hwmgr);
> +
> + tmp_result = vega10_disable_power_containment(hwmgr);
> + PP_ASSERT_WITH_CODE((tmp_result == 0),
> + "Failed to disable power containment!", result =
> tmp_result);
> +
> + tmp_result = vega10_avfs_enable(h
