Re: [PATCH 3/6] drm/amdgpu: add get_clockgating callback for soc15

2017-03-24 Thread William Lewis 


On 03/24/17 00:47, Huang Rui wrote:
> Signed-off-by: Huang Rui 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |  3 +++
>   drivers/gpu/drm/amd/amdgpu/soc15.c | 34 
> ++
>   2 files changed, 37 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 743a852..fef89c0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -55,7 +55,10 @@ static const struct cg_flag_name clocks[] = {
>   {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock 
> Gating"},
>   {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
>   {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
> + {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Managment Medium Grain Clock 
> Gating"},
> + {AMD_CG_SUPPORT_DRM_LS, "Digital Right Managment Light Sleep"},
s/Managment/Management/
>   {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
> + {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
>   {0, NULL},
>   };
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index e37c1ff..dd70984 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -782,6 +782,39 @@ static int soc15_common_set_clockgating_state(void 
> *handle,
>   return 0;
>   }
>   
> +static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
> +{
> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + int data;
> +
> + nbio_v6_1_get_clockgating_state(adev, flags);
> +
> + /* AMD_CG_SUPPORT_HDP_LS */
> + data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
> + if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
> + *flags |= AMD_CG_SUPPORT_HDP_LS;
> +
> + /* AMD_CG_SUPPORT_DRM_MGCG */
> + data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_CGTT_DRM_CLK_CTRL0));
> + if (!(data & MP0_SMN_CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
> + *flags |= AMD_CG_SUPPORT_DRM_MGCG;
> +
> + /* AMD_CG_SUPPORT_DRM_LS */
> + data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_DRM_LIGHT_SLEEP_CTRL));
> + if (data & MP0_SMN_DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK)
> + *flags |= AMD_CG_SUPPORT_DRM_LS;
> +
> + /* AMD_CG_SUPPORT_ROM_MGCG */
> + data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
> + if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
> + *flags |= AMD_CG_SUPPORT_ROM_MGCG;
> +
> + /* AMD_CG_SUPPORT_DF_MGCG */
> + data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
> + if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
> + *flags |= AMD_CG_SUPPORT_DF_MGCG;
> +}
> +
>   static int soc15_common_set_powergating_state(void *handle,
>   enum amd_powergating_state state)
>   {
> @@ -804,4 +837,5 @@ const struct amd_ip_funcs soc15_common_ip_funcs = {
>   .soft_reset = soc15_common_soft_reset,
>   .set_clockgating_state = soc15_common_set_clockgating_state,
>   .set_powergating_state = soc15_common_set_powergating_state,
> + .get_clockgating_state= soc15_common_get_clockgating_state,
>   };

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[PATCH 3/6] drm/amdgpu: add get_clockgating callback for soc15

2017-03-23 Thread Huang Rui 
Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |  3 +++
 drivers/gpu/drm/amd/amdgpu/soc15.c | 34 ++
 2 files changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 743a852..fef89c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -55,7 +55,10 @@ static const struct cg_flag_name clocks[] = {
{AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock 
Gating"},
{AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
{AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
+   {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Managment Medium Grain Clock 
Gating"},
+   {AMD_CG_SUPPORT_DRM_LS, "Digital Right Managment Light Sleep"},
{AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
+   {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
{0, NULL},
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index e37c1ff..dd70984 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -782,6 +782,39 @@ static int soc15_common_set_clockgating_state(void *handle,
return 0;
 }
 
+static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   int data;
+
+   nbio_v6_1_get_clockgating_state(adev, flags);
+
+   /* AMD_CG_SUPPORT_HDP_LS */
+   data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
+   if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
+   *flags |= AMD_CG_SUPPORT_HDP_LS;
+
+   /* AMD_CG_SUPPORT_DRM_MGCG */
+   data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_CGTT_DRM_CLK_CTRL0));
+   if (!(data & MP0_SMN_CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
+   *flags |= AMD_CG_SUPPORT_DRM_MGCG;
+
+   /* AMD_CG_SUPPORT_DRM_LS */
+   data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_DRM_LIGHT_SLEEP_CTRL));
+   if (data & MP0_SMN_DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK)
+   *flags |= AMD_CG_SUPPORT_DRM_LS;
+
+   /* AMD_CG_SUPPORT_ROM_MGCG */
+   data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
+   if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
+   *flags |= AMD_CG_SUPPORT_ROM_MGCG;
+
+   /* AMD_CG_SUPPORT_DF_MGCG */
+   data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
+   if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
+   *flags |= AMD_CG_SUPPORT_DF_MGCG;
+}
+
 static int soc15_common_set_powergating_state(void *handle,
enum amd_powergating_state state)
 {
@@ -804,4 +837,5 @@ const struct amd_ip_funcs soc15_common_ip_funcs = {
.soft_reset = soc15_common_soft_reset,
.set_clockgating_state = soc15_common_set_clockgating_state,
.set_powergating_state = soc15_common_set_powergating_state,
+   .get_clockgating_state= soc15_common_get_clockgating_state,
 };
-- 
2.7.4

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