[PATCH 4/5] drm/amd/display: Delete old implementation of bw_calcs_data_update_from_pplib
From: Rex Zhu
this function is copied from dce112. it is not for AI/RV.
driver need to re-implement this function.
Signed-off-by: Rex Zhu
---
.../amd/display/dc/dce120/dce120_resource.c | 123 +-
1 file changed, 1 insertion(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 13c388a608c4..1126dc56e407 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -26,7 +26,6 @@
#include "dm_services.h"
-
#include "stream_encoder.h"
#include "resource.h"
#include "include/irq_service_interface.h"
@@ -691,127 +690,7 @@ static const struct resource_funcs dce120_res_pool_funcs
= {
static void bw_calcs_data_update_from_pplib(struct dc *dc)
{
- struct dm_pp_clock_levels_with_latency eng_clks = {0};
- struct dm_pp_clock_levels_with_latency mem_clks = {0};
- struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
- int i;
- unsigned int clk;
- unsigned int latency;
-
- /*do system clock*/
- if (!dm_pp_get_clock_levels_by_type_with_latency(
- dc->ctx,
- DM_PP_CLOCK_TYPE_ENGINE_CLK,
- _clks) || eng_clks.num_levels == 0) {
-
- eng_clks.num_levels = 8;
- clk = 30;
-
- for (i = 0; i < eng_clks.num_levels; i++) {
- eng_clks.data[i].clocks_in_khz = clk;
- clk += 10;
- }
- }
-
- /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
- dc->bw_vbios->high_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
- dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
- dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
- dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
- dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
- dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
- dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
- dc->bw_vbios->low_sclk = bw_frc_to_fixed(
- eng_clks.data[0].clocks_in_khz, 1000);
-
- /*do memory clock*/
- if (!dm_pp_get_clock_levels_by_type_with_latency(
- dc->ctx,
- DM_PP_CLOCK_TYPE_MEMORY_CLK,
- _clks) || mem_clks.num_levels == 0) {
-
- mem_clks.num_levels = 3;
- clk = 25;
- latency = 45;
-
- for (i = 0; i < eng_clks.num_levels; i++) {
- mem_clks.data[i].clocks_in_khz = clk;
- mem_clks.data[i].latency_in_us = latency;
- clk += 50;
- latency -= 5;
- }
-
- }
-
- /* we don't need to call PPLIB for validation clock since they
-* also give us the highest sclk and highest mclk (UMA clock).
-* ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
-* YCLK = UMACLK*m_memoryTypeMultiplier
-*/
- dc->bw_vbios->low_yclk = bw_frc_to_fixed(
- mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
- dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
- mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz *
MEMORY_TYPE_MULTIPLIER,
- 1000);
- dc->bw_vbios->high_yclk = bw_frc_to_fixed(
- mem_clks.data[mem_clks.num_levels-1].clocks_in_khz *
MEMORY_TYPE_MULTIPLIER,
- 1000);
-
- /* Now notify PPLib/SMU about which Watermarks sets they should select
-* depending on DPM state they are in. And update BW MGR GFX Engine and
-* Memory clock member variables for Watermarks calculations for each
-* Watermark Set
-*/
- clk_ranges.num_wm_sets = 4;
- clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
- clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
- eng_clks.data[0].clocks_in_khz;
- clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
- eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz -
1;
- clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz =
- mem_clks.data[0].clocks_in_khz;
- clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
-
Re: [PATCH 4/5] drm/amd/display: Delete old implementation of bw_calcs_data_update_from_pplib
On Mon, Jun 18, 2018 at 7:18 AM, Rex Zhu wrote:
> this function is copied from dce112. it is not for AI/RV.
> driver need to re-implement this function.
Maybe it's similar enough to be ok for now? What's better? Harry?
Alex
>
> Signed-off-by: Rex Zhu
> ---
> .../drm/amd/display/dc/dce120/dce120_resource.c| 123
> +
> 1 file changed, 1 insertion(+), 122 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
> b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
> index 2d58dac..450f7ec 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
> @@ -26,7 +26,6 @@
>
> #include "dm_services.h"
>
> -
> #include "stream_encoder.h"
> #include "resource.h"
> #include "include/irq_service_interface.h"
> @@ -691,127 +690,7 @@ static void dce120_destroy_resource_pool(struct
> resource_pool **pool)
>
> static void bw_calcs_data_update_from_pplib(struct dc *dc)
> {
> - struct dm_pp_clock_levels_with_latency eng_clks = {0};
> - struct dm_pp_clock_levels_with_latency mem_clks = {0};
> - struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
> - int i;
> - unsigned int clk;
> - unsigned int latency;
> -
> - /*do system clock*/
> - if (!dm_pp_get_clock_levels_by_type_with_latency(
> - dc->ctx,
> - DM_PP_CLOCK_TYPE_ENGINE_CLK,
> - _clks) || eng_clks.num_levels == 0) {
> -
> - eng_clks.num_levels = 8;
> - clk = 30;
> -
> - for (i = 0; i < eng_clks.num_levels; i++) {
> - eng_clks.data[i].clocks_in_khz = clk;
> - clk += 10;
> - }
> - }
> -
> - /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
> - dc->bw_vbios->high_sclk = bw_frc_to_fixed(
> - eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
> - dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
> - eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
> - dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
> - eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
> - dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
> - eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
> - dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
> - eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
> - dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
> - eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
> - dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
> - eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
> - dc->bw_vbios->low_sclk = bw_frc_to_fixed(
> - eng_clks.data[0].clocks_in_khz, 1000);
> -
> - /*do memory clock*/
> - if (!dm_pp_get_clock_levels_by_type_with_latency(
> - dc->ctx,
> - DM_PP_CLOCK_TYPE_MEMORY_CLK,
> - _clks) || mem_clks.num_levels == 0) {
> -
> - mem_clks.num_levels = 3;
> - clk = 25;
> - latency = 45;
> -
> - for (i = 0; i < eng_clks.num_levels; i++) {
> - mem_clks.data[i].clocks_in_khz = clk;
> - mem_clks.data[i].latency_in_us = latency;
> - clk += 50;
> - latency -= 5;
> - }
> -
> - }
> -
> - /* we don't need to call PPLIB for validation clock since they
> -* also give us the highest sclk and highest mclk (UMA clock).
> -* ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
> -* YCLK = UMACLK*m_memoryTypeMultiplier
> -*/
> - dc->bw_vbios->low_yclk = bw_frc_to_fixed(
> - mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
> 1000);
> - dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
> - mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz *
> MEMORY_TYPE_MULTIPLIER,
> - 1000);
> - dc->bw_vbios->high_yclk = bw_frc_to_fixed(
> - mem_clks.data[mem_clks.num_levels-1].clocks_in_khz *
> MEMORY_TYPE_MULTIPLIER,
> - 1000);
> -
> - /* Now notify PPLib/SMU about which Watermarks sets they should select
> -* depending on DPM state they are in. And update BW MGR GFX Engine
> and
> -* Memory clock member variables for Watermarks calculations for each
> -* Watermark Set
> -*/
> - clk_ranges.num_wm_sets = 4;
> - clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
> - clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
> - eng_clks.data[0].clocks_in_khz;
> -
[PATCH 4/5] drm/amd/display: Delete old implementation of bw_calcs_data_update_from_pplib
this function is copied from dce112. it is not for AI/RV.
driver need to re-implement this function.
Signed-off-by: Rex Zhu
---
.../drm/amd/display/dc/dce120/dce120_resource.c| 123 +
1 file changed, 1 insertion(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 2d58dac..450f7ec 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -26,7 +26,6 @@
#include "dm_services.h"
-
#include "stream_encoder.h"
#include "resource.h"
#include "include/irq_service_interface.h"
@@ -691,127 +690,7 @@ static void dce120_destroy_resource_pool(struct
resource_pool **pool)
static void bw_calcs_data_update_from_pplib(struct dc *dc)
{
- struct dm_pp_clock_levels_with_latency eng_clks = {0};
- struct dm_pp_clock_levels_with_latency mem_clks = {0};
- struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
- int i;
- unsigned int clk;
- unsigned int latency;
-
- /*do system clock*/
- if (!dm_pp_get_clock_levels_by_type_with_latency(
- dc->ctx,
- DM_PP_CLOCK_TYPE_ENGINE_CLK,
- _clks) || eng_clks.num_levels == 0) {
-
- eng_clks.num_levels = 8;
- clk = 30;
-
- for (i = 0; i < eng_clks.num_levels; i++) {
- eng_clks.data[i].clocks_in_khz = clk;
- clk += 10;
- }
- }
-
- /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
- dc->bw_vbios->high_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
- dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
- dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
- dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
- dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
- dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
- dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
- eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
- dc->bw_vbios->low_sclk = bw_frc_to_fixed(
- eng_clks.data[0].clocks_in_khz, 1000);
-
- /*do memory clock*/
- if (!dm_pp_get_clock_levels_by_type_with_latency(
- dc->ctx,
- DM_PP_CLOCK_TYPE_MEMORY_CLK,
- _clks) || mem_clks.num_levels == 0) {
-
- mem_clks.num_levels = 3;
- clk = 25;
- latency = 45;
-
- for (i = 0; i < eng_clks.num_levels; i++) {
- mem_clks.data[i].clocks_in_khz = clk;
- mem_clks.data[i].latency_in_us = latency;
- clk += 50;
- latency -= 5;
- }
-
- }
-
- /* we don't need to call PPLIB for validation clock since they
-* also give us the highest sclk and highest mclk (UMA clock).
-* ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
-* YCLK = UMACLK*m_memoryTypeMultiplier
-*/
- dc->bw_vbios->low_yclk = bw_frc_to_fixed(
- mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
- dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
- mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz *
MEMORY_TYPE_MULTIPLIER,
- 1000);
- dc->bw_vbios->high_yclk = bw_frc_to_fixed(
- mem_clks.data[mem_clks.num_levels-1].clocks_in_khz *
MEMORY_TYPE_MULTIPLIER,
- 1000);
-
- /* Now notify PPLib/SMU about which Watermarks sets they should select
-* depending on DPM state they are in. And update BW MGR GFX Engine and
-* Memory clock member variables for Watermarks calculations for each
-* Watermark Set
-*/
- clk_ranges.num_wm_sets = 4;
- clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
- clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
- eng_clks.data[0].clocks_in_khz;
- clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
- eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz -
1;
- clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz =
- mem_clks.data[0].clocks_in_khz;
- clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
- mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
-
