RE: [PATCH 5/5] drm/amd/sriov skip vcn powergating and dec_ring_test
Reviewed-by: Leo Liu
-Original Message-
From: Jack Zhang
Sent: July 15, 2020 1:50 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Jack (Jian) ; Zhang, Hawking
; Liu, Leo
Subject: [PATCH 5/5] drm/amd/sriov skip vcn powergating and dec_ring_test
1.Skip decode_ring test in VF, because VCN in SRIOV does not support direct
register read/write.
2.Skip powergating configuration in hw fini because
VCN3.0 SRIOV doesn't support powergating.
V2: delete unneccessary white lines and refine implementation.
Signed-off-by: Jack Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 21 -
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 15ff30c53e24..92a55e40bc48 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -421,6 +421,10 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
+ /* VCN in SRIOV does not support direct register read/write */
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 3);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 0a0ca10bf55b..910a4a32ff78 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -354,11 +354,13 @@ static int vcn_v3_0_hw_fini(void *handle)
ring = &adev->vcn.inst[i].ring_dec;
- if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, mmUVD_STATUS)))
- vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
-
+ if (!amdgpu_sriov_vf(adev)) {
+ if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+ (adev->vcn.cur_state !=
AMD_PG_STATE_GATE &&
+RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
+ vcn_v3_0_set_powergating_state(adev,
AMD_PG_STATE_GATE);
+ }
+ }
ring->sched.ready = false;
for (j = 0; j < adev->vcn.num_enc_rings; ++j) { @@ -1861,6
+1863,15 @@ static int vcn_v3_0_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
+ /* for SRIOV, guest should not control VCN Power-gating
+* MMSCH FW should control Power-gating and clock-gating
+* guest should avoid touching CGC and PG
+*/
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+ return 0;
+ }
+
if(state == adev->vcn.cur_state)
return 0;
--
2.17.1
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[PATCH 5/5] drm/amd/sriov skip vcn powergating and dec_ring_test
1.Skip decode_ring test in VF, because VCN in SRIOV does not
support direct register read/write.
2.Skip powergating configuration in hw fini because
VCN3.0 SRIOV doesn't support powergating.
V2: delete unneccessary white lines and refine implementation.
Signed-off-by: Jack Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 21 -
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 15ff30c53e24..92a55e40bc48 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -421,6 +421,10 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
+ /* VCN in SRIOV does not support direct register read/write */
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 3);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 0a0ca10bf55b..910a4a32ff78 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -354,11 +354,13 @@ static int vcn_v3_0_hw_fini(void *handle)
ring = &adev->vcn.inst[i].ring_dec;
- if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, mmUVD_STATUS)))
- vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
-
+ if (!amdgpu_sriov_vf(adev)) {
+ if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+ (adev->vcn.cur_state !=
AMD_PG_STATE_GATE &&
+RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
+ vcn_v3_0_set_powergating_state(adev,
AMD_PG_STATE_GATE);
+ }
+ }
ring->sched.ready = false;
for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
@@ -1861,6 +1863,15 @@ static int vcn_v3_0_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
+ /* for SRIOV, guest should not control VCN Power-gating
+* MMSCH FW should control Power-gating and clock-gating
+* guest should avoid touching CGC and PG
+*/
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+ return 0;
+ }
+
if(state == adev->vcn.cur_state)
return 0;
--
2.17.1
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Re: [PATCH 5/5] drm/amd/sriov skip vcn powergating and dec_ring_test
On 2020-07-13 10:47 p.m., Jack Zhang wrote:
1.Skip decode_ring test in VF, because VCN in SRIOV does not
support direct register read/write.
2.Skip powergating configuration in hw fini because
VCN3.0 SRIOV doesn't support powergating.
Signed-off-by: Jack Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 17 +++--
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 15ff30c53e24..92a55e40bc48 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -421,6 +421,10 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
+ /* VCN in SRIOV does not support direct register read/write */
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 3);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 0a0ca10bf55b..8e5de9ed64f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -354,10 +354,13 @@ static int vcn_v3_0_hw_fini(void *handle)
ring = &adev->vcn.inst[i].ring_dec;
- if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+ if (amdgpu_sriov_vf(adev)) {
+ /* for SRIOV, VM does not control PG state */
+ }
It looks odd to me that only comments inside the bracket. Can you
combine it to the "else if" line?
else if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, mmUVD_STATUS)))
+ RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ }
ring->sched.ready = false;
@@ -1208,6 +1211,7 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
return 0;
}
+
Why do you add an empty line here?
Regards,
Leo
static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
{
int i, j;
@@ -1861,6 +1865,15 @@ static int vcn_v3_0_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
+ /* for SRIOV, guest should not control VCN Power-gating
+* MMSCH FW should control Power-gating and clock-gating
+* guest should avoid touching CGC and PG
+*/
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+ return 0;
+ }
+
if(state == adev->vcn.cur_state)
return 0;
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[PATCH 5/5] drm/amd/sriov skip vcn powergating and dec_ring_test
1.Skip decode_ring test in VF, because VCN in SRIOV does not
support direct register read/write.
2.Skip powergating configuration in hw fini because
VCN3.0 SRIOV doesn't support powergating.
Signed-off-by: Jack Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 17 +++--
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 15ff30c53e24..92a55e40bc48 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -421,6 +421,10 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
+ /* VCN in SRIOV does not support direct register read/write */
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 3);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 0a0ca10bf55b..8e5de9ed64f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -354,10 +354,13 @@ static int vcn_v3_0_hw_fini(void *handle)
ring = &adev->vcn.inst[i].ring_dec;
- if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+ if (amdgpu_sriov_vf(adev)) {
+ /* for SRIOV, VM does not control PG state */
+ } else if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, mmUVD_STATUS)))
+ RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ }
ring->sched.ready = false;
@@ -1208,6 +1211,7 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
return 0;
}
+
static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
{
int i, j;
@@ -1861,6 +1865,15 @@ static int vcn_v3_0_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
+ /* for SRIOV, guest should not control VCN Power-gating
+* MMSCH FW should control Power-gating and clock-gating
+* guest should avoid touching CGC and PG
+*/
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+ return 0;
+ }
+
if(state == adev->vcn.cur_state)
return 0;
--
2.17.1
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