RE: [PATCH Review 1/1] drm/amdgpu: initialize umc ras function

2021-07-08 Thread Chen, Guchun 
[Public]

+   {24, 8, 2, 18}, {15, 31, 5, 21},
+   {19, 3, 9, 25}, {28, 12, 6, 22},

The coding style should be corrected. With this fixed, the patch is:
Reviewed-by: Guchun Chen 

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Stanley.Yang
Sent: Thursday, July 8, 2021 11:28 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Yang, Stanley 
; Clements, John ; Zhang, Hawking 

Subject: [PATCH Review 1/1] drm/amdgpu: initialize umc ras function

From: John Clements 

support umc ras function initialization for aldebaran

Change-Id: I84155d4d3eaae86a8c1bd2331b1964946c47f6da
Signed-off-by: John Clements 
Signed-off-by: Stanley.Yang 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 13 +  
drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 15 +++  
drivers/gpu/drm/amd/amdgpu/umc_v6_7.h | 12 
 3 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 3332c9e0a4e2..42d7244573b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -53,6 +53,7 @@
 #include "mmhub_v1_7.h"
 #include "umc_v6_1.h"
 #include "umc_v6_0.h"
+#include "umc_v6_7.h"
 #include "hdp_v4_0.h"
 
 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
@@ -1163,6 +1164,18 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device 
*adev)
adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
break;
+   case CHIP_ALDEBARAN:
+   adev->umc.max_ras_err_cnt_per_query = 
UMC_V6_7_TOTAL_CHANNEL_NUM;
+   adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
+   adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
+   adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
+   if (!adev->gmc.xgmi.connected_to_cpu)
+   adev->umc.ras_funcs = &umc_v6_7_ras_funcs;
+   if (1 & adev->smuio.funcs->get_die_id(adev))
+   adev->umc.channel_idx_tbl = 
&umc_v6_7_channel_idx_tbl_first[0][0];
+   else
+   adev->umc.channel_idx_tbl = 
&umc_v6_7_channel_idx_tbl_second[0][0];
+   break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index 3a8f787374c0..7da12110425c 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -28,6 +28,21 @@
 #include "umc/umc_6_7_0_offset.h"
 #include "umc/umc_6_7_0_sh_mask.h"
 
+const uint32_t
+   
umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM]
 = {
+   {28, 12, 6, 22},{19, 3, 9, 25},
+   {20, 4, 30, 14},{11, 27, 1, 17},
+   {24, 8, 2, 18}, {15, 31, 5, 21},
+   {16, 0, 26, 10},{7, 23, 29, 13}
+};
+const uint32_t
+   
umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM]
 = {
+   {19, 3, 9, 25}, {28, 12, 6, 22},
+   {11, 27, 1, 17},{20, 4, 30, 14},
+   {15, 31, 5, 21},{24, 8, 2, 18},
+   {7, 23, 29, 13},{16, 0, 26, 10}
+};
+
 static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev,
  uint32_t umc_inst,
  uint32_t ch_inst)
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h 
b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
index 4eb85f247e96..aa282687e0e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
@@ -32,6 +32,18 @@
 
 #define UMC_V6_7_INST_DIST 0x4
 
+/* number of umc channel instance with memory map register access */
+#define UMC_V6_7_CHANNEL_INSTANCE_NUM  4
+/* number of umc instance with memory map register access */
+#define UMC_V6_7_UMC_INSTANCE_NUM  8
+/* total channel instances in one umc block */
+#define UMC_V6_7_TOTAL_CHANNEL_NUM (UMC_V6_7_CHANNEL_INSTANCE_NUM * 
UMC_V6_7_UMC_INSTANCE_NUM)
+/* UMC regiser per channel offset */
+#define UMC_V6_7_PER_CHANNEL_OFFSET0x400
 extern const struct amdgpu_umc_ras_funcs umc_v6_7_ras_funcs;
+extern const uint32_t
+   
+umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHA
+NNEL_INSTANCE_NUM];
+extern const uint32_t
+   
+umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHAN
+NEL_INSTANCE_NUM];
 
 #endif
--
2.17.1

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RE: [PATCH Review 1/1] drm/amdgpu: initialize umc ras function

2021-07-08 Thread Clements, John 
[AMD Official Use Only]

Reviewed-by: John Clements 

-Original Message-
From: Stanley.Yang  
Sent: Thursday, July 8, 2021 11:28 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Hawking 
; Clements, John ; Clements, John 
; Yang, Stanley 
Subject: [PATCH Review 1/1] drm/amdgpu: initialize umc ras function

From: John Clements 

support umc ras function initialization for aldebaran

Change-Id: I84155d4d3eaae86a8c1bd2331b1964946c47f6da
Signed-off-by: John Clements 
Signed-off-by: Stanley.Yang 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 13 +  
drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 15 +++  
drivers/gpu/drm/amd/amdgpu/umc_v6_7.h | 12 
 3 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 3332c9e0a4e2..42d7244573b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -53,6 +53,7 @@
 #include "mmhub_v1_7.h"
 #include "umc_v6_1.h"
 #include "umc_v6_0.h"
+#include "umc_v6_7.h"
 #include "hdp_v4_0.h"
 
 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
@@ -1163,6 +1164,18 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device 
*adev)
adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
break;
+   case CHIP_ALDEBARAN:
+   adev->umc.max_ras_err_cnt_per_query = 
UMC_V6_7_TOTAL_CHANNEL_NUM;
+   adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
+   adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
+   adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
+   if (!adev->gmc.xgmi.connected_to_cpu)
+   adev->umc.ras_funcs = &umc_v6_7_ras_funcs;
+   if (1 & adev->smuio.funcs->get_die_id(adev))
+   adev->umc.channel_idx_tbl = 
&umc_v6_7_channel_idx_tbl_first[0][0];
+   else
+   adev->umc.channel_idx_tbl = 
&umc_v6_7_channel_idx_tbl_second[0][0];
+   break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index 3a8f787374c0..7da12110425c 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -28,6 +28,21 @@
 #include "umc/umc_6_7_0_offset.h"
 #include "umc/umc_6_7_0_sh_mask.h"
 
+const uint32_t
+   
umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM]
 = {
+   {28, 12, 6, 22},{19, 3, 9, 25},
+   {20, 4, 30, 14},{11, 27, 1, 17},
+   {24, 8, 2, 18}, {15, 31, 5, 21},
+   {16, 0, 26, 10},{7, 23, 29, 13}
+};
+const uint32_t
+   
umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM]
 = {
+   {19, 3, 9, 25}, {28, 12, 6, 22},
+   {11, 27, 1, 17},{20, 4, 30, 14},
+   {15, 31, 5, 21},{24, 8, 2, 18},
+   {7, 23, 29, 13},{16, 0, 26, 10}
+};
+
 static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev,
  uint32_t umc_inst,
  uint32_t ch_inst)
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h 
b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
index 4eb85f247e96..aa282687e0e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
@@ -32,6 +32,18 @@
 
 #define UMC_V6_7_INST_DIST 0x4
 
+/* number of umc channel instance with memory map register access */
+#define UMC_V6_7_CHANNEL_INSTANCE_NUM  4
+/* number of umc instance with memory map register access */
+#define UMC_V6_7_UMC_INSTANCE_NUM  8
+/* total channel instances in one umc block */
+#define UMC_V6_7_TOTAL_CHANNEL_NUM (UMC_V6_7_CHANNEL_INSTANCE_NUM * 
UMC_V6_7_UMC_INSTANCE_NUM)
+/* UMC regiser per channel offset */
+#define UMC_V6_7_PER_CHANNEL_OFFSET0x400
 extern const struct amdgpu_umc_ras_funcs umc_v6_7_ras_funcs;
+extern const uint32_t
+   
+umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHA
+NNEL_INSTANCE_NUM];
+extern const uint32_t
+   
+umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHAN
+NEL_INSTANCE_NUM];
 
 #endif
--
2.17.1
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[PATCH Review 1/1] drm/amdgpu: initialize umc ras function

2021-07-08 Thread Stanley . Yang 
From: John Clements 

support umc ras function initialization for aldebaran

Change-Id: I84155d4d3eaae86a8c1bd2331b1964946c47f6da
Signed-off-by: John Clements 
Signed-off-by: Stanley.Yang 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 13 +
 drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 15 +++
 drivers/gpu/drm/amd/amdgpu/umc_v6_7.h | 12 
 3 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 3332c9e0a4e2..42d7244573b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -53,6 +53,7 @@
 #include "mmhub_v1_7.h"
 #include "umc_v6_1.h"
 #include "umc_v6_0.h"
+#include "umc_v6_7.h"
 #include "hdp_v4_0.h"
 
 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
@@ -1163,6 +1164,18 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device 
*adev)
adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
break;
+   case CHIP_ALDEBARAN:
+   adev->umc.max_ras_err_cnt_per_query = 
UMC_V6_7_TOTAL_CHANNEL_NUM;
+   adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
+   adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
+   adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
+   if (!adev->gmc.xgmi.connected_to_cpu)
+   adev->umc.ras_funcs = &umc_v6_7_ras_funcs;
+   if (1 & adev->smuio.funcs->get_die_id(adev))
+   adev->umc.channel_idx_tbl = 
&umc_v6_7_channel_idx_tbl_first[0][0];
+   else
+   adev->umc.channel_idx_tbl = 
&umc_v6_7_channel_idx_tbl_second[0][0];
+   break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index 3a8f787374c0..7da12110425c 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -28,6 +28,21 @@
 #include "umc/umc_6_7_0_offset.h"
 #include "umc/umc_6_7_0_sh_mask.h"
 
+const uint32_t
+   
umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM]
 = {
+   {28, 12, 6, 22},{19, 3, 9, 25},
+   {20, 4, 30, 14},{11, 27, 1, 17},
+   {24, 8, 2, 18}, {15, 31, 5, 21},
+   {16, 0, 26, 10},{7, 23, 29, 13}
+};
+const uint32_t
+   
umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM]
 = {
+   {19, 3, 9, 25}, {28, 12, 6, 22},
+   {11, 27, 1, 17},{20, 4, 30, 14},
+   {15, 31, 5, 21},{24, 8, 2, 18},
+   {7, 23, 29, 13},{16, 0, 26, 10}
+};
+
 static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev,
  uint32_t umc_inst,
  uint32_t ch_inst)
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h 
b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
index 4eb85f247e96..aa282687e0e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
@@ -32,6 +32,18 @@
 
 #define UMC_V6_7_INST_DIST 0x4
 
+/* number of umc channel instance with memory map register access */
+#define UMC_V6_7_CHANNEL_INSTANCE_NUM  4
+/* number of umc instance with memory map register access */
+#define UMC_V6_7_UMC_INSTANCE_NUM  8
+/* total channel instances in one umc block */
+#define UMC_V6_7_TOTAL_CHANNEL_NUM (UMC_V6_7_CHANNEL_INSTANCE_NUM * 
UMC_V6_7_UMC_INSTANCE_NUM)
+/* UMC regiser per channel offset */
+#define UMC_V6_7_PER_CHANNEL_OFFSET0x400
 extern const struct amdgpu_umc_ras_funcs umc_v6_7_ras_funcs;
+extern const uint32_t
+   
umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];
+extern const uint32_t
+   
umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];
 
 #endif
-- 
2.17.1

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