Re: [PATCH libdrm] headers: Sync {amdgpu,radeon}_drm.h with the kernel v2

[Emil Velikov]

On 9 January 2017 at 18:34, Andres Rodriguez  wrote:
> Generated using make headers_install from:
> airlied/drm-next 3806a27 Merge tag 'drm-misc-next-2016-12-30' ...
> +
> drm/radeon: define RADEON_TILING_R600_NO_SCANOUT
>
> By adding RADEON_TILING_R600_NO_SCANOUT to the kernel tree we no longer
> need to maintain this define on radeon_drm.h manually.
>
> v2: Add RADEON_TILING_R600_NO_SCANOUT to the kernel tree instead of
> manually re-adding it.
>
Please hold this off for a bit until the fix lands in airlied/drm-next.

Thanks!
Emil
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[PATCH libdrm] headers: Sync {amdgpu, radeon}_drm.h with the kernel v2

[Andres Rodriguez]

Generated using make headers_install from:
airlied/drm-next 3806a27 Merge tag 'drm-misc-next-2016-12-30' ...
+
drm/radeon: define RADEON_TILING_R600_NO_SCANOUT

By adding RADEON_TILING_R600_NO_SCANOUT to the kernel tree we no longer
need to maintain this define on radeon_drm.h manually.

v2: Add RADEON_TILING_R600_NO_SCANOUT to the kernel tree instead of
manually re-adding it.

Signed-off-by: Andres Rodriguez 
---
 include/drm/README   |   7 +-
 include/drm/amdgpu_drm.h | 387 +--
 include/drm/radeon_drm.h | 130 
 3 files changed, 308 insertions(+), 216 deletions(-)

diff --git a/include/drm/README b/include/drm/README
index a50b02c..fc782be 100644
--- a/include/drm/README
+++ b/include/drm/README
@@ -94,10 +94,6 @@ Status: ?
 Promote to fixed size ints, which match the current (32bit) ones.
 
 
-amdgpu_drm.h
- - Using the stdint.h uint*_t over the respective __u* ones
-Status: Trivial.
-
 drm_mode.h
  - Missing DPI encode/connector pair.
 Status: Trivial.
@@ -123,8 +119,7 @@ r128_drm.h
  - Broken compat ioctls.
 
 radeon_drm.h
- - Missing RADEON_TILING_R600_NO_SCANOUT, CIK_TILE_MODE_*, broken UMS ioctls,
-using stdint types.
+ - Missing CIK_TILE_MODE_*, broken UMS ioctls.
  - Both kernel and libdrm: missing padding -
 drm_radeon_gem_{create,{g,s}et_tiling,set_domain} others ?
 Status: ?
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d8f2497..3961836 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -50,6 +50,7 @@ extern "C" {
 #define DRM_AMDGPU_WAIT_CS 0x09
 #define DRM_AMDGPU_GEM_OP  0x10
 #define DRM_AMDGPU_GEM_USERPTR 0x11
+#define DRM_AMDGPU_WAIT_FENCES 0x12
 
 #define DRM_IOCTL_AMDGPU_GEM_CREATEDRM_IOWR(DRM_COMMAND_BASE + 
DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
 #define DRM_IOCTL_AMDGPU_GEM_MMAP  DRM_IOWR(DRM_COMMAND_BASE + 
DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -63,6 +64,7 @@ extern "C" {
 #define DRM_IOCTL_AMDGPU_WAIT_CS   DRM_IOWR(DRM_COMMAND_BASE + 
DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
 #define DRM_IOCTL_AMDGPU_GEM_OPDRM_IOWR(DRM_COMMAND_BASE + 
DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
 #define DRM_IOCTL_AMDGPU_GEM_USERPTR   DRM_IOWR(DRM_COMMAND_BASE + 
DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
+#define DRM_IOCTL_AMDGPU_WAIT_FENCES   DRM_IOWR(DRM_COMMAND_BASE + 
DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
 
 #define AMDGPU_GEM_DOMAIN_CPU  0x1
 #define AMDGPU_GEM_DOMAIN_GTT  0x2
@@ -79,22 +81,26 @@ extern "C" {
 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
 /* Flag that the memory should be in VRAM and cleared */
 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
+/* Flag that create shadow bo(GTT) while allocating vram bo */
+#define AMDGPU_GEM_CREATE_SHADOW   (1 << 4)
+/* Flag that allocating the BO should use linear VRAM */
+#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS  (1 << 5)
 
 struct drm_amdgpu_gem_create_in  {
/** the requested memory size */
-   uint64_t bo_size;
+   __u64 bo_size;
/** physical start_addr alignment in bytes for some HW requirements */
-   uint64_t alignment;
+   __u64 alignment;
/** the requested memory domains */
-   uint64_t domains;
+   __u64 domains;
/** allocation flags */
-   uint64_t domain_flags;
+   __u64 domain_flags;
 };
 
 struct drm_amdgpu_gem_create_out  {
/** returned GEM object handle */
-   uint32_t handle;
-   uint32_t _pad;
+   __u32 handle;
+   __u32 _pad;
 };
 
 union drm_amdgpu_gem_create {
@@ -111,28 +117,28 @@ union drm_amdgpu_gem_create {
 
 struct drm_amdgpu_bo_list_in {
/** Type of operation */
-   uint32_t operation;
+   __u32 operation;
/** Handle of list or 0 if we want to create one */
-   uint32_t list_handle;
+   __u32 list_handle;
/** Number of BOs in list  */
-   uint32_t bo_number;
+   __u32 bo_number;
/** Size of each element describing BO */
-   uint32_t bo_info_size;
+   __u32 bo_info_size;
/** Pointer to array describing BOs */
-   uint64_t bo_info_ptr;
+   __u64 bo_info_ptr;
 };
 
 struct drm_amdgpu_bo_list_entry {
/** Handle of BO */
-   uint32_t bo_handle;
+   __u32 bo_handle;
/** New (if specified) BO priority to be used during migration */
-   uint32_t bo_priority;
+   __u32 bo_priority;
 };
 
 struct drm_amdgpu_bo_list_out {
/** Handle of resource list  */
-   uint32_t list_handle;
-   uint32_t _pad;
+   __u32 list_handle;
+   __u32 _pad;
 };
 
 union drm_amdgpu_bo_list {
@@ -156,26 +162,26 @@ union drm_amdgpu_bo_list {
 
 struct drm_amdgpu_ctx_in {
/** AMDGPU_CTX_OP_* */
-   uint32_top;
+   __u32   op;
/** For future use, no flags defined so far */
-   uint32_t