[PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10
v2: set average clock value on level 1 when current clock equal min or max clock (fine grained dpm support). the navi10 gfxclk (sclk) support fine grained DPM, so use level 1 to show current dpm freq in sysfs pp_dpm_xxx Change-Id: I14daa6e30c52c89795708ec06660862bb4591036 Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 47 +++--- 1 file changed, 41 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 895a4e592d5a..1f721b85c0f6 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -627,11 +627,26 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, return ret; } +static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) +{ + PPTable_t *pptable = smu->smu_table.driver_pptable; + DpmDescriptor_t *dpm_desc = NULL; + uint32_t clk_index = 0; + + clk_index = smu_clk_get_index(smu, clk_type); + dpm_desc = &pptable->DpmDescriptor[clk_index]; + + /* 0 - Fine grained DPM, 1 - Discrete DPM */ + return dpm_desc->SnapToDiscrete == 0 ? true : false; +} + static int navi10_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) { int i, size = 0, ret = 0; uint32_t cur_value = 0, value = 0, count = 0; + uint32_t freq_values[3] = {0}; + uint32_t mark_index = 0; switch (clk_type) { case SMU_GFXCLK: @@ -644,22 +659,42 @@ static int navi10_print_clk_levels(struct smu_context *smu, ret = smu_get_current_clk_freq(smu, clk_type, &cur_value); if (ret) return size; + /* 10KHz -> MHz */ cur_value = cur_value / 100; - size += sprintf(buf, "current clk: %uMhz\n", cur_value); - ret = smu_get_dpm_level_count(smu, clk_type, &count); if (ret) return size; - for (i = 0; i < count; i++) { - ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value); + if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { + for (i = 0; i < count; i++) { + ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value); + if (ret) + return size; + + size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, + cur_value == value ? "*" : ""); + } + } else { + ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); + if (ret) + return size; + ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); if (ret) return size; - size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, - cur_value == value ? "*" : ""); + freq_values[1] = cur_value; + mark_index = cur_value == freq_values[0] ? 0 : +cur_value == freq_values[2] ? 2 : 1; + if (mark_index != 1) + freq_values[1] = (freq_values[0] + freq_values[2]) / 2; + + for (i = 0; i < 3; i++) { + size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i], + i == mark_index ? "*" : ""); + } + } break; default: -- 2.22.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10
Reviewed-by: Kenneth Feng -Original Message- From: Wang, Kevin(Yang) Sent: Thursday, July 18, 2019 5:43 PM To: amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth ; Quan, Evan ; Huang, Ray ; Xu, Feifei ; Wang, Kevin(Yang) Subject: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10 v2: set average clock value on level 1 when current clock equal min or max clock (fine grained dpm support). the navi10 gfxclk (sclk) support fine grained DPM, so use level 1 to show current dpm freq in sysfs pp_dpm_xxx Change-Id: I14daa6e30c52c89795708ec06660862bb4591036 Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 47 +++--- 1 file changed, 41 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 895a4e592d5a..1f721b85c0f6 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -627,11 +627,26 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, return ret; } +static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, +enum smu_clk_type clk_type) { + PPTable_t *pptable = smu->smu_table.driver_pptable; + DpmDescriptor_t *dpm_desc = NULL; + uint32_t clk_index = 0; + + clk_index = smu_clk_get_index(smu, clk_type); + dpm_desc = &pptable->DpmDescriptor[clk_index]; + + /* 0 - Fine grained DPM, 1 - Discrete DPM */ + return dpm_desc->SnapToDiscrete == 0 ? true : false; } + static int navi10_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) { int i, size = 0, ret = 0; uint32_t cur_value = 0, value = 0, count = 0; + uint32_t freq_values[3] = {0}; + uint32_t mark_index = 0; switch (clk_type) { case SMU_GFXCLK: @@ -644,22 +659,42 @@ static int navi10_print_clk_levels(struct smu_context *smu, ret = smu_get_current_clk_freq(smu, clk_type, &cur_value); if (ret) return size; + /* 10KHz -> MHz */ cur_value = cur_value / 100; - size += sprintf(buf, "current clk: %uMhz\n", cur_value); - ret = smu_get_dpm_level_count(smu, clk_type, &count); if (ret) return size; - for (i = 0; i < count; i++) { - ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value); + if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { + for (i = 0; i < count; i++) { + ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value); + if (ret) + return size; + + size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, + cur_value == value ? "*" : ""); + } + } else { + ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); + if (ret) + return size; + ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, +&freq_values[2]); if (ret) return size; - size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, - cur_value == value ? "*" : ""); + freq_values[1] = cur_value; + mark_index = cur_value == freq_values[0] ? 0 : +cur_value == freq_values[2] ? 2 : 1; + if (mark_index != 1) + freq_values[1] = (freq_values[0] + freq_values[2]) / 2; + + for (i = 0; i < 3; i++) { + size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i], + i == mark_index ? "*" : ""); + } + } break; default: -- 2.22.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10
reviewed-by: Evan Quan 获取 Outlook for iOS<https://aka.ms/o0ukef> 发件人: Feng, Kenneth 发送时间: Thursday, July 18, 2019 5:49:56 PM 收件人: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org 抄送: Quan, Evan ; Huang, Ray ; Xu, Feifei 主题: RE: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10 Reviewed-by: Kenneth Feng -Original Message- From: Wang, Kevin(Yang) Sent: Thursday, July 18, 2019 5:43 PM To: amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth ; Quan, Evan ; Huang, Ray ; Xu, Feifei ; Wang, Kevin(Yang) Subject: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10 v2: set average clock value on level 1 when current clock equal min or max clock (fine grained dpm support). the navi10 gfxclk (sclk) support fine grained DPM, so use level 1 to show current dpm freq in sysfs pp_dpm_xxx Change-Id: I14daa6e30c52c89795708ec06660862bb4591036 Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 47 +++--- 1 file changed, 41 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 895a4e592d5a..1f721b85c0f6 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -627,11 +627,26 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, return ret; } +static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, +enum smu_clk_type clk_type) { + PPTable_t *pptable = smu->smu_table.driver_pptable; + DpmDescriptor_t *dpm_desc = NULL; + uint32_t clk_index = 0; + + clk_index = smu_clk_get_index(smu, clk_type); + dpm_desc = &pptable->DpmDescriptor[clk_index]; + + /* 0 - Fine grained DPM, 1 - Discrete DPM */ + return dpm_desc->SnapToDiscrete == 0 ? true : false; } + static int navi10_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) { int i, size = 0, ret = 0; uint32_t cur_value = 0, value = 0, count = 0; + uint32_t freq_values[3] = {0}; + uint32_t mark_index = 0; switch (clk_type) { case SMU_GFXCLK: @@ -644,22 +659,42 @@ static int navi10_print_clk_levels(struct smu_context *smu, ret = smu_get_current_clk_freq(smu, clk_type, &cur_value); if (ret) return size; + /* 10KHz -> MHz */ cur_value = cur_value / 100; - size += sprintf(buf, "current clk: %uMhz\n", cur_value); - ret = smu_get_dpm_level_count(smu, clk_type, &count); if (ret) return size; - for (i = 0; i < count; i++) { - ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value); + if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { + for (i = 0; i < count; i++) { + ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value); + if (ret) + return size; + + size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, + cur_value == value ? "*" : ""); + } + } else { + ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); + if (ret) + return size; + ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, +&freq_values[2]); if (ret) return size; - size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, - cur_value == value ? "*" : ""); + freq_values[1] = cur_value; + mark_index = cur_value == freq_values[0] ? 0 : +cur_value == freq_values[2] ? 2 : 1; + if (mark_index != 1) + freq_values[1] = (freq_values[0] + freq_values[2]) / 2; + + for (i = 0; i < 3; i++) { + size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i], + i == mark_index ? "*" : ""); + } + } break; default: -- 2.22.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10
> -Original Message- > From: Wang, Kevin(Yang) > Sent: Thursday, July 18, 2019 5:43 PM > To: amd-gfx@lists.freedesktop.org > Cc: Feng, Kenneth ; Quan, Evan > ; Huang, Ray ; Xu, Feifei > ; Wang, Kevin(Yang) > Subject: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format > for navi10 > > v2: > set average clock value on level 1 when current clock equal min or max clock > (fine grained dpm support). > > the navi10 gfxclk (sclk) support fine grained DPM, so use level 1 to show > current dpm freq in sysfs pp_dpm_xxx > > Change-Id: I14daa6e30c52c89795708ec06660862bb4591036 > Signed-off-by: Kevin Wang Acked-by: Huang Rui > --- > drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 47 +++- > -- > 1 file changed, 41 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > index 895a4e592d5a..1f721b85c0f6 100644 > --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > @@ -627,11 +627,26 @@ static int > navi10_get_current_clk_freq_by_table(struct smu_context *smu, > return ret; > } > > +static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, > +enum smu_clk_type clk_type) { > + PPTable_t *pptable = smu->smu_table.driver_pptable; > + DpmDescriptor_t *dpm_desc = NULL; > + uint32_t clk_index = 0; > + > + clk_index = smu_clk_get_index(smu, clk_type); > + dpm_desc = &pptable->DpmDescriptor[clk_index]; > + > + /* 0 - Fine grained DPM, 1 - Discrete DPM */ > + return dpm_desc->SnapToDiscrete == 0 ? true : false; } > + > static int navi10_print_clk_levels(struct smu_context *smu, > enum smu_clk_type clk_type, char *buf) { > int i, size = 0, ret = 0; > uint32_t cur_value = 0, value = 0, count = 0; > + uint32_t freq_values[3] = {0}; > + uint32_t mark_index = 0; > > switch (clk_type) { > case SMU_GFXCLK: > @@ -644,22 +659,42 @@ static int navi10_print_clk_levels(struct > smu_context *smu, > ret = smu_get_current_clk_freq(smu, clk_type, &cur_value); > if (ret) > return size; > + > /* 10KHz -> MHz */ > cur_value = cur_value / 100; > > - size += sprintf(buf, "current clk: %uMhz\n", cur_value); > - > ret = smu_get_dpm_level_count(smu, clk_type, &count); > if (ret) > return size; > > - for (i = 0; i < count; i++) { > - ret = smu_get_dpm_freq_by_index(smu, clk_type, i, > &value); > + if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { > + for (i = 0; i < count; i++) { > + ret = smu_get_dpm_freq_by_index(smu, > clk_type, i, &value); > + if (ret) > + return size; > + > + size += sprintf(buf + size, "%d: %uMhz %s\n", > i, value, > + cur_value == value ? "*" : ""); > + } > + } else { > + ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, > &freq_values[0]); > + if (ret) > + return size; > + ret = smu_get_dpm_freq_by_index(smu, clk_type, > count - 1, > +&freq_values[2]); > if (ret) > return size; > > - size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, > - cur_value == value ? "*" : ""); > + freq_values[1] = cur_value; > + mark_index = cur_value == freq_values[0] ? 0 : > + cur_value == freq_values[2] ? 2 : 1; > + if (mark_index != 1) > + freq_values[1] = (freq_values[0] + > freq_values[2]) / 2; > + > + for (i = 0; i < 3; i++) { > + size += sprintf(buf + size, "%d: %uMhz %s\n", > i, freq_values[i], > + i == mark_index ? "*" : ""); > + } > + > } > break; > default: > -- > 2.22.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx