RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only] Hi Li, > -Original Message- > From: Ma, Li > Sent: Monday, July 1, 2024 9:14 PM > To: Huang, Tim ; amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Zhang, Yifan > > Subject: RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels > for SMU v14.0.0 and v14.0.1 > > [AMD Official Use Only - AMD Internal Distribution Only] > > Hi Tim, > > > -Original Message- > > From: Huang, Tim > > Sent: Monday, July 1, 2024 7:32 PM > > To: Ma, Li ; amd-gfx@lists.freedesktop.org > > Cc: Deucher, Alexander ; Zhang, Yifan > > > > Subject: RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile > > levels for SMU v14.0.0 and v14.0.1 > > > > [AMD Official Use Only - AMD Internal Distribution Only] > > > > Hi Li, > > > > > -Original Message- > > > From: Ma, Li > > > Sent: Monday, July 1, 2024 6:44 PM > > > To: amd-gfx@lists.freedesktop.org > > > Cc: Deucher, Alexander ; Zhang, Yifan > > > ; Huang, Tim ; Ma, Li > > > > > > Subject: [PATCH v2] drm/amd/swsmu: enable more Pstates profile > > > levels for SMU v14.0.0 and v14.0.1 > > > > > > This patch enables following UMD stable Pstates profile levels for > > > power_dpm_force_performance_level interface. > > > > > > - profile_peak > > > - profile_min_mclk > > > - profile_min_sclk > > > - profile_standard > > > > > > Signed-off-by: Li Ma > > > --- > > > .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 138 > > > +- > > > 1 file changed, 131 insertions(+), 7 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > > b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > > index 3a9d58c036ea..72fca481dec1 100644 > > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > > @@ -65,6 +65,10 @@ > > > > > > #define SMU_MALL_PG_CONFIG_DEFAULT > > > SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON > > > > > > +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700 > > > +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678 > > > +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800 > > > + > > > #define FEATURE_MASK(feature) (1ULL << feature) #define > > > SMC_DPM_FEATURE ( \ > > > FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -818,9 +822,11 > @@ > > > static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu, > > > break; > > > case SMU_MCLK: > > > case SMU_UCLK: > > > - case SMU_FCLK: > > > max_dpm_level = 0; > > > break; > > > + case SMU_FCLK: > > > + max_dpm_level = > clk_table->NumFclkLevelsEnabled - 1; > > > + break; > > > case SMU_SOCCLK: > > > max_dpm_level = > clk_table->NumSocClkLevelsEnabled - 1; > > > break; > > > @@ -855,7 +861,7 @@ static int > > > smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu, > > > min_dpm_level = > clk_table->NumMemPstatesEnabled - 1; > > > break; > > > case SMU_FCLK: > > > - min_dpm_level = > clk_table->NumFclkLevelsEnabled - 1; > > > + min_dpm_level = 0; > > > break; > > > case SMU_SOCCLK: > > > min_dpm_level = 0; @@ -936,9 +942,11 @@ > static > > > int smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu, > > > break; > > > case SMU_MCLK: > > > case SMU_UCLK: > > > - case SMU_FCLK: > > > max_dpm_level = 0; > > > break; > > > + case SMU_FCLK: > > > + max_dpm_level = > clk_table->NumFclkLevelsEnabled - 1; > > > + break; > > > case SMU_SOCCLK: > > > max_dpm_level = > clk_table->NumSocClkLevelsEnabled - 1; > > > break; > > > @@ -969,7 +977,7 @@
RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only] Hi Tim, > -Original Message- > From: Huang, Tim > Sent: Monday, July 1, 2024 7:32 PM > To: Ma, Li ; amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Zhang, Yifan > > Subject: RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels > for SMU v14.0.0 and v14.0.1 > > [AMD Official Use Only - AMD Internal Distribution Only] > > Hi Li, > > > -Original Message- > > From: Ma, Li > > Sent: Monday, July 1, 2024 6:44 PM > > To: amd-gfx@lists.freedesktop.org > > Cc: Deucher, Alexander ; Zhang, Yifan > > ; Huang, Tim ; Ma, Li > > > > Subject: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for > > SMU v14.0.0 and v14.0.1 > > > > This patch enables following UMD stable Pstates profile levels for > > power_dpm_force_performance_level interface. > > > > - profile_peak > > - profile_min_mclk > > - profile_min_sclk > > - profile_standard > > > > Signed-off-by: Li Ma > > --- > > .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 138 > > +- > > 1 file changed, 131 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > index 3a9d58c036ea..72fca481dec1 100644 > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > @@ -65,6 +65,10 @@ > > > > #define SMU_MALL_PG_CONFIG_DEFAULT > > SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON > > > > +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700 > > +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678 > > +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800 > > + > > #define FEATURE_MASK(feature) (1ULL << feature) #define > > SMC_DPM_FEATURE ( \ > > FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -818,9 +822,11 @@ > > static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu, > > break; > > case SMU_MCLK: > > case SMU_UCLK: > > - case SMU_FCLK: > > max_dpm_level = 0; > > break; > > + case SMU_FCLK: > > + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1; > > + break; > > case SMU_SOCCLK: > > max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1; > > break; > > @@ -855,7 +861,7 @@ static int > > smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu, > > min_dpm_level = clk_table->NumMemPstatesEnabled - 1; > > break; > > case SMU_FCLK: > > - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1; > > + min_dpm_level = 0; > > break; > > case SMU_SOCCLK: > > min_dpm_level = 0; > > @@ -936,9 +942,11 @@ static int > > smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu, > > break; > > case SMU_MCLK: > > case SMU_UCLK: > > - case SMU_FCLK: > > max_dpm_level = 0; > > break; > > + case SMU_FCLK: > > + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1; > > + break; > > case SMU_SOCCLK: > > max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1; > > break; > > @@ -969,7 +977,7 @@ static int > > smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu, > > min_dpm_level = clk_table->NumMemPstatesEnabled - 1; > > break; > > case SMU_FCLK: > > - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1; > > + min_dpm_level = 0; > > break; > > case SMU_SOCCLK: > > min_dpm_level = 0; > > @@ -1268,13 +1276,67 @@ static int smu_v14_0_0_force_clk_levels(struct > > smu_context *smu, > > return ret; > > } > > > > -static int smu_v14_0_0_set_performance_level(struct smu_context *smu, > > +static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context > > *smu, > > +
RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Li,
> -Original Message-
> From: Ma, Li
> Sent: Monday, July 1, 2024 6:44 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
> ; Huang, Tim ; Ma, Li
>
> Subject: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for
> SMU v14.0.0 and v14.0.1
>
> This patch enables following UMD stable Pstates profile levels for
> power_dpm_force_performance_level interface.
>
> - profile_peak
> - profile_min_mclk
> - profile_min_sclk
> - profile_standard
>
> Signed-off-by: Li Ma
> ---
> .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 138
> +-
> 1 file changed, 131 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> index 3a9d58c036ea..72fca481dec1 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> @@ -65,6 +65,10 @@
>
> #define SMU_MALL_PG_CONFIG_DEFAULT
> SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
>
> +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
> +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
> +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
> +
> #define FEATURE_MASK(feature) (1ULL << feature) #define
> SMC_DPM_FEATURE ( \
> FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -818,9 +822,11 @@
> static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -855,7 +861,7 @@ static int
> smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -936,9 +942,11 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -969,7 +977,7 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -1268,13 +1276,67 @@ static int smu_v14_0_0_force_clk_levels(struct
> smu_context *smu,
> return ret;
> }
>
> -static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
> +static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context
> *smu,
> + enum amd_dpm_forced_level level,
> + enum smu_clk_type clk_type,
> + uint32_t *min_clk,
> + uint32_t *max_clk)
> +{
> + uint32_t clk_limit = 0;
> + int ret = 0;
> +
> + switch (clk_type) {
> + case SMU_GFXCLK:
> + case SMU_SCLK:
> + clk_limit = SMU_14_0_0_UMD_PSTATE_GFXCLK;
> + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> + smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK,
> NULL, _limit);
> + else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
> + smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK,
> _limit, NULL);
> + break;
> + case SMU_SOCCLK:
>
[PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
This patch enables following UMD stable Pstates profile
levels for power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: Li Ma
---
.../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 138 +-
1 file changed, 131 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
index 3a9d58c036ea..72fca481dec1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
@@ -65,6 +65,10 @@
#define SMU_MALL_PG_CONFIG_DEFAULT SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
+#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
+#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
+#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
+
#define FEATURE_MASK(feature) (1ULL << feature)
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@@ -818,9 +822,11 @@ static int smu_v14_0_1_get_dpm_ultimate_freq(struct
smu_context *smu,
break;
case SMU_MCLK:
case SMU_UCLK:
- case SMU_FCLK:
max_dpm_level = 0;
break;
+ case SMU_FCLK:
+ max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
+ break;
case SMU_SOCCLK:
max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
break;
@@ -855,7 +861,7 @@ static int smu_v14_0_1_get_dpm_ultimate_freq(struct
smu_context *smu,
min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
break;
case SMU_FCLK:
- min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
+ min_dpm_level = 0;
break;
case SMU_SOCCLK:
min_dpm_level = 0;
@@ -936,9 +942,11 @@ static int smu_v14_0_0_get_dpm_ultimate_freq(struct
smu_context *smu,
break;
case SMU_MCLK:
case SMU_UCLK:
- case SMU_FCLK:
max_dpm_level = 0;
break;
+ case SMU_FCLK:
+ max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
+ break;
case SMU_SOCCLK:
max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
break;
@@ -969,7 +977,7 @@ static int smu_v14_0_0_get_dpm_ultimate_freq(struct
smu_context *smu,
min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
break;
case SMU_FCLK:
- min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
+ min_dpm_level = 0;
break;
case SMU_SOCCLK:
min_dpm_level = 0;
@@ -1268,13 +1276,67 @@ static int smu_v14_0_0_force_clk_levels(struct
smu_context *smu,
return ret;
}
-static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
+static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ enum smu_clk_type clk_type,
+ uint32_t *min_clk,
+ uint32_t *max_clk)
+{
+ uint32_t clk_limit = 0;
+ int ret = 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ clk_limit = SMU_14_0_0_UMD_PSTATE_GFXCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK,
NULL, _limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+ smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK,
_limit, NULL);
+ break;
+ case SMU_SOCCLK:
+ clk_limit = SMU_14_0_0_UMD_PSTATE_SOCCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK,
NULL, _limit);
+ break;
+ case SMU_FCLK:
+ clk_limit = SMU_14_0_0_UMD_PSTATE_FCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK,
NULL, _limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
+ smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK,
_limit, NULL);
+ break;
+ case SMU_VCLK:
+ smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
_limit);
+ break;
+ case SMU_VCLK1:
+
