[PATCH v2] drm/amdgpu: access RLC_SPM_MC_CNTL through MMIO in SRIOV runtime

[ZhenGuo Yin]

Register RLC_SPM_MC_CNTL is not blocked by L1 policy, VF can
directly access it through MMIO during SRIOV runtime.

v2: use SOC15 interface to access registers

Signed-off-by: ZhenGuo Yin <zhenguo....@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +++----------
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 13 +++----------
 2 files changed, 6 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 0aee9c8288a2..6ccde07ed63e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7897,22 +7897,15 @@ static int gfx_v10_0_update_gfx_clock_gating(struct 
amdgpu_device *adev,
 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
                                               unsigned int vmid)
 {
-       u32 reg, data;
+       u32 data;
 
        /* not for *_SOC15 */
-       reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
-       if (amdgpu_sriov_is_pp_one_vf(adev))
-               data = RREG32_NO_KIQ(reg);
-       else
-               data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
+       data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL);
 
        data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
        data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << 
RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
 
-       if (amdgpu_sriov_is_pp_one_vf(adev))
-               WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
-       else
-               WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
+       WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
 }
 
 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int 
vmid)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index b0c32521efdc..337ed771605f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4984,23 +4984,16 @@ static int gfx_v11_0_update_gfx_clock_gating(struct 
amdgpu_device *adev,
 
 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned 
vmid)
 {
-       u32 reg, data;
+       u32 data;
 
        amdgpu_gfx_off_ctrl(adev, false);
 
-       reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
-       if (amdgpu_sriov_is_pp_one_vf(adev))
-               data = RREG32_NO_KIQ(reg);
-       else
-               data = RREG32(reg);
+       data = RREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL);
 
        data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
        data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << 
RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
 
-       if (amdgpu_sriov_is_pp_one_vf(adev))
-               WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
-       else
-               WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
+       WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
 
        amdgpu_gfx_off_ctrl(adev, true);
 }
-- 
2.35.1