RE: [PATCH v2 1/2] drm/amd/amdgpu: fix psp tmr bo pin count leak in SRIOV

2021-12-14 Thread Liu, Shaoyun
[AMD Official Use Only]

These workaround code looks confusing.  For PSP TMR , I think guest side should 
avoid to load it totally  since it's loaded in host side.  For gart table , in 
current  code path probably it's ok, but I think if we have  a correct sequence 
in SRIOV , we shouldn't have  these kinds  of workaround.  Ex .  Can  we try 
call  ip_suspend  for sriov in amdgpu_device_pre_asic_reset , so we  will have  
the  same logic as baremetal. 

Regards
Shaoyun.liu

-Original Message-
From: amd-gfx  On Behalf Of Jingwen Chen
Sent: Monday, December 13, 2021 11:18 PM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, Horace ; Chen, JingWen ; 
Liu, Monk 
Subject: [PATCH v2 1/2] drm/amd/amdgpu: fix psp tmr bo pin count leak in SRIOV

[Why]
psp tmr bo will be pinned during loading amdgpu and reset in SRIOV while only 
unpinned in unload amdgpu

[How]
add amdgpu_in_reset and sriov judgement to skip pin bo

v2: fix wrong judgement

Signed-off-by: Jingwen Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 103bcadbc8b8..4de46fcb486c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2017,12 +2017,16 @@ static int psp_hw_start(struct psp_context *psp)
return ret;
}
 
+   if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 
+   goto skip_pin_bo;
+
ret = psp_tmr_init(psp);
if (ret) {
DRM_ERROR("PSP tmr init failed!\n");
return ret;
}
 
+skip_pin_bo:
/*
 * For ASICs with DF Cstate management centralized
 * to PMFW, TMR setup should be performed after PMFW
--
2.30.2


RE: [PATCH v2 1/2] drm/amd/amdgpu: fix psp tmr bo pin count leak in SRIOV

2021-12-13 Thread Chen, Horace
[AMD Official Use Only]

Reviewed-by: Horace Chen 

-Original Message-
From: Chen, JingWen 
Sent: Tuesday, December 14, 2021 12:18 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk ; Chen, Horace ; Chen, 
JingWen 
Subject: [PATCH v2 1/2] drm/amd/amdgpu: fix psp tmr bo pin count leak in SRIOV

[Why]
psp tmr bo will be pinned during loading amdgpu and reset in SRIOV while only 
unpinned in unload amdgpu

[How]
add amdgpu_in_reset and sriov judgement to skip pin bo

v2: fix wrong judgement

Signed-off-by: Jingwen Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 103bcadbc8b8..4de46fcb486c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2017,12 +2017,16 @@ static int psp_hw_start(struct psp_context *psp)
return ret;
}

+   if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
+   goto skip_pin_bo;
+
ret = psp_tmr_init(psp);
if (ret) {
DRM_ERROR("PSP tmr init failed!\n");
return ret;
}

+skip_pin_bo:
/*
 * For ASICs with DF Cstate management centralized
 * to PMFW, TMR setup should be performed after PMFW
--
2.30.2



[PATCH v2 1/2] drm/amd/amdgpu: fix psp tmr bo pin count leak in SRIOV

2021-12-13 Thread Jingwen Chen
[Why]
psp tmr bo will be pinned during loading amdgpu and reset in SRIOV while
only unpinned in unload amdgpu

[How]
add amdgpu_in_reset and sriov judgement to skip pin bo

v2: fix wrong judgement

Signed-off-by: Jingwen Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 103bcadbc8b8..4de46fcb486c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2017,12 +2017,16 @@ static int psp_hw_start(struct psp_context *psp)
return ret;
}
 
+   if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 
+   goto skip_pin_bo;
+
ret = psp_tmr_init(psp);
if (ret) {
DRM_ERROR("PSP tmr init failed!\n");
return ret;
}
 
+skip_pin_bo:
/*
 * For ASICs with DF Cstate management centralized
 * to PMFW, TMR setup should be performed after PMFW
-- 
2.30.2